Intermediate frequency isolation circuit

Abstract

The utility model relates to an intermediate frequency isolation circuit, comprising a high speed DAC circuit, a waveform buffer circuit, a DC pulse conversion AC circuit and a power amplification and isolation circuit, the high speed DAC circuit is connected with the waveform buffer circuit, and the waveform buffer circuit is also connected with the DC pulse conversion AC circuit. The high-speed DAC circuit comprises a chip U1 and a capacitor C4, the high-speed DAC circuit is used, generated waveform frequency errors are further reduced, precision is improved, buffering is added, rail-to-rail operational amplifiers are used, loading capacity is improved, waveform distortion is reduced, and the high-speed DAC circuit is high in reliability and high in reliability. The meticulously designed pulse transformer can electrically isolate the front and rear poles, the isolation voltage between the circuit behind the transformer and the load reaches 4000 V and is higher than the standard requirement, the precision of the waveform frequency is improved, the waveform distortion is further reduced, the front and rear pole circuits are electrically and completely isolated, and the product safety is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to electrical isolation technical field, especially in -frequency isolation circuit. BACKGROUND

[0002] In the field of electronic technology, intermediate frequency circuit plays a key role in signal processing and conversion, especially in radio communication and electronic equipment manufacturing. However, traditional intermediate frequency circuits often lack sufficient electrical isolation, leading to problems such as current, voltage or electromagnetic interference, affecting the stability and safety of the circuit. In order to solve these problems, the industry has begun to explore the design of intermediate frequency isolation circuit. This circuit realizes effective isolation between different parts of the circuit through special isolation elements or technology, thereby improving the overall performance and reliability of the circuit.

[0003] At present, although there are some design schemes of intermediate frequency isolation circuit, there are still problems such as unsatisfactory isolation effect and high circuit complexity, and a new type of intermediate frequency isolation circuit is needed to solve the shortcomings of the prior art. CONTENT OF THE UTILITY MODEL

[0004] The utility model proposes intermediate frequency isolation circuit to solve the problems mentioned in the prior art.

[0005] In order to achieve the above purpose, the utility model provides the following technical scheme:

[0006] The intermediate frequency isolation circuit includes a high-speed DAC circuit, a waveform buffer circuit, a direct current pulse conversion alternating current circuit and a power amplification and isolation circuit, the high-speed DAC circuit is connected with the waveform buffer circuit, the waveform buffer circuit is further connected with the direct current pulse conversion alternating current circuit, the direct current pulse conversion alternating current circuit is further connected with the power amplification and isolation circuit, the high-speed DAC circuit includes a chip U1 and a capacitor C4, the waveform buffer circuit includes a chip U7, a resistor R13, a resistor R33, a capacitor C8 and a capacitor C52, the direct current pulse conversion alternating current circuit includes a chip U4, a capacitor C2, a capacitor C6, a resistor R7, a resistor R8, a resistor R10 and a resistor R14, the power amplification and isolation circuit includes a power amplifier U12 and a pulse transformer, a pin 17 of the chip U1 is connected with a pin 18 of the chip U1, a pin 4 of the chip U1, the capacitor C4 and a 5V voltage, a pin 3 of the chip U7 is connected with the resistor R13, a pin 5 of the chip U7 is connected with the resistor R33, a pin 8 of the chip U7 is connected with the capacitor C8 and a 5V voltage, a pin 4 of the chip U7 is connected with the capacitor C52 and a 5V voltage, the other end of the capacitor C52 is grounded, the other end of the capacitor C8 is grounded, a pin 1 of the chip U4 is connected with the resistor R7, the other end of the resistor R7 is connected with the resistor R8, the resistor R10 and a pin 6 of the chip U4, a pin 7 of the chip U4 is connected with the other end of the resistor R10, a pin 8 of the chip U4 is connected with the capacitor C2, the other end of the resistor R8 and a 5V voltage, the other end of the capacitor C2 is grounded, a pin 3 of the chip U4 is connected with the capacitor C6 and a ground terminal, a pin 4 of the chip U4 is connected with the other end of the capacitor C6 and a -5V voltage, a pin 5 of the chip U4 is connected with the resistor R14, the other end of the resistor R14 is grounded, a pin 2 of the chip U4 is connected with a pin 2 of the chip U1, a pin 1 of the chip U12 is connected with one input end of the pulse transformer, a pin 2 of the chip U12 is connected with the other input end of the pulse transformer, a pin 3 of the chip U12 is connected with the resistor R46, a capacitor C29, a pin 13 of the chip U12 and a 12V voltage, a pin 6 of the chip U12 is connected with the resistor R46, a capacitor C19 and a pin 7 of the chip U12, the other end of the capacitor C19 is grounded, the other end of the capacitor C29 is grounded, and the output end of the pulse transformer is connected with a load.

[0007] As a further technical scheme of the utility model: the model number of the chip U1 is TCL7528.

[0008] As a further technical scheme of the utility model: the model number of the chip U4 is TCL2272.

[0009] As a further technical scheme of the utility model: the model number of the chip U7 is TCL2272.

[0010] As a further technical scheme of the utility model: the model number of the chip U12 is TDA7297.

[0011] In the above technical solution, the technical effect and advantages provided by the utility model are:

[0012] The utility model uses high -speed DAC, the waveform frequency error of producing further reduces, improves precision, adds buffer and uses track to track operational amplifier, improves the ability of taking load and reduces waveform distortion simultaneously, the pulse transformer of careful design can make the electrical isolation of front stage and back stage, the circuit and load isolation voltage after transformer reaches 4000V, higher than standard requirement, improve the precision of waveform frequency, further reduce waveform distortion, the front stage and back stage circuit is electrically completely isolated, improves product safety. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, the following will briefly introduce the drawings needed to be used in embodiment or prior art description, obviously, the drawings in the following description only some embodiments of the utility model, for ordinary skilled person in the art, under the premise of not paying creative labor, other drawings can also be obtained according to these drawings.

[0014] Figure 1 The circuit diagram of the intermediate frequency isolation circuit designed by the utility model is shown. DETAILED DESCRIPTION

[0015] The technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model, obviously, the described embodiments only some embodiments of the utility model, not all embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary skilled person in the art without creative labor belong to the scope of protection of the utility model.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the utility model belongs; the terms used in the specification of the utility model herein are only for the purpose of describing specific embodiments, and are not intended to limit the utility model; the term "and / or" used herein includes any and all combinations of one or more related listed items.

[0017] The utility model provides Figure 1The drawing paper shown, specifically the intermediate frequency isolation circuit, includes a high-speed DAC circuit, a waveform buffer circuit, a direct current pulse conversion alternating current circuit, and a power amplification and isolation circuit. The high-speed DAC circuit is connected to the waveform buffer circuit, the waveform buffer circuit is also connected to the direct current pulse conversion alternating current circuit, the direct current pulse conversion alternating current circuit is also connected to the power amplification and isolation circuit. The high-speed DAC circuit includes a chip U1 and a capacitor C4. The waveform buffer circuit includes a chip U7, a resistor R13, a resistor R33, a capacitor C8, and a capacitor C52. The direct current pulse conversion alternating current circuit includes a chip U4, a capacitor C2, a capacitor C6, a resistor R7, a resistor R8, a resistor R10, and a resistor R14. The power amplification and isolation circuit includes a power amplifier U12 and a pulse transformer. The pin 17 of the chip U1 is connected to the pin 18 of the chip U1, the pin 4 of the chip U1, the capacitor C4, and a 5V voltage. The pin 3 of the chip U7 is connected to the resistor R13. The pin 5 of the chip U7 is connected to the resistor R33. The pin 8 of the chip U7 is connected to the capacitor C8 and a 5V voltage. The pin 4 of the chip U7 is connected to the capacitor C52 and a 5V voltage. The other end of the capacitor C52 is grounded. The other end of the capacitor C8 is grounded. The pin 1 of the chip U4 is connected to the resistor R7. The other end of the resistor R7 is connected to the resistor R8, the resistor R10, and the pin 6 of the chip U4. The pin 7 of the chip U4 is connected to the other end of the resistor R10. The pin 8 of the chip U4 is connected to the capacitor C2, the other end of the resistor R8, and a 5V voltage. The other end of the capacitor C2 is grounded. The pin 3 of the chip U4 is connected to the capacitor C6 and a ground terminal. The pin 4 of the chip U4 is connected to the other end of the capacitor C6 and a -5V voltage. The pin 5 of the chip U4 is connected to the resistor R14. The other end of the resistor R14 is grounded. The pin 2 of the chip U4 is connected to the pin 2 of the chip U1. The pin 1 of the chip U12 is connected to one input terminal of the pulse transformer. The pin 2 of the chip U12 is connected to the other input terminal of the pulse transformer. The pin 3 of the chip U12 is connected to the resistor R46, the capacitor C29, the pin 13 of the chip U12, and a 12V voltage. The pin 6 of the chip U12 is connected to the resistor R46, the capacitor C19, and the pin 7 of the chip U12. The other end of the capacitor C19 is grounded. The other end of the capacitor C29 is grounded. The output terminal of the pulse transformer is connected to a load.

[0018] The model of the chip U1 is TCL7528. The model of the chip U4 is TCL2272. The model of the chip U7 is TCL2272. The model of the chip U12 is TDA7297.

[0019] Working principle:

[0020] The conversion time of the high-speed DAC circuit reaches the nS level, which is controlled by the MCU to generate a high-frequency basic waveform.

[0021] Waveform buffer circuit: waveform buffering, the driving ability of the waveform generated by the DAC is weak. In order to avoid distortion, a buffer is added to strengthen the driving ability of the subsequent stage.

[0022] Direct current pulse conversion alternating current circuit: direct current pulse conversion alternating current, the direct current pulse signal generated by the previous stage is converted into a pure alternating current signal, which is the basic waveform for the power amplification of the subsequent stage.

[0023] Power amplification and isolation circuit: power amplification and isolation, the alternating current signal converted by the previous stage is bridge amplified, and the high load pulse transformer behind is driven on both sides, the pulse transformer transmits the signal to the final load after voltage amplification. The pulse transformer is designed to completely isolate the signals of the previous and subsequent stages, the signal is not distorted under the maximum load condition, and the isolation voltage reaches 4000V.

[0024] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, the scope of the present application is defined by the appended claims rather than the above description, and therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application.

[0025] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment have been properly combined to form other embodiments easily understood by those skilled in the art.

Claims

1. An intermediate frequency isolation circuit comprising a high speed DAC circuit, a waveform buffer circuit, a direct current pulse to alternating current circuit and a power amplification and isolation circuit, characterized in that, The high-speed DAC circuit is connected with a waveform buffer circuit, the waveform buffer circuit is further connected with a direct current pulse to alternating current circuit, the direct current pulse to alternating current circuit is further connected with a power amplifier and isolation circuit, the high-speed DAC circuit comprises a chip U1 and a capacitor C4, the waveform buffer circuit comprises a chip U7, a resistor R13, a resistor R33, a capacitor C8 and a capacitor C52, the direct current pulse to alternating current circuit comprises a chip U4, a capacitor C2, a capacitor C6, a resistor R7, a resistor R8, a resistor R10 and a resistor R14, the power amplifier and isolation circuit comprises a power amplifier U12 and a pulse transformer, a pin 17 of the chip U1 is connected with a pin 18 of the chip U1, a pin 4 of the chip U1, the capacitor C4 and a 5V voltage, a pin 3 of the chip U7 is connected with the resistor R13, a pin 5 of the chip U7 is connected with the resistor R33, a pin 8 of the chip U7 is connected with the capacitor C8 and a 5V voltage, a pin 4 of the chip U7 is connected with the capacitor C52 and a 5V voltage, the other end of the capacitor C52 is grounded, the other end of the capacitor C8 is grounded, a pin 1 of the chip U4 is connected with the resistor R7, the other end of the resistor R7 is connected with the resistor R8, the resistor R10 and a pin 6 of the chip U4, a pin 7 of the chip U4 is connected with the other end of the resistor R10, a pin 8 of the chip U4 is connected with the capacitor C2, the other end of the resistor R8 and a 5V voltage, the other end of the capacitor C2 is grounded, a pin 3 of the chip U4 is connected with the capacitor C6 and a ground terminal, a pin 4 of the chip U4 is connected with the other end of the capacitor C6 and a -5V voltage, a pin 5 of the chip U4 is connected with the resistor R14, the other end of the resistor R14 is grounded, a pin 2 of the chip U4 is connected with a pin 2 of the chip U1, a pin 1 of the chip U12 is connected with one input terminal of the pulse transformer, a pin 2 of the chip U12 is connected with the other input terminal of the pulse transformer, a pin 3 of the chip U12 is connected with the resistor R46, a capacitor C29, a pin 13 of the chip U12 and a 12V voltage, a pin 6 of the chip U12 is connected with the resistor R46, a capacitor C19 and a pin 7 of the chip U12, the other end of the capacitor C19 is grounded, the other end of the capacitor C29 is grounded, and an output terminal of the pulse transformer is connected with a load.

2. The intermediate frequency isolation circuit of claim 1, wherein: The model of the chip U1 is TCL7528.

3. The intermediate frequency isolation circuit of claim 1, wherein: The model of the chip U4 is TCL2272.

4. The intermediate frequency isolation circuit of claim 1, wherein: The model of the chip U7 is TCL2272.

5. The intermediate frequency isolation circuit of claim 1, wherein: The model of the chip U12 is TDA7297.

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