LED chip

Abstract

The LED chip comprises a substrate, an epitaxial laminated layer arranged on the surface of one side of the substrate, a first electrode, a first transparent conductive layer, a second electrode and a second transparent conductive layer, the epitaxial laminated layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially laminated in the direction away from the substrate; the first transparent conductive layer is laminated on the partial surface, away from the substrate, of the second type semiconductor layer and is provided with a first hole for exposing the second type semiconductor layer; the second electrode covers the partial surface, deviating from the substrate, of the first transparent conductive layer and is electrically connected with the second type semiconductor layer through the first hole; the second transparent conductive layer at least covers the side wall of the second electrode and a part of the surface deviating from the substrate. A structure for clamping the second electrode through the upper layer and the lower layer is formed through the two transparent conducting layers, ohmic contact between the second electrode and the transparent conducting layers is guaranteed, adhesion between the second electrode and other film layers of the chip is improved, and the reliability of a bonding wire is improved.

Description

Technical Field

[0001] This utility model relates to the field of light-emitting diode technology, and more specifically, to an LED chip. Background Technology

[0002] LEDs have advantages such as small size, rich color range, high resolution, long lifespan, and fast response, and are widely used in various fields. While there is a general pursuit of high brightness and low cost, ensuring the reliability of LEDs is also a significant challenge in gaining market share.

[0003] Currently, conventional small-to-medium-sized LED chip structures typically involve stacking a first-type semiconductor layer, an active layer, a second-type semiconductor layer, a transparent conductive layer '03, an electrode '02, and a passivation layer '01' on a substrate. The entire chip fabrication is usually completed using four or five photolithography steps. Four photolithography steps include MESA platform fabrication, transparent conductive layer '03 fabrication, electrode '02 fabrication, and passivation layer '01 (PV) fabrication. The electrode '02 structure is as follows... Figure 1 As shown. The five-step photolithography process, based on the four-step process described above, adds an extra photolithography step because a current blocking layer '04 is added beneath the transparent conductive layer '03. The electrode '02 structure is as follows... Figure 2 As shown. In these two common chip structures, the area where electrode '02' contacts the transparent conductive layer '03 (the area circled by an ellipse in the figure) is a region where the client bonding wire is prone to failure, that is, in this region, electrode '02 is prone to detach from the transparent conductive layer '03. Utility Model Content

[0004] In view of this, the present invention provides an LED chip that ensures ohmic contact between the second electrode and the transparent conductive layer while improving the overall adhesion between the second electrode and other film layers of the chip, thereby enhancing the reliability of the bonding wire.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0006] This utility model also provides an LED chip, which includes:

[0007] Substrate;

[0008] An epitaxial stack is disposed on one side surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked along a direction away from the substrate;

[0009] The first electrode is electrically connected to the first type of semiconductor layer;

[0010] A first transparent conductive layer is stacked on the portion of the second type semiconductor layer facing away from the substrate, and a first hole is provided to expose the second type semiconductor layer;

[0011] The second electrode at least covers the portion of the first transparent conductive layer that faces away from the substrate, and is electrically connected to the second type semiconductor layer through the first hole;

[0012] A second transparent conductive layer covers at least the sidewalls of the second electrode and a portion of its surface facing away from the substrate.

[0013] Furthermore, the thickness of the first transparent conductive layer is less than the thickness of the second transparent conductive layer.

[0014] Furthermore, the second transparent conductive layer also covers at least a portion of the exposed surface of the first transparent conductive layer.

[0015] Furthermore, the second transparent conductive layer has a second hole, which exposes a portion of the surface of the second electrode facing away from the substrate;

[0016] The radius of the first hole is R1, the radius of the second hole is R2, and the radius of the second electrode is R3; wherein, R3-R1≥1um, R3-R2≥1um.

[0017] Furthermore, it also includes a passivation layer; the passivation layer covers the exposed surface of the second transparent conductive layer and the epitaxial stack.

[0018] Furthermore, the top layer metal of the second electrode is one of titanium, chromium, gold, nickel, aluminum, silver, platinum, and copper.

[0019] Furthermore, the first transparent conductive layer and the second transparent conductive layer are single metal thin films or metal oxides;

[0020] The single metal thin film is one of gold, silver, platinum, copper, aluminum, chromium, and palladium;

[0021] The metal oxide is one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride.

[0022] Furthermore, the first transparent conductive layer is fabricated using a sputtering method.

[0023] Compared with the prior art, the technical solution provided by this utility model has at least the following advantages:

[0024] The LED chip of this application includes a substrate, an epitaxial stack disposed on one surface of the substrate, a first electrode, a first transparent conductive layer, a second electrode, and a second transparent conductive layer. The epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked in a direction away from the substrate. The first electrode is electrically connected to the first type semiconductor layer. The first transparent conductive layer is stacked on a portion of the second type semiconductor layer away from the substrate and has a first hole exposing the second type semiconductor layer. The second electrode covers a portion of the first transparent conductive layer away from the substrate and is electrically connected to the second type semiconductor layer through the first hole. The second transparent conductive layer at least covers the sidewalls of the second electrode and a portion of the surface away from the substrate.

[0025] The LED chip of this application, based on the above structural design, incorporates a second transparent conductive layer that covers at least the sidewalls of the second electrode and the portion of the surface facing away from the substrate. This creates a structure where the second electrode is sandwiched between two transparent conductive layers, ensuring ohmic contact between the second electrode and the transparent conductive layer while improving the overall adhesion between the second electrode and other film layers of the chip, thus enhancing wire bonding reliability. Since the adhesion between the second type semiconductor layer and the second electrode in direct contact is greater than the adhesion between the second electrode and the transparent conductive layer, the placement of the second transparent conductive layer on the second electrode maximizes the contact area between the second electrode and the second type semiconductor layer.

[0026] The thickness of the first transparent conductive layer is less than the thickness of the second transparent conductive layer. The better the adhesion between the second electrode and the second type of semiconductor layer, the better the reliability of the LED chip.

[0027] The top metal of the second electrode is one of titanium, chromium, gold, nickel, aluminum, silver, platinum, or copper, which have strong adhesion, to enhance the adhesion between the second transparent conductive layer and the sidewall of the second electrode and the surface of the second electrode away from the substrate.

[0028] The first transparent conductive layer is fabricated using a sputtering method, which results in a higher carrier density. This improves the conductivity of the first transparent conductive layer, reduces Joule heat loss, helps lower the operating voltage of the LED chip, and improves power conversion efficiency. Furthermore, the high carrier density allows the first transparent conductive layer to be made thinner while maintaining sufficient conductivity, thereby reducing light absorption and reflection losses in the first transparent conductive layer. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a schematic cross-sectional view of an electrode structure formed by four photolithography steps in the prior art.

[0031] Figure 2 This is a schematic cross-sectional view of an electrode structure formed by five photolithography steps in the prior art.

[0032] Figure 3 This is a cross-sectional structural diagram of an LED chip according to this application;

[0033] Figure 4 This is a cross-sectional structural diagram of another LED chip in this application;

[0034] Figure 5 This is a schematic diagram showing the projected relationship between the second electrode, the first hole, and the second hole in this application;

[0035] Figure 6-14 This is a cross-sectional structural diagram of the LED chip manufacturing process in this application.

[0036] Figure label:

[0037] Passivation layer '01; Electrode '02; Transparent conductive layer '03; Current blocking layer '04;

[0038] Substrate 1; Epitaxial stack 2; Type I semiconductor layer 21; Active layer 22; Type II semiconductor layer 23; Groove 24; First electrode 3; First transparent conductive layer 4; First hole 41; Second electrode 5; Second transparent conductive layer 6; Second hole 61; Passivation layer 7; Current blocking layer 8; Total thickness D. Detailed Implementation

[0039] To make the content of this utility model clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0040] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0041] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0042] This application provides an LED chip, such as Figure 3 As shown, the LED chip includes a substrate 1, an epitaxial stack 2 disposed on one side of the substrate 1, a first electrode 3, a first transparent conductive layer 4, a second electrode 5, and a second transparent conductive layer 6. The epitaxial stack 2 includes a first type semiconductor layer 21, an active layer 22, and a second type semiconductor layer 23 sequentially stacked in a direction away from the substrate 1. The first electrode 3 is electrically connected to the first type semiconductor layer 21. The first transparent conductive layer 4 is stacked on the portion of the second type semiconductor layer 23 facing away from the substrate 1, and has a first hole 41 exposing the second type semiconductor layer 23 (e.g., ...). Figure 9 (As shown). The second electrode 5 covers a portion of the surface of the first transparent conductive layer 4 that is away from the substrate 1, and is electrically connected to the second type semiconductor layer 23 through the first hole 41. The second transparent conductive layer 6 covers at least the sidewalls of the second electrode 5 and a portion of the surface away from the substrate 1.

[0043] The LED chip of this application is based on the above-described structure. Because a second transparent conductive layer 6 is provided, covering at least the sidewalls of the second electrode 5 and a portion of the surface facing away from the substrate 1, the two transparent conductive layers form a structure that sandwiches the second electrode 5. This ensures ohmic contact between the second electrode 5 and the transparent conductive layer while improving the overall adhesion between the second electrode 5 and other film layers of the chip, thus enhancing the reliability of the bonding wires. Since the adhesion between the second type semiconductor layer 23 and the second electrode 5 in direct contact is greater than the adhesion between the second electrode 5 and the transparent conductive layer, providing the second transparent conductive layer 6 on the second electrode 5 maximizes the contact area between the second electrode 5 and the second type semiconductor layer 23.

[0044] In this embodiment, one of the first type semiconductor layer 21 and the second type semiconductor layer 23 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. This application uses the example of the first type semiconductor layer 21 being an N-type semiconductor layer and the second type semiconductor layer 23 being a P-type semiconductor layer for illustration; the P-type semiconductor layer can be P-type GaN, and the N-type semiconductor layer can be N-type GaN, but is not limited to these, and the materials can be selected according to specific needs. The substrate 1 includes, but is not limited to, silicon substrates, sapphire substrates, etc., and can be a flat substrate or a PSS substrate. In addition to the first type semiconductor layer, the active layer, and the second type semiconductor layer, the epitaxial stack 2 can also include other functional layers as needed, such as buffer layers, superlattice layers, etc.

[0045] The LED chip in this application example has a horizontal structure and a groove 24 that penetrates at least the second type semiconductor layer 23 and the active layer 22 and exposes a portion of the surface of the first type semiconductor layer 21. The first electrode 3 is disposed within the groove 24 and forms an electrical connection with the first type semiconductor layer 21. Preferably, the first electrode 3 and the second electrode 5 can be a multi-layer stacked structure, wherein a single stacked layer can be a single metal or alloy material. The single metal layer includes, but is not limited to, gold, silver, titanium, nickel, aluminum, platinum, chromium, tin, copper, etc. It should be understood that this application only uses a horizontal structure LED chip as an example. However, if other LED chips have the problem of the electrode bottom easily detaching from the contact position with the transparent conductive layer, leading to wire bonding failure, the structure of this application, which uses two transparent conductive layers to form two layers sandwiching the electrode, can be used to ensure ohmic contact between the electrode 5 and the transparent conductive layer, while improving the overall adhesion between the electrode and other film layers of the chip, thereby enhancing the reliability of the wire bonding.

[0046] The horizontally structured LED chip in this application is a front-mounted LED chip. The second electrode 5 has a multi-layer stacked structure. To prevent the second electrode 5 from absorbing light, the material of the stacked layer closest to the second type semiconductor layer 23 of the second electrode 5 needs to consider both adhesion and reflectivity, thus limiting the range of material choices. After adding the second transparent conductive layer 6 to the LED chip of this application, since the second transparent conductive layer 6 is in contact with the sidewall of the second electrode 5 and the part of the surface facing away from the substrate 1, the material selection for the remaining stacked layers of the electrode only needs to consider adhesion, not reflectivity. This allows for a wider range of material choices, better adhesion, and improved wire bonding reliability.

[0047] In a preferred embodiment, the thickness of the first transparent conductive layer 4 is less than the thickness of the second transparent conductive layer 6, which improves the adhesion between the second electrode 5 and the second type semiconductor layer 23 and enhances the reliability of the LED chip.

[0048] More preferably, to improve the light extraction efficiency, the total thickness of the first transparent conductive layer 4 and the second transparent conductive layer 6 can be designed in conjunction with optical interference effects to reduce reflection loss and enhance transmission. For example, the total thickness of the first transparent conductive layer 4 and the second transparent conductive layer 6 can be designed to be one-quarter of the wavelength λ, where wavelength λ is the dominant wavelength of light emitted by the LED chip. Furthermore, when the total thickness of the first transparent conductive layer 4 and the second transparent conductive layer 6 remains constant, the thinner the first transparent conductive layer 4, the better the adhesion between the second electrode 5 and the second type semiconductor layer 23. Figure 3 The total thickness D of the first transparent conductive layer 4 and the second transparent conductive layer 6 is shown. That is, the total thickness D of the first transparent conductive layer 4 and the second transparent conductive layer 6 refers to the total thickness formed by the stacking of the two layers on the light-emitting surface of the second type semiconductor layer 23, which are not in contact with the second electrode 5.

[0049] Preferably, based on any of the above embodiments, the second transparent conductive layer 6 further covers at least a portion of the exposed surface of the first transparent conductive layer 4. The second transparent conductive layer 6 can also conduct electricity between the second electrode 5 and the first transparent conductive layer 4, achieving a better current spreading effect. Preferably, in this application, the second transparent conductive layer 6 covers the entire exposed surface of the first transparent conductive layer 4 and covers the portion of the second type semiconductor layer 23 facing away from the substrate 1.

[0050] Based on any of the above embodiments, preferably, the second transparent conductive layer 6 is provided with a second hole 61 (e.g., ...). Figure 12 As shown), the second hole 61 exposes the portion of the second electrode 5 that faces away from the substrate 1. The projected outer contours of the second electrode 5, the first hole 41, and the second hole 61 on a first plane parallel to the substrate 1 are as follows: Figure 5 As shown. The radius of the first hole 41 is R1, the radius of the second hole 61 is R2, and the radius of the second electrode 5 is R3; wherein, R3-R1≥1um, R3-R2≥1um. Figure 5 The example only uses the case where R2 is greater than R1. R1 can also be greater than R2. This application does not impose any restrictions.

[0051] In a preferred embodiment, the LED chip further includes a passivation layer 7, which covers the exposed surface of the second transparent conductive layer 6 and the epitaxial stack 2. Preferably, the passivation layer 7 is made of a transparent insulating material, such as silicon oxide, silicon nitride, aluminum oxide, or magnesium fluoride. Specifically, the passivation layer 7 covers the exposed surface of the second transparent conductive layer 6, the exposed surface of the second type semiconductor layer 23, the exposed surface of the first type semiconductor layer 21, and the trench walls of the groove 24.

[0052] The top layer metal of the second electrode 5 can be a metal with strong adhesion to enhance the adhesion between the second transparent conductive layer 6 and the sidewalls of the second electrode 5, and the surface of the second electrode 5 facing away from the substrate 1. For example, the top layer metal of the second electrode 5 is one of titanium, chromium, gold, nickel, aluminum, silver, platinum, and copper. It should be understood that the material of the top layer metal in this application is not limited to these, as long as it satisfies the requirement of strong adhesion.

[0053] Preferably, in any of the above embodiments, the first transparent conductive layer 4 and the second transparent conductive layer 6 are single metal thin films or metal oxides. The single metal thin film is one of gold, silver, platinum, copper, aluminum, chromium, and palladium.

[0054] The metal oxide is one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride. When multiple metal oxides are used, they can be doped in different proportions. The materials of the first transparent conductive layer 4 and the second transparent conductive layer 6 can be the same or different.

[0055] Preferably, in any of the above embodiments, the first transparent conductive layer 4 is fabricated using a sputtering method. Fabricating the first transparent conductive layer 4 by sputtering results in a higher carrier density, which is beneficial for improving the conductivity of the first transparent conductive layer 4, reducing Joule heat loss, and helping to lower the operating voltage of the LED chip and improve power conversion efficiency. Furthermore, the high carrier density allows the first transparent conductive layer 4 to be made thinner while maintaining sufficient conductivity, thereby reducing light absorption and reflection losses in the first transparent conductive layer 4.

[0056] Based on any of the above embodiments, preferably, such as Figure 4 As shown, the LED chip also includes a current blocking layer 8, which is located between the first transparent conductive layer 4 and the second type semiconductor layer 23, and has a third hole exposing the second type semiconductor layer 23; the third hole communicates with the first hole 41, and the diameter of the third hole is smaller than the diameter of the first hole 41. The second electrode 5 passes through the first hole 41 and the third hole and is electrically connected to the second type semiconductor layer 23.

[0057] This application also provides a method for manufacturing an LED chip, comprising the following steps:

[0058] S01: Provide a substrate 1.

[0059] S02: As Figure 6 As shown, an epitaxial stack 2 is grown on one side surface of the substrate 1. The epitaxial stack 2 includes a first type semiconductor layer 21, an active layer 22, and a second type semiconductor layer 23, which are grown sequentially along the surface away from the substrate 1.

[0060] The LED chip in this application example has a horizontal structure; therefore, a step for fabricating a MESA step is included between steps S02 and S03. Specifically, as shown... Figure 6 , 7 As shown, after cleaning the epitaxial wafer prepared in step S02, the epitaxial stack 2 is etched to form a groove 24 that at least penetrates the second type semiconductor layer 23 and the active layer 22 and exposes a portion of the surface of the first type semiconductor layer 21. Specifically, photoresist is coated on the surface of the epitaxial stack 2, the pattern of the mask is transferred onto the photoresist by photolithography, and the groove 24 is formed by etching to expose the first type semiconductor layer 21, forming a MESA step.

[0061] S03: As Figure 9 As shown, a first transparent conductive layer 4 is fabricated; the first transparent conductive layer 4 is stacked on the surface of the second type semiconductor layer 23 facing away from the substrate 1, and a first hole 41 is provided to expose the second type semiconductor layer 23. Specifically, as shown... Figure 8 As shown, a transparent conductive layer material is grown on the surface of the epitaxial stack 2 facing away from the substrate 1, and photoresist is coated on it. The pattern on the photomask is transferred to the photoresist by photolithography, and then the transparent conductive layer material in the uncoated area is removed by etching. At the same time, the first hole 41 is etched to expose the second type semiconductor layer 23, forming a structure as shown. Figure 9 The first transparent conductive layer 4 is shown.

[0062] S04: Fabricate the first electrode 3 and the second electrode 5; the first electrode 3 is electrically connected to the first type semiconductor layer 21; the second electrode 5 covers the portion of the first transparent conductive layer 4 facing away from the substrate 1, and is electrically connected to the second type semiconductor layer 23 through the first hole 41. Specifically, photoresist is coated on the surface of the semi-finished product facing away from the substrate 1 formed in step S03 above, the pattern on the photomask is transferred to the photoresist by photolithography, electrode material is grown, and the electrode material in the area not covered by the photoresist is retained to form the first electrode 3 and the second electrode 5.

[0063] S05: Fabricate a second transparent conductive layer 6; the second transparent conductive layer 6 at least covers the sidewalls of the second electrode 5 and the portion of its surface facing away from the substrate 1. Specifically, as shown... Figure 11 As shown, a transparent conductive layer material is grown on the surface of the semi-finished product formed in step S04 away from the substrate 1. Photoresist is coated on the transparent conductive layer material. The pattern on the mask is transferred to the photoresist by photolithography. The transparent conductive layer material in the area not covered by the photoresist is removed to form the second transparent conductive layer 6.

[0064] In this embodiment, one of the first type semiconductor layer 21 and the second type semiconductor layer 23 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. This application uses the example of the first type semiconductor layer 21 being an N-type semiconductor layer and the second type semiconductor layer 23 being a P-type semiconductor layer for illustration; the P-type semiconductor layer can be P-type GaN, and the N-type semiconductor layer can be N-type GaN, but is not limited to these, and the material can be selected according to specific needs.

[0065] In a preferred embodiment, the thickness of the first transparent conductive layer 4 is less than the thickness of the second transparent conductive layer 6.

[0066] Based on any of the above embodiments, preferably, such as Figure 12 As shown, the second transparent conductive layer 6 also covers at least a portion of the exposed surface of the first transparent conductive layer 4. The second transparent conductive layer 6 can also conduct electricity between the second electrode 5 and the first transparent conductive layer 4, achieving a better current spreading effect. Preferably, in this application, the second transparent conductive layer 6 covers the entire exposed surface of the first transparent conductive layer 4 and covers the portion of the second type semiconductor layer 23 facing away from the substrate 1.

[0067] Based on any of the above embodiments, preferably, such as Figure 12 The second transparent conductive layer 6 is provided with a second hole 61, which exposes a portion of the surface of the second electrode 5 away from the substrate 1; the radius of the first hole 41 is R1, the radius of the second hole 61 is R2, and the radius of the second electrode 5 is R3; wherein, R3-R1≥1um, R3-R2≥1um.

[0068] Preferably, based on any of the above embodiments, after step S05, a passivation layer 7 is further formed, which covers the exposed surface of the second transparent conductive layer 6 and the epitaxial stack 2. Specifically, as shown... Figure 13 As shown, in step S05, a passivation layer material is deposited on the side of the semi-finished product facing away from the substrate 1. Photoresist is then coated onto the passivation layer material. Photolithography is then used to transfer the hole pattern from the mask onto the photoresist. Figure 14 As shown, the first electrode 3 and the second electrode 5 are exposed through an etching process. The passivation layer 7 covers the exposed surfaces of the second transparent conductive layer 6, the exposed surfaces of the second type semiconductor layer 23, the exposed surfaces of the first type semiconductor layer 21, and the trench walls of the groove 24.

[0069] The top layer metal of the second electrode 5 can be a metal with strong adhesion to enhance the adhesion between the second transparent conductive layer 6 and the sidewalls of the second electrode 5, and the surface of the second electrode 5 facing away from the substrate 1. For example, the top layer metal of the second electrode 5 is one of titanium, chromium, gold, nickel, aluminum, silver, platinum, and copper. It should be understood that the material of the top layer metal in this application is not limited to these, as long as it satisfies the requirement of strong adhesion.

[0070] Preferably, in any of the above embodiments, the first transparent conductive layer 4 and the second transparent conductive layer 6 are single-metal thin films or metal oxides. The single-metal thin film is one of gold, silver, platinum, copper, aluminum, chromium, and palladium. The metal oxide is one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride. The materials of the first transparent conductive layer 4 and the second transparent conductive layer 6 can be the same or different.

[0071] Based on any of the above embodiments, the first transparent conductive layer 4 is preferably fabricated by sputtering.

[0072] Preferably, based on any of the above embodiments, when the LED chip further includes a current blocking layer 8, the current blocking layer 8 is further fabricated on the surface of the second type semiconductor layer 23 between steps S02 and S03. Specifically, the current blocking layer 8 can be fabricated after the MESA step is fabricated. The current blocking layer 8 has a third hole exposing the second type semiconductor layer 23. The first hole 41 on the subsequently fabricated first transparent conductive layer 4 communicates with the third hole, and the diameter of the third hole is smaller than the diameter of the first hole 41.

[0073] The method for manufacturing the LED chip provided in this application can be used to manufacture the LED chip of any of the above embodiments. Therefore, it has all the beneficial effects of the above-described LED chip, which will not be repeated here.

[0074] Those skilled in the art should understand that in the disclosure of this utility model, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as a limitation of this utility model.

[0075] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0076] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, include: Substrate; An epitaxial stack is disposed on one side surface of the substrate; the epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked along a direction away from the substrate; The first electrode is electrically connected to the first type of semiconductor layer; A first transparent conductive layer is stacked on the portion of the second type semiconductor layer facing away from the substrate, and a first hole is provided to expose the second type semiconductor layer; The second electrode covers a portion of the first transparent conductive layer that is away from the substrate and is electrically connected to the second type semiconductor layer through the first hole. A second transparent conductive layer covers at least the sidewalls of the second electrode and a portion of its surface facing away from the substrate.

2. The LED chip as described in claim 1, characterized in that, The thickness of the first transparent conductive layer is less than the thickness of the second transparent conductive layer.

3. The LED chip as described in claim 1, characterized in that, The second transparent conductive layer also covers at least a portion of the exposed surface of the first transparent conductive layer.

4. An LED chip as described in claim 1, characterized in that, The second transparent conductive layer has a second hole, which exposes a portion of the surface of the second electrode that faces away from the substrate; The radius of the first hole is R1, the radius of the second hole is R2, and the radius of the second electrode is R3; wherein, R3-R1≥1um, R3-R2≥1um.

5. An LED chip as described in claim 1, characterized in that, It also includes a passivation layer; the passivation layer covers the exposed surface of the second transparent conductive layer and the epitaxial stack.

6. An LED chip as described in claim 1, characterized in that, The top layer metal of the second electrode is one of titanium, chromium, gold, nickel, aluminum, silver, platinum, and copper.

7. An LED chip as described in claim 1, characterized in that, The first transparent conductive layer and the second transparent conductive layer are single metal thin films or metal oxides; The single metal thin film is one of gold, silver, platinum, copper, aluminum, chromium, and palladium; The metal oxide is one or more of indium oxide, indium tin oxide, zirconium oxide, cadmium oxide, and titanium nitride.

8. An LED chip as described in claim 7, characterized in that, The first transparent conductive layer is fabricated using a sputtering method.

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