Dual-channel nuclear pulse acquisition daughter card based on JESD204B interface

Abstract

The utility model discloses a dual-channel nuclear pulse acquisition daughter card based on a JESD204B interface, which adopts a dual-channel high-speed ADC (analog-to-digital converter) chip based on the JESD204B interface as a core module of hardware design, and selects a universal MCX connector in the industry as an input interface of two paths of analog pulse signals. Wherein one path of pulse signal enters the ADC for sampling through the alternating current coupling transformer driving module, the other path of pulse signal enters the ADC for sampling through the direct current coupling amplifier driving module, and a high-integration positive and negative power supply module is designed to provide working voltage for a hardware system, so that nuclear electronics data acquisition with two channels, 14-bit sampling precision and 1 GHz sampling rate is realized; and the nuclear pulse signal data acquisition capability of a nuclear electronics system can be greatly improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the field of nuclear electronics, and relates to a double-channel nuclear pulse collection daughter card based on a JESD204B interface. BACKGROUND

[0002] In recent years, with the development of nuclear science and technology, whether the research on the characteristics and laws of the nucleus or the application of nuclear science and technology, the information carried by nuclear radiation and the nucleus needs to be measured and analyzed. Generally, the industry adopts various nuclear radiation detectors to detect and output nuclear information, and converts it into an electrical signal, and then processes and studies the signal by using special electronics, and tries to preserve the information carried by the detector output signal as much as possible. This gradually develops into the field of nuclear electronics in nuclear science and technology.

[0003] Nuclear electronics undertakes the functions of nuclear signal collection, nuclear signal processing and nuclear signal transmission, especially in the aspect of nuclear signal collection. Because the physical information obtained by the front-end nuclear radiation detector is first converted into a nuclear pulse signal in the detector, the signal is rapidly collected by the ADC of the nuclear electronics system after preliminary amplification or shaping processing, and then converted into a digital signal, and then transmitted to the FPGA for signal processing and signal transmission. Therefore, the higher the precision of the ADC collection and the faster the sampling speed, the more complete the preservation of the original information of the nuclear pulse, and thus the more real and accurate physical information can be obtained.

[0004] Since the multi-channel high-speed ADC based on the LVDS data transmission interface was introduced in 2001, its performance indicators have become higher and higher, and the data transmission rate can reach 1Gbps. At present, for a 16-channel ADC, the sampling rate can reach 80MSPS, and the sampling precision can reach 12bit. As a bridge between analog signals and digital signals, it has made great achievements in all fields of electronics, and due to the high-speed and multi-channel characteristics of the signal in the nuclear electronics system, almost all nuclear electronics systems (except for nuclear electronics systems based on ASIC chips) currently use multi-channel ADC based on the LVDS interface to obtain detector pulse signals.

[0005] With the continuous increase in ADC sampling rates and channel density, data throughput is also increasing. Existing LVDS interfaces are increasingly unable to meet the data transmission interface design requirements of high-sampling-rate, multi-channel ADCs. The industry needs a faster and more energy-efficient digital interface than LVDS. In recent years, a new type of multi-channel ADC based on the JESD204B data transmission interface has emerged, with a maximum data transmission rate of 12.5Gbps, which can meet the data transmission requirements of high-sampling-rate, multi-channel ADCs. Therefore, how to achieve high-speed nuclear pulse acquisition based on the JESD204B interface has become an urgent technical problem to be solved. Utility Model Content

[0006] To address the problems existing in the prior art, the purpose of this utility model is to provide a dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface. This solution uses a dual-channel high-speed ADC chip based on the JESD204B interface as the core module of the hardware design. The industry-standard MCX connector is selected as the input interface for two analog pulse signals. One pulse signal enters the ADC for sampling through a passive AC coupling transformer drive module, and the other enters the ADC for sampling through an active DC coupling amplifier drive module. A highly integrated positive and negative power supply module is designed to provide the operating voltage of the hardware system, realizing a new dual-channel, 1GHz sampling rate high-speed nuclear pulse acquisition daughter card hardware design scheme.

[0007] This application uses the industry-leading 2-channel ADC chip—ADS54J40—based on the JESD204B data transmission interface. It achieves different forms of data sampling through two methods: transformer AC coupling and amplifier DC coupling. The first channel signal is DC coupled through the MCX connector, and the second channel signal is AC coupled through the MCX connector.

[0008] This application uses four LDO chips—TPS7A8300—to power the ADC; two FMC-LPC connectors are used to implement hardware power supply and ADC configuration; and one FMC-HPC connector is used to enable high-speed data communication between the hardware system and the external JESD204B.

[0009] The technical solution of this utility model is as follows:

[0010] A dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface is characterized by comprising a first MCX connector 1, a second MCX connector 2, a dual-channel high-speed ADC chip 8 based on the JESD204B interface 8, an FMC-HPC connector 9, a second FMC-LPC connector 10, a DC-coupled amplifier driver module 13, and an AC-coupled transformer driver module 14.

[0011] The first MCX connector 1 is used for receiving the first nuclear pulse signal generated by the nuclear radiation detector and inputting the signal into the direct current coupling amplifier driving module 13;

[0012] The direct current coupling amplifier driving module 13 is used for converting the input nuclear pulse signal into a non-distorted direct current differential pulse signal and inputting the signal into the double-channel high-speed ADC chip 8 based on the JESD204B interface;

[0013] The second MCX connector 2 is used for receiving the second nuclear pulse signal generated by the nuclear radiation detector and inputting the signal into the alternating current coupling transformer driving module 14;

[0014] The alternating current coupling transformer driving module 14 is used for converting the input nuclear pulse signal into a non-distorted alternating current differential pulse signal and inputting the signal into the double-channel high-speed ADC chip 8 based on the JESD204B interface;

[0015] The double-channel high-speed ADC chip 8 based on the JESD204B interface is used for digitizing the two input nuclear pulse signals and transmitting the signals to the FMC-HPC connector 9 through the JESD204B interface;

[0016] The FMC-HPC connector 9 is used for transmitting the signal processed by the double-channel high-speed ADC chip 8 based on the JESD204B interface to a backend device and receiving a sampling clock provided by the backend device for the double-channel high-speed ADC chip 8 based on the JESD204B interface;

[0017] The second FMC-LPC connector 10 is used for receiving an external instruction to configure the internal register state of the double-channel high-speed ADC chip 8 based on the JESD204B interface.

[0018] Further, the first FMC-LPC connector 4, the first analog LDO power module 3, the second analog LDO power module 5, the third analog LDO power module 6, and the fourth analog LDO power module 7 are further included; the first FMC-LPC connector 4 is used to provide digital voltages of external devices to the first analog LDO power module 3, the second analog LDO power module 5, the third analog LDO power module 6, and the fourth analog LDO power module 7 respectively; the first analog LDO power module 3 is used to provide a working voltage of 1.9V for an analog part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; the second analog LDO power module 5 is used to provide a working voltage of 1.9V for a digital part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; the third analog LDO power module 6 is used to provide a working voltage of 1.15V for the digital part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; and the fourth analog LDO power module 7 is used to provide a working voltage of 3V for the analog part of the double-channel high-speed ADC chip 8 based on the JESD204B interface.

[0019] Further, the DC-DC digital power module 11 and the analog LDO positive and negative power module 12 are further included; the second FMC-LPC connector 10 converts a voltage provided by an external device into a 5.4V digital voltage and then provides the voltage to the DC-DC digital power module 11; the DC-DC digital power module 11 is used to provide a ±5V digital voltage for the analog LDO positive and negative power module 12; and the analog LDO positive and negative power module 12 is used to provide a ±3.3V analog power supply for the direct current coupling amplifier driving module 13.

[0020] Further, the double-channel high-speed ADC chip 8 based on the JESD204B interface is an ADS54J40, the sampling frequency of which is 1GHz, and the sampling precision of which is 14bit.

[0021] Further, the direct current coupling amplifier driving module 13 adopts a high-bandwidth differential amplifier chip ADA4940 to convert an input nuclear pulse signal into a distortionless direct current differential pulse signal.

[0022] Further, the alternating current coupling transformer driving module 14 adopts a high-bandwidth transformer ADT1-1WT to convert an input nuclear pulse signal into a distortionless alternating current differential pulse signal.

[0023] The advantages of the utility model are as follows:

[0024] The utility model provides a new 2 channel, 14bit sampling precision, 1GHz sampling rate's nuclear electronics data collection solution, this hardware design scheme handles 2 way front end detector high speed pulse signal simultaneously, compatible alternating current and direct current coupling input sampling ability, can greatly improve nuclear electronics system's nuclear pulse signal data collection ability, convenient to use.

[0025] 1, MCX connector frequency band is wide, reliability is strong, and universality is good.

[0026] 2, power supply design is high in integration, and low in power consumption.

[0027] 3, 1 way is alternating current coupling input, and the other way is direct current coupling input, and application scene is flexible.

[0028] 4, general high density FMC-LPC, FMC-HPC connector is used, can provide power supply for this hardware design again can transmit high speed signal and configuration information. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 It is the hardware structure block diagram of the scheme.

[0030] Fig. 1-1st MCX connector, 2-2nd MCX connector, 3-1st analog LDO power module, 4-1st FMC-LPC connector, 5-2nd analog LDO power module, 6-3rd analog LDO power module, 7-4th analog LDO power module, 8-Double channel high speed ADC chip based on JESD204B interface, 9-FMC-HPC connector, 10-2nd FMC-LPC connector, 11-DC-DC digital power module, 12-analog LDO positive and negative power module, 13-direct current coupling amplifier drive module, 14-alternating current coupling transformer drive module. DETAILED DESCRIPTION

[0031] The utility model will be further described in detail in combination with the drawings, and the example is only used to explain the utility model, and is not used to limit the scope of the utility model.

[0032] The hardware structure block diagram of the utility model scheme is as Figure 1The first MCX connector 1 is used as an AC coupling input interface of the first high-speed nuclear pulse signal generated by the front-end nuclear radiation detector; the second MCX connector 2 is used as a DC coupling input interface of the second high-speed nuclear pulse signal generated by the front-end nuclear radiation detector; the first analog LDO power module 3 provides a working voltage of 1.9V for the analog part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; the external device provides digital voltages of 3.3V, 2.5V and 1.8V to the hardware system through the first FMC-LPC connector 4; the second analog LDO power module 5 provides a working voltage of 1.9V for the digital part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; the third analog LDO power module 6 provides a working voltage of 1.15V for the digital part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; the fourth analog LDO power module 7 provides a working voltage of 3V for the analog part of the double-channel high-speed ADC chip 8 based on the JESD204B interface; the double-channel high-speed ADC chip 8 based on the JESD204B interface is ADS54J40, with a sampling frequency of 1GHz and a sampling accuracy of 14bit; the double-channel high-speed ADC chip 8 based on the JESD204B interface simultaneously digitizes two nuclear pulse signals and transmits them to the FMC-HPC connector 9 through the high-speed JESD204B interface; the digitized sampling data of the double-channel high-speed ADC chip 8 based on the JESD204B interface is transmitted to the back-end device through the FMC-HPC connector 9, and the back-end device provides a sampling clock of 1GHz for the double-channel high-speed ADC chip 8 based on the JESD204B interface through the FMC-HPC connector 9; the external device provides a digital voltage of 5.4V to the hardware system through the second FMC-LPC connector 10, and configures the internal register state of the double-channel high-speed ADC chip 8 based on the JESD204B interface through the second FMC-LPC connector 10; the DC-DC digital power module 11 provides a digital power input of ±5V for the analog LDO positive and negative power module 12; the analog LDO positive and negative power module 12 provides a ±3.3V analog power input for the high-speed differential amplifier chip of the DC coupling amplifier driving module 13; the DC coupling amplifier driving module 13 is used to change the high-speed single-ended nuclear pulse signal output by the first MCX connector 1 into a distortionless DC differential pulse signal suitable for sampling by the double-channel high-speed ADC chip 8; the AC coupling transformer driving module 14 is used to change the high-speed single-ended nuclear pulse signal output by the second MCX connector 2 into a distortionless AC differential pulse signal suitable for sampling by the double-channel high-speed ADC chip 8.

[0033] The utility model provides a hardware design scheme of double channel, 1GHz sampling rate, 14bit sampling precision's high speed nuclear pulse collection daughter card based on JESD204B interface, after design, manufacture, its simple structure, convenient to use, high integration, low noise, fully satisfy the hardware design requirement of nuclear pulse collection electronics. As described above, first MCX connector 1 and second MCX connector 2 are all industry general MCX connector, for external high speed pulse signal input, first analog LDO power module 3, second analog LDO power module 5, third analog LDO power module 6, fourth analog LDO power module 7 all take TI company's low noise LDO power chip-TPS7A8300 as the core, and provide digital 1.9V, analog 1.9V, digital 1.15V and analog 3V working voltage for double channel high speed ADC chip based on JESD204B interface respectively, first FMC-LPC connector 4 is samtec company's FMC-LPC connector, and the back-end equipment provides digital 1.5V, digital 2.5V and digital 3.3V voltage for the hardware design through it, and double channel high speed ADC chip based on JESD204B interface takes TI company's double channel high speed ADC chip-ADS54J40 as the core, and digitizes 2-way high speed nuclear pulse signal simultaneously and transmits to FMC-HPC connector 9 through JESD204B interface, FMC-HPC connector 9 is samtec company's FMC-HPC connector, and the back-end equipment carries out JESD204B high speed data communication through it and double channel high speed ADC chip 8 based on JESD204B interface, second FMC-LPC connector 10 is samtec company's FMC-LPC connector, and the back-end equipment provides digital 5.4V and the ADC chip operating mode of configuration FMC-HPC connector 9 for the hardware design, DC-DC digital power module 11 takes ADI company's positive and negative output switching power chip-LTM8049 as the core, and provides ±5V digital power for analog LDO positive and negative power module 12, analog LDO positive and negative power module 12 takes ADI company's positive and negative output LDO power chip-LT3032 as the core, and provides ±3.3V analog power for amplifier chip of direct current coupling amplifier drive module 13, direct current coupling amplifier drive module 13 takes ADI company's high bandwidth differential amplifier chip-ADA4940 as the core, and changes high speed single-ended pulse signal input from first MCX connector 1 into differential signal suitable for ADC sampling through direct current coupling mode, alternating current coupling transformer drive module 14 takes ADI company's high bandwidth transformer-ADT1-1WT as the core, and changes high speed single-ended pulse signal input from second MCX connector 2 into differential signal suitable for ADC sampling through alternating current coupling mode.

[0034] Although the specific embodiments of the utility model are disclosed for the purpose of illustration, the purpose is to help understand the content of the utility model and to implement it, the person skilled in the art can understand that: without departing from the spirit and scope of the utility model and the appended claims, various substitutions, changes and modifications are possible. Therefore, the utility model should not be limited to the disclosed content of the best embodiment, and the scope of the utility model claimed is the scope defined by the claims.

Claims

1. A dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface, characterized in that, Includes a first MCX connector (1), a second MCX connector (2), a dual-channel high-speed ADC chip (8) based on the JESD204B interface, an FMC-HPC connector (9), a second FMC-LPC connector (10), a DC-coupled amplifier drive module (13), and an AC-coupled transformer drive module (14); The first MCX connector (1) is used to receive the first nuclear pulse signal generated by the nuclear radiation detector and input it into the DC-coupled amplifier drive module (13); The DC-coupled amplifier driver module (13) is used to convert the input nuclear pulse signal into a distortion-free DC differential pulse signal and then input it into the dual-channel high-speed ADC chip (8) based on the JESD204B interface. The second MCX connector (2) is used to receive the second nuclear pulse signal generated by the nuclear radiation detector and input it into the AC coupling transformer drive module (14); The AC coupling transformer drive module (14) is used to convert the input nuclear pulse signal into a distortion-free AC differential pulse signal and input it into the dual-channel high-speed ADC chip (8) based on the JESD204B interface; The dual-channel high-speed ADC chip (8) based on the JESD204B interface is used to digitize the two input nuclear pulse signals and transmit them to the FMC-HPC connector (9) through the JESD204B interface. The FMC-HPC connector (9) is used to transmit the signal processed by the dual-channel high-speed ADC chip (8) based on the JESD204B interface to the back-end device, and to receive the sampling clock provided by the back-end device for the dual-channel high-speed ADC chip (8) based on the JESD204B interface. The second FMC-LPC connector (10) is used to receive external instructions to configure the internal register state of the dual-channel high-speed ADC chip (8) based on the JESD204B interface.

2. The dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface according to claim 1, characterized in that, It also includes a first FMC-LPC connector (4), a first analog LDO power module (3), a second analog LDO power module (5), a third analog LDO power module (6), and a fourth analog LDO power module (7); the first FMC-LPC connector (4) is used to supply the digital voltage of the external device to the first analog LDO power module (3), the second analog LDO power module (5), the third analog LDO power module (6), and the fourth analog LDO power module (7), respectively; the first analog LDO power module (3) is used to power the dual-channel high-speed AD converter based on the JESD204B interface. The analog section of the C chip (8) is provided with a working voltage of 1.9V; the second analog LDO power module (5) is used to provide a working voltage of 1.9V to the digital section of the dual-channel high-speed ADC chip (8) based on the JESD204B interface; the third analog LDO power module (6) is used to provide a working voltage of 1.15V to the digital section of the dual-channel high-speed ADC chip (8) based on the JESD204B interface; and the fourth analog LDO power module (7) is used to provide a working voltage of 3V to the analog section of the dual-channel high-speed ADC chip (8) based on the JESD204B interface.

3. The dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface according to claim 1, characterized in that, It also includes a DC-DC digital power module (11) and an analog LDO positive and negative power module (12). The second FMC-LPC connector (10) converts the voltage provided by the external device into a 5.4V digital voltage and provides it to the DC-DC digital power module (11). The DC-DC digital power module (11) is used to provide ±5V digital voltage to the analog LDO positive and negative power module (12). The analog LDO positive and negative power module (12) is used to provide ±3.3V analog power to the DC-coupled amplifier driver module (13).

4. The dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface according to claim 1, 2, or 3, characterized in that, The dual-channel high-speed ADC chip (8) based on the JESD204B interface is ADS54J40, with a sampling frequency of 1GHz and a sampling accuracy of 14bit.

5. The dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface according to claim 1, 2, or 3, characterized in that, The DC-coupled amplifier driver module (13) uses the high-bandwidth differential amplifier chip ADA4940 to convert the input nuclear pulse signal into a distortion-free DC differential pulse signal.

6. The dual-channel nuclear pulse acquisition daughter card based on the JESD204B interface according to claim 1, 2, or 3, characterized in that, The AC coupling transformer drive module (14) uses a high-bandwidth transformer ADT1-1WT to convert the input nuclear pulse signal into a distortion-free AC differential pulse signal.

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