Parallel circuit of current pulse width modulation chip

Abstract

The utility model provides a parallel circuit of a current pulse width modulation chip, which belongs to the technical field of current pulse width modulation chip application, and comprises a master control chip circuit and a slave control chip circuit which are electrically connected, the master control chip circuit outputs A-PWM signals, the slave control chip circuit outputs B-PWM signals, and the A-PWM signals output by the master control chip circuit and the B-PWM signals output by the slave control chip circuit. The frequency and pulse width standards of the A-PWM signal and the B-PWM signal are synchronous; according to the invention, the two power inverters of the master control chip circuit and the slave control chip circuit can be driven, the two inverters can realize accurate synchronization no matter whether the frequency or the working PWM pulse width, the working interference in the high-frequency inversion process is reduced, and the reliability of the inverters is greatly improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field that current pulse width modulation chip applied, specifically, a kind of parallel circuit of current pulse width modulation chip. BACKGROUND

[0002] At present, most of the inverter DC welders on the market use single-chip single-machine-core inverter mode. The output power of the single-chip inverter DC welder can meet the basic requirements when it is less than 20KW. However, when the output power is greater than 20KW, the single-machine-core inverter DC welder has significant drawbacks: 1. As the power increases, the selection of power inverter semiconductor devices will be limited. Large-current power inverter semiconductor devices are not common on the domestic market. To solve this problem, the common power inverter semiconductor devices on the market are usually connected in parallel for inverter DC welders. This method requires high consistency of power inverter semiconductor devices. If the consistency of power inverter semiconductor devices cannot be met, it is very easy to cause damage to the power inverter semiconductor devices. 2. However, the existing parallel connection of power inverter semiconductor devices is usually two separate power inverter semiconductor devices. In different inverter states, the two devices are connected in parallel. Although this parallel connection method can achieve power stacking, it may cause power inverter semiconductor devices to be out of sync, resulting in unpredictable interference and reducing the reliability of power inverter semiconductor devices. As the output power of the inverter DC welder increases, the power inverter semiconductor devices also generate a considerable amount of heat, which requires high requirements for the structural design and air duct design of the power inverter semiconductor devices.

[0003] Therefore, there is an urgent need for a connection method that improves the consistency of parallel-connected power inverter semiconductor devices, disperses the heat generated by the inverter, and improves the reliability of the entire machine. SUMMARY

[0004] Therefore, there is an urgent need for a connection method that improves the consistency of parallel-connected power inverter semiconductor devices, disperses the heat generated by the inverter, and improves the reliability of the entire machine.

[0005] The technical solution of the utility model is as follows: a parallel circuit of current pulse width modulation chip, including main control chip circuit and slave control chip circuit connected electrically, the main control chip circuit outputs A-PWM signal, the slave control chip circuit outputs B-PWM signal, the frequency and pulse width of A-PWM signal and B-PWM signal are standard synchronous.

[0006] On the basis of the above technical scheme, preferably, the main control chip circuit comprises a main control chip slope compensation circuit, a main control chip peak circuit protection circuit and a current pulse width modulation chip U1; the slave control chip circuit comprises a slave control chip slope compensation circuit, a slave control chip peak circuit protection circuit and a current pulse width modulation chip U2, and the main control chip peak circuit protection circuit and the slave control chip peak circuit protection circuit are connected with different power inversion modules.

[0007] On the basis of the above technical scheme, preferably, the current pulse width modulation chip U1 comprises an 8th U1 pin and a 9th U1 pin, the 8th U1 pin is electrically connected with a frequency capacitor C13, and the 9th U1 pin is electrically connected with a frequency resistor R13.

[0008] On the basis of the above technical scheme, preferably, the current pulse width modulation chip U1 comprises a 10th U1 pin, and the current pulse width modulation chip U2 comprises a 10th U2 pin, and the 10th U1 pin is electrically connected with the 10th U2 pin.

[0009] On the basis of the above technical scheme, preferably, the current pulse width modulation chip U1 comprises a 5th U1 pin and a 7th U1 pin, the 5th U1 pin inputs a peripheral input pulse width modulation voltage signal; the current pulse width modulation chip U2 comprises a 7th U2 pin, and the 7th U1 pin is electrically connected with the 7th U2 pin.

[0010] On the basis of the above technical scheme, preferably, the main control chip slope compensation circuit and the slave control chip slope compensation circuit are connected in parallel, a parallel circuit of the main control chip slope compensation circuit and the slave control chip slope compensation circuit is electrically connected with the 8th U1 pin, an oscillation triangular wave signal generated by the 8th U1 pin of the current pulse width modulation chip U1 is provided, the main control chip slope compensation circuit comprises an operational amplifier follower ID1-D, the slave control chip slope compensation circuit comprises an operational amplifier follower ID1-C, and the operational amplifier follower ID1-D and the operational amplifier follower ID1-C follow the oscillation triangular wave signal.

[0011] On the basis of the above technical scheme, preferably, the current pulse width modulation chip U1 comprises a 4th U1 pin, the current pulse width modulation chip U2 comprises a 4th U2 pin, the main control chip slope compensation circuit is electrically connected with the 4th U1 pin, and the slave control chip slope compensation circuit is electrically connected with the 4th U2 pin.

[0012] On the basis of the above technical scheme, preferably, the current pulse width modulation chip U1 comprises a 16th U1 pin, the current pulse width modulation chip U2 comprises a 16th U2 pin, the main control chip peak circuit protection circuit is electrically connected with the 16th U1 pin, and the slave control chip peak circuit protection circuit is electrically connected with the 16th U2 pin.

[0013] The parallel circuit of the current pulse width modulation chip has the following beneficial effects relative to the prior art:

[0014] The two power inverters of the master control chip circuit and the slave control chip circuit can be driven, and the two inverters can realize precise synchronization in terms of frequency and working PWM pulse width, reduce working interference in the high-frequency inversion process, and greatly improve the reliability of the inverter. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, a brief introduction will be given below to the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0016] Figure 1 The circuit diagram of the parallel circuit of the current pulse width modulation chip of the present application;

[0017] Figure 2 The internal principle block diagram of the current-mode PWM controller 3846 of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be described below in a clear and complete manner in combination with the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0019] As shown in Figure 1 and 2 , a parallel circuit of a current pulse width modulation chip includes a master control chip circuit 1 and a slave control chip circuit 2 connected electrically, the master control chip circuit 1 outputs an A-PWM signal, the slave control chip circuit 2 outputs a B-PWM signal, and the frequency and pulse width of the A-PWM signal and the B-PWM signal are standard synchronous. The master control chip circuit 1 includes a master control chip slope compensation circuit 11, a master control chip peak circuit protection circuit 12, and a current pulse width modulation chip U113; the slave control chip circuit 2 includes a slave control chip slope compensation circuit 21, a slave control chip peak circuit protection circuit 22, and a current pulse width modulation chip U223, and the master control chip peak circuit protection circuit 12 and the slave control chip peak circuit protection circuit 22 are connected with different power inversion modules. The current pulse width modulation chip U113 and the current pulse width modulation chip U223 are both current-mode PWM controllers 3846, and the circuit diagram is as followsFigure 2 As shown, the power supply and current limiting circuit belongs to the conventional application connection, for example, the current pulse width modulation chip U113: pin 15 U1 is connected to the power input, pin 13 U1 is the output A-PWM power supply end, the positive VCC power supply is connected to pin 15 U1, and is connected to pin 13 U1 through resistor R20, at the same time, pin 15 U1 is electrically connected to filter capacitor C18, and pin 13 U1 is electrically connected to filter capacitor C17. Pin 2 U1 is the reference 5V power output end, pin 1 U1 is the current limiting signal input end, the reference voltage is taken from pin 2 U1, is divided by resistors R12 and R11, and is connected to pin 1 U1 as a current limiting signal, at the same time, pin 2 U1 is electrically connected to filter capacitor C12, and pin 1 U1 is electrically connected to filter capacitor C11. The peripheral connection of pin 15 U2, pin 13 U2, pin 2 U2 and pin 1 U2 of the current pulse width modulation chip U223 is the same as that of the current pulse width modulation chip U113. Pin 3 U2 and pin 12 U2 are connected to GND as the ground end.

[0020] The 8th pin, 9th pin and 10th pin of the current pulse width modulation chip U113 and the 8th pin, 9th pin and 10th pin of the current pulse width modulation chip U223 are the oscillator peripheral interface. The current pulse width modulation chip U113 includes the 8th pin and 9th pin, the 8th pin is electrically connected to frequency capacitor C13, and the 9th pin is electrically connected to frequency resistor R13, so as to realize the frequency oscillation of the master control chip. The 8th pin of the current pulse width modulation chip U223 is electrically connected to GND, the 9th pin is electrically connected to the reference 5V power supply, and the 10th pin is electrically connected to the 10th pin as a synchronous signal end, so as to realize the synchronization of the oscillation frequency.

[0021] The current pulse width modulation chip U113 includes the 5th pin and 7th pin, the 5th pin inputs the peripheral input pulse width modulation voltage signal; the current pulse width modulation chip U223 includes the 7th pin, and the 7th pin is electrically connected to the 7th pin. The 5th pin is externally connected to the input pulse width modulation voltage signal, which is the given signal of the whole machine system, and is connected only to the current pulse width modulation chip U113. The 6th pin of the current pulse width modulation chip U113 is electrically connected to the 7th pin and the 7th pin. The 7th pin is also electrically connected to the reference 5V power supply, and the 6th pin is connected to GND. The synchronization of the given signal is realized by the connection of the 7th pin and the 7th pin.

[0022] The main control chip ramp compensation circuit 11 and the slave control chip ramp compensation circuit 21 are connected in parallel. This parallel circuit is electrically connected to pin 8 (U1). The oscillating triangular wave generated by pin 8 (U1) of the current pulse width modulation chip U113 provides the signal. The main control chip ramp compensation circuit 11 includes operational amplifier follower ID1-D, and the slave control chip ramp compensation circuit 21 includes operational amplifier follower ID1-C. Operational amplifier follower ID1-D and ID1-C follow the oscillating triangular wave signal. The current pulse width modulation chip U113 includes pin 4 (U1), and the current pulse width modulation chip U223 includes pin 4 (U2). The main control chip ramp compensation circuit 11 is electrically connected to pin 4 (U1), and the slave control chip ramp compensation circuit 21 is electrically connected to pin 4 (U2). The ramp compensation circuit 11 of the main control chip generates an oscillating triangular wave from pin 8 (U1), which is connected to the op-amp follower ID1-D. After following, it passes through resistors R14 / R15 and capacitors C14 / C15 and is connected to pin 4 (U1) of the main control chip. At the same time, pin 4 (U1) is connected to GND through resistor R16. Through the voltage division of the resistors, ramp compensation of the current is achieved. At this time, the primary current detection feedback signal of the main control chip circuit 1 is also connected to pin 4 (U1) through resistor R17, and is superimposed with the ramp compensation signal to achieve pulse width control. The ramp compensation circuit 21 of the slave control chip also samples from pin 8 (U1), passes through the op-amp follower ID1-C, and is connected to pin 4 (U2) through resistors R24 / R25 and capacitors C24 / C25. Because the sampling points are consistent, the ramp compensation parts of the main control chip circuit 1 and the slave control chip circuit 2 can achieve coordination and unity. The primary current detection feedback signal of the slave control chip circuit 2 is also connected to pin 4 (U2) through resistor R27, and superimposed with the ramp compensation signal to achieve pulse width adjustment.

[0023] The current pulse width modulation chip U113 includes pin 16 (U1), and the current pulse width modulation chip U223 includes pin 16 (U2). The peak circuit protection circuit 12 of the master control chip is electrically connected to pin 16 (U1), and the peak circuit protection circuit 22 of the slave control chip is electrically connected to pin 16 (U2).

[0024] The peak current protection circuit 12 of the main control chip receives the primary-side current sampling signal from the main control chip circuit 1. This signal is divided by resistors R18 / R19 and connected to pin 16 (U1). A filter capacitor C16 is also externally connected to pin 16 (U1). Similarly, the peak current protection circuit 22 of the slave control chip receives the primary-side current sampling signal from the slave control chip circuit 2. This signal is divided by resistors R28 / R29 and connected to pin 16 (U2). A filter capacitor C26 is also externally connected to pin 16 (U2). By utilizing the external shutdown logic of pin 16 (U1), protection against primary-side current overcurrent is achieved. This significantly improves the reliability of both the main control chip circuit 1 and the slave control chip circuit 2.

[0025] 11th U1 pin and 13th U1 pin as output, access A-PWM drive. 11th U2 pin and 13th U2 pin as output, access B-PWM drive, the above-mentioned current pulse width modulation chip U113 and current pulse width modulation chip U223 connection, A-PWM and B-PWM drive signal, whether frequency or pulse width size change, can realize complete unity, make the master chip circuit 1 and slave chip circuit 2 can do inverter switch consistent, eliminate because of the pace of the inconsistent mutual interference and other adverse factors, greatly improve the main control chip circuit 1 and slave chip circuit 2 of the whole machine reliability.

[0026] The above only for the preferred embodiment of the present application has been described, and is not used to limit the present application, any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application, should be included in the scope of protection of the present application.

Claims

1. A parallel circuit of current pulse width modulation chips comprising a master chip circuit (1) and a slave chip circuit (2) electrically connected, characterized in that: The master chip circuit (1) outputs A-PWM signal, the slave chip circuit (2) outputs B-PWM signal, and the frequency and pulse width of A-PWM signal and B-PWM signal are standard synchronous.

2. A parallel connection of current pulse width modulation chips as defined in claim 1, characterized in that: The master chip circuit (1) comprises a master chip slope compensation circuit (11), a master chip peak circuit protection circuit (12) and a current pulse width modulation chip U1 (13); the slave chip circuit (2) comprises a slave chip slope compensation circuit (21), a slave chip peak circuit protection circuit (22) and a current pulse width modulation chip U2 (23), and the master chip peak circuit protection circuit (12) and the slave chip peak circuit protection circuit (22) are connected with different power inverter modules.

3. A parallel connection of current pulse width modulated chips as defined in claim 2, characterized in that: The current pulse width modulation chip U1 (13) comprises a No. 8 U1 pin and a No. 9 U1 pin, the No. 8 U1 pin is electrically connected with a frequency capacitor C13, and the No. 9 U1 pin is electrically connected with a frequency resistor R13.

4. A parallel connection of current pulse width modulated chips as defined in claim 3, characterized in that: The current pulse width modulation chip U1 (13) comprises a No. 10 U1 pin, and the current pulse width modulation chip U2 (23) comprises a No. 10 U2 pin, the No. 10 U1 pin is electrically connected with the No. 10 U2 pin.

5. A parallel connection of current pulse width modulated chips as defined in claim 2, wherein: The current pulse width modulation chip U1 (13) comprises a No. 5 U1 pin and a No. 7 U1 pin, the No. 5 U1 pin inputs peripheral input pulse width modulation voltage signal; the current pulse width modulation chip U2 (23) comprises a No. 7 U2 pin, and the No. 7 U1 pin is electrically connected with the No. 7 U2 pin.

6. A parallel connection of current pulse width modulated chips as defined in claim 3, characterized in that: The master chip slope compensation circuit (11) and the slave chip slope compensation circuit (21) are connected in parallel, the parallel circuit of the master chip slope compensation circuit (11) and the slave chip slope compensation circuit (21) is electrically connected with the No. 8 U1 pin, the oscillation triangular wave signal generated by the No. 8 U1 pin of the current pulse width modulation chip U1 (13) provides a signal, the master chip slope compensation circuit (11) comprises an operational amplifier follower ID1-D, the slave chip slope compensation circuit (21) comprises an operational amplifier follower ID1-C, and the operational amplifier follower ID1-D and the operational amplifier follower ID1-C follow the oscillation triangular wave signal.

7. A parallel connection of current pulse width modulated chips as defined in claim 3, characterized in that: The current pulse width modulation chip U1 (13) comprises a No. 4 U1 pin, and the current pulse width modulation chip U2 (23) comprises a No. 4 U2 pin, the master chip slope compensation circuit (11) is electrically connected with the No. 4 U1 pin, and the slave chip slope compensation circuit (21) is electrically connected with the No. 4 U2 pin.

8. A parallel connection of current pulse width modulated chips as defined in claim 2, wherein: The current pulse width modulation chip U1 (13) comprises a No. 16 U1 pin, and the current pulse width modulation chip U2 (23) comprises a No. 16 U2 pin, the master chip peak circuit protection circuit (12) is electrically connected with the No. 16 U1 pin, and the slave chip peak circuit protection circuit (22) is electrically connected with the No. 16 U2 pin.

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