Copper alloy seed laminated structure
By setting a copper alloy stack between the copper seed layer and the TCO film contact surface, the problem of poor adhesion of the copper seed layer in the PVD process is solved, thereby improving the adhesion of copper grid cells and the reliability of the cells.
Patent Information
- Application Number
- CN202520126582.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-20
- Publication Date
- 2026-03-03
- Estimated Expiration
- 2035-01-20
AI Technical Summary
During the PVD process for preparing copper seed layers, high-energy particles may damage the TCO film, affecting its optical and electrical properties. Furthermore, the adhesion between the pure copper seed layer and the TCO film is poor, impacting the stability and reliability of the battery.
A copper alloy seed stack structure is adopted, including a copper alloy seed layer and a pure copper seed layer, which are disposed on a transparent conductive oxide film. By setting the copper alloy stack between the pure copper and the TCO contact surface, the bonding force is improved and the resistivity is reduced.
It effectively improves the bonding force between the seed layer and the grid lines in the copper grid cell, reduces resistivity and contact resistance, and enhances the oxidation resistance and reliability of the cell.
Smart Images
Figure CN223968150U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of silicon heterojunction solar cell technology, and in particular to a copper alloy seed stack structure. Background Technology
[0002] The primary function of the copper seed layer is to provide a conductive starting point on the transparent conductive oxide (TCO) film, laying the foundation for subsequent copper electroplating. The quality of the copper seed layer significantly impacts the performance of heterojunction solar cells, including photoelectric conversion efficiency, stability, and lifetime. During the preparation of the copper seed layer, the PVD process needs to be optimized to ensure that the copper seed layer has appropriate thickness, uniformity, and adhesion.
[0003] However, some challenges may be encountered in the preparation of the copper seed layer using the PVD process. For example, high-energy particles in the PVD process may damage the TCO film, affecting its optical and electrical properties. Furthermore, the adhesion between the copper seed layer and the TCO film needs to be sufficiently guaranteed to ensure the stability of the battery in subsequent processes and long-term operation.
[0004] To address these issues, researchers have continuously explored and optimized the fabrication techniques for copper seed layers. For example, they have improved the quality and performance of copper seed layers by modifying PVD process parameters and using specialized target materials. Currently, pure copper is used to fabricate seed layers for copper-grid heterojunction solar cells. Although pure copper seed layers possess good electrical conductivity, their thermal expansion coefficient is relatively high (16.6 × 10⁻⁶). -6 / ℃, while the thermal expansion coefficient of most TCOs is between 4.5 and 5.9 × 10. -6 The difference in thermal expansion coefficients between the two, at / ℃, can easily lead to poor bonding between pure copper and TCO at the interface, posing a challenge to the reliability of subsequent components and batteries. Utility Model Content
[0005] The present invention aims to at least improve one of the technical problems existing in the prior art. To this end, the present invention proposes a copper alloy seed stack structure.
[0006] According to the copper alloy seed stack structure of the first aspect of the present invention, it includes:
[0007] Blue membrane;
[0008] A copper alloy stack, the copper alloy stack comprising a copper alloy seed layer and a pure copper seed layer, wherein the copper alloy seed layer is disposed on the surface of the blue film, and the pure copper seed layer is disposed on the surface of the copper alloy seed layer away from the blue film.
[0009] Copper grid lines are disposed on the surface of the pure copper seed layer.
[0010] In one possible implementation of the first aspect, the blue diaphragm comprises:
[0011] Monocrystalline silicon wafers;
[0012] The intrinsic amorphous silicon layer is disposed on the surface of the monocrystalline silicon wafer.
[0013] A first doped layer is disposed on the surface of the intrinsic amorphous silicon layer;
[0014] A first semiconductor transparent conductive film is disposed on the surface of the first doped layer;
[0015] The second semiconductor transparent conductive film is disposed on the surface of the first semiconductor transparent conductive film.
[0016] In one possible implementation of the first aspect, the first doped layer is a microcrystalline silicon doped layer or an amorphous silicon doped layer.
[0017] In one possible implementation of the first aspect, the thickness of the copper alloy seed layer is 0 nm to 110 nm. A copper alloy seed layer within this range can improve the bonding force between the seed layer and the first semiconductor transparent conductive film.
[0018] In one possible implementation of the first aspect, the thickness of the pure copper seed layer is 0 nm to 110 nm, and a pure copper seed layer within this range can ensure that the entire seed layer has good conductivity.
[0019] In one possible implementation of the first aspect, the thickness of the first doped layer is 4 nm to 6 nm, which is used to improve the on-state voltage and fill factor of the battery.
[0020] In one possible implementation of the first aspect, the pure copper seed layer is a graphical seed layer.
[0021] In one possible implementation of the first aspect, the first semiconductor transparent conductive film is a TCO film containing a high-efficiency target material with a thickness of 50nm to 100nm, used to collect lateral charge carriers. The high-efficiency target material has low sheet resistance, high carrier mobility, and high transmittance, which can effectively improve the performance of the solar cell.
[0022] In one possible implementation of the first aspect, the second semiconductor transparent conductive film is an ITO film with a thickness of 0 nm to 50 nm, used to reduce the contact resistance between the TCO and the metal electrode, so that no Schottky barrier is generated when it contacts the metal electrode, thereby improving the efficiency of the metal electrode in collecting charge carriers.
[0023] According to the copper alloy seed stack structure of this utility model embodiment, by adopting the copper alloy seed stack structure of this utility model, specifically by setting a copper alloy stack between the pure copper and TCO contact surface, the bonding force between the copper alloy stack and the copper grid lines in the cell can be effectively improved. At the same time, the effects of increased sheet resistance and contact resistance caused by the copper alloy seed layer can also be appropriately reduced. This further enhances the oxidation resistance of the cell and ensures the reliability of the cell.
[0024] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0026] Figure 1 This is a schematic diagram of the copper alloy seed stack structure according to an embodiment of the present invention.
[0027] Figure label:
[0028] 100 monocrystalline silicon wafer, 200 intrinsic amorphous silicon layer, 300 first doped layer, 400 first semiconductor transparent conductive film, 500 second semiconductor transparent conductive film, 600 copper alloy seed layer, 700 pure copper seed layer, and 800 copper gate line. Detailed Implementation
[0029] The embodiments of this utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. It should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.
[0030] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0032] The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects and not to describe a particular order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, it may include a series of steps or units, or optionally, steps or units not listed, or other steps or units inherent to these processes, methods, products, or devices.
[0033] The accompanying drawings show only the portions relevant to this application, not all of them. Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations may be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process may correspond to a method, function, procedure, subroutine, subprogram, etc.
[0034] The terms “component,” “module,” “system,” “unit,” etc., used in this specification are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a unit can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or distributed between two or more computers. Furthermore, these units can be executed from various computer-readable media on which various data structures are stored. Units can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from a second unit interacting with another unit between a local system, a distributed system, and / or a network; for example, the Internet interacting with other systems via signals).
[0035] Example 1
[0036] See Figure 1 As shown, this embodiment provides a copper alloy seed stack structure, which includes:
[0037] Blue membrane, wherein the blue membrane includes:
[0038] 100 monocrystalline silicon wafers;
[0039] Intrinsic amorphous silicon layer 200 is disposed on the outer surface of monocrystalline silicon wafer 100;
[0040] The first doped layer 300 is disposed on the surface of the intrinsic amorphous silicon layer 200, which is far away from the single crystal silicon wafer 100.
[0041] The first semiconductor transparent conductive film 400, the first semiconductor transparent conductive film TCO thin film 400 is disposed on the surface of the first doped layer 300 away from the intrinsic amorphous silicon layer 200;
[0042] The second semiconductor transparent conductive film 500, the second semiconductor transparent conductive film ITO thin film 500 is disposed on the surface of the first semiconductor transparent conductive film 400 away from the first doped layer 300;
[0043] The fabrication of the blue film includes: first, texturing and cleaning a single-crystal silicon wafer 100, followed by a second passivation process. The front passivation layer consists of an intrinsic amorphous silicon layer 200 and an N-type doped layer, while the back passivation layer consists of an intrinsic amorphous silicon layer 200 and a P-type doped layer. Subsequently, a transparent conductive oxide (TCO, transparent conductive semiconductor film) layer is deposited on the surface of the front and back passivation layers using magnetron sputtering, thus obtaining a semi-finished blue film solar cell.
[0044] The copper alloy stack includes a copper alloy seed layer 600 and a pure copper seed layer 700, wherein the copper alloy seed layer 600 is disposed on the surface of the second semiconductor transparent conductive film 500 which is far away from the first semiconductor transparent conductive film 400, and the pure copper seed layer 700 is disposed on the surface of the copper alloy seed layer 600 which is far away from the second semiconductor transparent conductive film 500.
[0045] Copper grid lines 800 are distributed on the surface of pure copper seed layer 700, which is far away from copper alloy seed layer 600.
[0046] According to the copper alloy seed stack structure of this utility model embodiment, by adopting the copper alloy seed stack structure of this utility model, the bonding force between the seed layer and the grid line in the cell in the copper grid can be effectively improved. Specifically, a copper alloy stack is set between the pure copper and TCO contact surface, which can appropriately reduce the influence of the increased resistivity and increased contact resistance with the copper grid line electrode caused by the all-alloy copper seed layer, so that the tensile reliability can be guaranteed, the oxidation resistance of the cell is enhanced, and the cost performance is high.
[0047] It should be noted that the thickness of the copper alloy seed layer 600 is 20nm to 60nm. Based on this range, the copper alloy seed layer 600 can improve the bonding force between the seed layer and the first semiconductor transparent conductive film.
[0048] It should be noted that the copper alloy seed layer in this embodiment can be a combination of copper and any other metal, including but not limited to copper-molybdenum alloy, copper-nickel alloy, copper-manganese alloy, and copper-zirconium alloy. However, the concentration of other metals doped in the copper substrate is not limited to 0%-30%. By setting a copper alloy seed layer, the bonding force between the seed layer and the grid lines in the copper grid cell can be effectively improved, which can not only reduce the resistivity of the entire seed layer.
[0049] It should be noted that the thickness of the pure copper seed layer 700 is 0nm to 110nm. Based on this range, the pure copper seed layer 700 can ensure that the entire seed layer has good conductivity.
[0050] It should be noted that the thickness of the first doped layer 300 is 4nm to 6nm, which is beneficial to improving the overall performance of the battery with copper alloy seed stack structure.
[0051] It should be noted that the first semiconductor transparent conductive film 400 is a TCO film containing a high-efficiency target material with a thickness of 50nm to 100nm. It is used to collect lateral charge carriers. The high-efficiency target material has low sheet resistance, high carrier mobility, and high transmittance, which can effectively improve the performance of the solar cell.
[0052] It should be noted that in this embodiment, high-efficiency target material refers to a target material with low resistance, high carrier mobility, and high transmittance. Such target materials are generally called VTTO / HITO in the industry. Different target material manufacturing companies have different names, but all such high-efficiency target materials are TCO target materials.
[0053] It should be noted that the second semiconductor transparent conductive film 500 is an ITO film with a thickness of 0nm to 50nm. The low oxygen and high carrier concentration process conditions are used to reduce the contact resistance between the TCO and the metal electrode, so that a Schottky barrier is not generated when it comes into contact with the metal electrode, which can improve the efficiency of the metal electrode in collecting carriers.
[0054] It should be noted that the thickness of the intrinsic amorphous silicon layer 200 is 1nm to 3nm.
[0055] In this embodiment, a specific implementation example of a copper alloy seed stack structure is provided, which includes:
[0056] 100 monocrystalline silicon wafers;
[0057] Intrinsic amorphous silicon layer 200 is disposed on the surface of monocrystalline silicon wafer 100, wherein the thickness of intrinsic amorphous silicon layer 200 is 2nm.
[0058] A microcrystalline silicon doped layer is disposed on the surface of the intrinsic amorphous silicon layer 200, wherein the thickness of the microcrystalline silicon doped layer is 5nm, which is beneficial to improving the overall performance of the battery with copper alloy seed stack structure.
[0059] TCO film, TCO film is disposed on the surface of microcrystalline silicon doped layer, wherein the thickness of TCO film is 0nm~50nm, used to collect lateral charge carriers. The high efficiency target material has low sheet resistance, high charge carrier mobility and high transmittance, which can effectively improve the performance of solar cell.
[0060] An ITO film is disposed on the surface of a TCO film. The thickness of the ITO film is 0 nm to 50 nm. It is used to reduce the contact resistance between the TCO and the metal electrode, so that a Schottky barrier is not generated when it comes into contact with the metal electrode, which can improve the efficiency of the metal electrode in collecting charge carriers.
[0061] A copper alloy seed layer 600 is disposed on the surface of the ITO film. The thickness of the copper alloy seed layer 600 is 0 nm to 50 nm, which can improve the bonding force between the seed layer and the first semiconductor transparent conductive film.
[0062] A pure copper seed layer 700 is disposed on the surface of a copper alloy seed layer 600 that is far away from the ITO film. The pure copper seed layer 700 is a patterned seed layer with a thickness of 50nm to 100nm, which can ensure that the entire seed layer has excellent conductivity.
[0063] Copper grid lines 800 are distributed on the surface of the pure copper seed layer 700.
[0064] The experimental data of the battery silicon wafers based on the partial copper alloy seed stacked structure in this embodiment and the existing stacked structure are shown in Tables 1 to 4 below:
[0065] Table 1: Experimental reference group data for pure copper and copper-molybdenum alloy
[0066]
[0067] Table 2: Experimental reference group data for pure copper and copper-nickel alloy
[0068]
[0069] Table 3: Experimental reference group data for pure copper and copper-manganese alloy
[0070]
[0071] Table 4: Experimental reference group data for pure copper and copper-zirconium alloy
[0072]
[0073] Tests have shown that the seed layer stacking scheme of this invention can effectively improve the bonding force between the seed layer and the grid lines in the copper grid cell, while not significantly affecting the contact resistance between the entire seed layer and the grid lines.
[0074] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the utility model.
[0075] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.
[0076] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The reference to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with an embodiment can be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily indicate the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0077] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.
Claims
1. A copper alloy seed stack structure, characterized by, The application relates to a blue film piece and a copper alloy laminated layer. The blue film piece comprises: a copper alloy copper seed layer and a pure copper seed layer, wherein the copper alloy copper seed layer is arranged on the surface of the blue film piece, and the pure copper seed layer is arranged on the surface of the copper alloy copper seed layer away from the blue film piece; a copper grid line arranged on the surface of the pure copper seed layer.
2. The copper alloy seed stack structure of claim 1, wherein The thickness of the copper alloy copper seed layer is 0-110 nm.
3. The copper alloy seed stack structure of claim 1, wherein The thickness of the pure copper seed layer is 0-110 nm.
4. The copper alloy seed stack structure of claim 1, wherein The pure copper seed layer is a patterned seed layer.
5. The copper alloy seed stack structure of claim 1, wherein The blue film piece comprises: a single crystal silicon piece; an intrinsic amorphous silicon layer arranged on the surface of the single crystal silicon piece; a first doped layer arranged on the surface of the intrinsic amorphous silicon layer; a first semiconductor transparent conductive film arranged on the surface of the first doped layer; a second semiconductor transparent conductive film arranged on the surface of the first semiconductor transparent conductive film.
6. The copper alloy seed stack structure of claim 5, wherein The first doped layer is a microcrystalline silicon doped layer.
7. The copper alloy seed stack structure of claim 5, wherein The thickness of the intrinsic amorphous silicon layer is 1-3 nm.
8. The copper alloy seed stack structure of claim 6, wherein, The thickness of the first doped layer is 4-6 nm.
9. The copper alloy seed stack structure of claim 5, wherein, The first semiconductor transparent conductive film is a transparent conductive oxide film containing high-efficiency target material, and has high carrier mobility, high transmittance and a thickness of 50-100 nm.