Solar cell

Abstract

The utility model discloses a solar cell. The solar cell comprises a silicon substrate, a first doping layer, a tunneling layer, a gradient doping structure, a first electrode and a second electrode. The silicon substrate comprises a first surface and a second surface which are oppositely arranged, a light trapping structure is formed on the first surface, the second surface comprises a grid line area and a non-grid line area, and a groove is formed in the grid line area; the first doping layer is located on the first surface; the tunneling layer is located in the groove; the gradient doping structure is stacked on the tunneling layer, the gradient doping structure comprises at least two doping layers, and the doping concentrations of the multiple doping layers are different and change layer by layer; the first electrode is positioned on the first surface and is in contact with the first doping layer; and the second electrode is in contact with the gradient doping structure in the groove. According to the solar cell, the efficiency of the solar cell can be improved.

Description

Technical Field

[0001] This utility model belongs to the field of solar cell technology, and specifically relates to a solar cell. Background Technology

[0002] Compared to traditional PERC cells, TOPCon (Tunnel Oxide Passivated Contact) cells are characterized by an ultra-thin tunneling layer and a doped polycrystalline silicon layer on the back of the silicon substrate. This improves the passivation performance of the cell surface, reduces the metal contact recombination current, and effectively increases the open-circuit voltage and short-circuit current of the cell.

[0003] Methods for fabricating tunneling layers on the back side of silicon substrates in TOPCon solar cells include LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), and ALD (atomic layer deposition). Methods for fabricating doped polycrystalline silicon layers on the back side of silicon substrates in TOPCon solar cells mainly include LPCVD, PECVD, and PVD (physical vapor deposition).

[0004] All of the aforementioned methods for preparing doped polycrystalline silicon layers can perform in-situ doping, meaning that polycrystalline silicon layer deposition and phosphorus doping are completed in the same step. However, compared to PECVD, LPCVD and PVD are more difficult to implement, and the distribution of phosphorus (P) in the doped polycrystalline silicon layer cannot be accurately controlled. Although PECVD can achieve in-situ doping relatively more easily, it also cannot accurately control the distribution of P in the doped polycrystalline silicon layer, and requires a subsequent high-temperature annealing process to achieve the transformation from amorphous silicon to polycrystalline silicon, as well as the excitation and redistribution of P atoms.

[0005] Furthermore, the introduction of the tunneling layer and doped polysilicon layer on the back side of the TOPCon cell silicon substrate also exacerbates current loss caused by parasitic absorption on the back side of the cell. Although thinning the tunneling layer and doped polysilicon layer can reduce current loss due to parasitic absorption on the back side, it cannot be completely eliminated and will also cause problems such as weakened passivation performance.

[0006] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0007] The purpose of this invention is to provide a solar cell that can solve the problems in the prior art.

[0008] To achieve the above objectives, the technical solution provided by a specific embodiment of this utility model is as follows:

[0009] A silicon substrate, the silicon substrate including a first surface and a second surface disposed opposite to each other, a light trapping structure formed on the first surface, and the second surface including a gate line region and a non-gate line region, wherein a groove is formed on the gate line region;

[0010] A first doped layer is located on the first surface;

[0011] A tunneling layer is located within the groove;

[0012] A gradient doped structure is stacked on the tunneling layer. The gradient doped structure includes at least two doped layers, and the doping concentration of the multiple doped layers is different and changes layer by layer.

[0013] The first electrode is located on the first surface and is in contact with the first doped layer;

[0014] The second electrode is in contact with the gradient doped structure within the groove.

[0015] In one or more embodiments of the present invention, the gradient doping structure includes: a third doped layer disposed close to the tunneling layer and a second doped layer disposed away from the tunneling layer, wherein the doping concentration of the third doped layer is less than the doping concentration of the second doped layer.

[0016] In one or more embodiments of the present invention, the gradient doping structure includes at least one fourth doping layer, the fourth doping layer being located between the second doping layer and the third doping layer, and the doping concentration of the fourth doping layer being less than the doping concentration of the second doping layer and greater than the doping concentration of the third doping layer.

[0017] In one or more embodiments of this invention, the tunneling layer is located on the bottom and side walls of the groove.

[0018] In one or more embodiments of the present invention, the grid line region includes a plurality of first sub-regions that are parallel and equally spaced, and a groove is formed in each of the first sub-regions.

[0019] In one or more embodiments of this utility model, the depth of the groove is 0.2μm-5μm, and the width of the groove is 20μm-100μm.

[0020] In one or more embodiments of this utility model, the second electrode is located within the groove; and / or,

[0021] The width of the second electrode is smaller than the width of the groove; and / or,

[0022] The sum of the thicknesses of the gradient doped structure and the tunneling layer is less than the depth of the groove.

[0023] In one or more embodiments of this utility model, the thickness of the gradient doped structure is 80nm-120nm, and the thickness of the multiple doped layers within the gradient doped structure increases from the direction away from the tunneling layer; and / or,

[0024] The doping concentration range of the third doped layer is 5E18cm⁻¹. -3 -5E19cm -3 The doping concentration range of the second doped layer is 5E20cm. -3 -5E21cm -3 .

[0025] In one or more embodiments of this utility model, the doping concentration of the first doped layer is 1E19cm. -3 -9E19cm -3 .

[0026] In one or more embodiments of this utility model, the solar cell further includes:

[0027] A first passivation layer is formed on the surface of the first doped layer opposite to the silicon substrate;

[0028] A first anti-reflection layer is formed on the surface of the first passivation layer that is opposite to the first doped layer;

[0029] A second passivation layer is formed on the second surface; and

[0030] The second anti-reflection layer is formed on the second passivation layer.

[0031] In one or more embodiments of this utility model, the first passivation layer includes one or more combinations of an aluminum oxide layer and a gallium oxide layer; and / or,

[0032] The second passivation layer includes one or more combinations of aluminum oxide and gallium oxide; and / or,

[0033] The first antireflection layer includes one or more combinations of silicon nitride, silicon oxynitride, and silicon oxide; and / or,

[0034] The second antireflection layer includes one or more combinations of silicon nitride layer and silicon oxynitride layer.

[0035] A method for preparing a solar cell, the method comprising the following steps:

[0036] A silicon substrate is provided, the silicon substrate including a first surface and a second surface disposed opposite to each other, the second surface including a gate line region and a non-gate line region;

[0037] A groove is formed in the grid line area;

[0038] A tunneling layer, a gradient doped structure, and an oxide layer are sequentially stacked on the second surface;

[0039] Remove the oxide layer and part of the gradient doped structure on the non-gate line region and the oxide layer on the gate line region, and crystallize the gradient doped structure.

[0040] A second electrode is prepared to contact the gradient doped structure within the groove.

[0041] In one or more embodiments of this utility model, the groove is formed on the gate line area using a laser process, wherein the laser power in the laser process is 30W-70W and the laser pulse width is 3ns-50ns.

[0042] In one or more embodiments of this utility model, the depth of the groove is 0.2μm-5μm, and the width of the groove is 20μm-100μm.

[0043] In one or more embodiments of this utility model, the width of the second electrode is smaller than the width of the groove.

[0044] In one or more embodiments of this utility model, the thickness of the gradient doped structure is 80nm-120nm, and the thickness of each doped layer increases from the direction away from the tunneling layer; and / or,

[0045] The doping concentration range of the doped layer near the tunneling layer is: 5E18cm -3 -5E19cm -3 The doping concentration range of the doped layer furthest from the tunneling layer is: 5E20cm. -3 -5E21cm -3 .

[0046] In one or more embodiments of this utility model, a laser process is used to remove the oxide layer and part of the graded doped structure on the non-gateline region and the oxide layer on the gateline region. The laser power in the laser process is 20W-220W, the laser is a picosecond laser, and the overlap ratio ranges from 0-50%; or,

[0047] Chemical etching is used to remove the oxide layer and part of the gradient doped structure on the non-gate line region, as well as the oxide layer on the gate line region.

[0048] In one or more embodiments of this utility model, the preparation method further includes:

[0049] After removing the oxide layer and some gradient doped structures on the non-gateline regions, the non-gateline regions are wet-cleaned to remove the remaining gradient doped structures and tunneling layers.

[0050] In one or more embodiments of the present invention, the gradient doped structure before crystallization includes multiple layers of amorphous silicon doped layers stacked sequentially, and the gradient doped structure after crystallization includes multiple layers of polycrystalline silicon doped layers stacked sequentially.

[0051] The crystallization process is carried out using laser technology or high-temperature annealing process.

[0052] The laser power in the laser process is 20W-220W, the laser pulse is a picosecond pulse, and the frequency is 100KHz-500KHz.

[0053] The annealing time in the high-temperature annealing process is 110-130 minutes, and the annealing temperature is 880℃-920℃.

[0054] In one or more embodiments of this utility model, the preparation method further includes:

[0055] A light-trapping structure is fabricated on the first and second surfaces of the silicon substrate using a texturing process; and / or,

[0056] The second surface of the silicon substrate is polished before the tunneling layer is prepared.

[0057] In one or more embodiments of this utility model, the preparation method further includes:

[0058] A first doped layer is prepared on the first surface; and,

[0059] A first electrode is prepared on the first surface to contact the first doped layer;

[0060] The doping concentration of the first doped layer is 1E19cm. -3 -9E19cm -3 .

[0061] In one or more embodiments of this utility model, the preparation method further includes:

[0062] A first passivation layer and / or a first antireflection layer are formed on a first surface of the silicon substrate; and / or,

[0063] A second passivation layer and / or a second antireflection layer are prepared on the second surface of the silicon substrate.

[0064] In one or more embodiments of the present invention, the step of forming the gradient doped structure includes: forming at least two intrinsic layers in a groove in a first region, and after each intrinsic layer is formed, performing phosphorus doping on the intrinsic layer to form at least two doped layers; the doping concentration of the doped layers increases in the direction away from the tunneling layer.

[0065] Compared with the prior art, the solar cell preparation method and solar cell of the present invention, by setting a groove and setting a gradient doping structure inside the groove, and printing the second electrode inside the groove, increases the contact area, reduces the contact resistance, and reduces the current loss caused by parasitic absorption.

[0066] The present invention discloses a method for preparing solar cells and a solar cell in which the distribution of doping sources in the gradient doping structure can be accurately controlled by setting up a multilayer doping layer with gradually varying doping concentration, thereby improving the efficiency of TOPcon solar cells.

[0067] The present invention discloses a method for fabricating a solar cell and a solar cell that, through differentiated treatment of the gradient doping structure on the second surface of the silicon substrate in the grid line region and the non-grid line region, completely removes the gradient doping structure in the non-grid line region, effectively reducing the parasitic absorption effect of the gradient doping structure in the non-grid line region and improving the bifaciality of the solar cell.

[0068] The present invention discloses a method for preparing solar cells and a solar cell that uses laser annealing to replace the traditional high-temperature annealing process, thereby avoiding the energy consumption reduction caused by high-temperature annealing, greatly reducing the process time, and improving the preparation efficiency.

[0069] The method for preparing the solar cell and the solar cell of this invention can increase optical absorption and improve the efficiency of the solar cell. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0071] Figure 1 This is a process flow diagram of the method for preparing the solar cell of this utility model;

[0072] Figures 2a-2j This is a flowchart illustrating the process steps of the solar cell fabrication method in Embodiment 1 of this utility model;

[0073] Figures 3a-3jThis is a flowchart illustrating the process steps of the solar cell fabrication method in Embodiment 2 of this utility model;

[0074] Figure 4 for Figure 3j A schematic diagram of the local structure at point A in the middle;

[0075] Figure 5 This is a structural diagram of the solar cell in Embodiment 4 of this utility model;

[0076] Figure 6 for Figure 5 A schematic diagram of the local structure at point B. Detailed Implementation

[0077] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0078] As mentioned in the background section, the fabrication method for the doped polycrystalline silicon layer on the back side of the silicon substrate in existing TOPcon solar cells is typically as follows: first, a P-doped amorphous silicon layer is formed, followed by high-temperature annealing to excite and redistribute P atoms, allowing the P-doping source to slowly penetrate into the amorphous silicon layer under the action of high-temperature annealing, thus achieving the transformation of the P-doped amorphous silicon layer into a polycrystalline silicon layer. However, the penetration rate of the P-doping source in the polycrystalline silicon layer under the action of high-temperature annealing is unstable, therefore, it is impossible to accurately control the distribution of the P-doping source in the polycrystalline silicon layer, thereby affecting the efficiency of the TOPcon solar cell. Secondly, the introduction of the tunneling layer and the doped polycrystalline silicon layer on the back side of the silicon substrate in TOPcon cells leads to increased current loss caused by parasitic absorption on the back side of the cell, resulting in problems such as weakened passivation performance.

[0079] Based on this, this application provides a method for fabricating a solar cell and the solar cell itself. By forming a groove on the second surface of a silicon substrate and creating a gradient doping structure within the groove, a second electrode is printed inside the groove. This increases the contact area, reduces contact resistance, and minimizes current loss caused by parasitic absorption. By setting multiple doped layers with varying doping concentrations to form a gradient doped structure, the doping sources within each doped layer can be redistributed during subsequent excitation of the doping source. This allows for precise control of the doping source distribution within the gradient doped structure, thereby improving the efficiency of the TOPcon solar cell.

[0080] like Figure 1As shown, a method for preparing a solar cell in one embodiment of this utility model includes the following steps:

[0081] S1, a silicon substrate is provided, the silicon substrate includes a first surface and a second surface disposed opposite to each other, the second surface includes a gate line region and a non-gate line region.

[0082] S2, forming a groove in the grid area.

[0083] S3, a tunneling layer, a gradient doped structure, and an oxide layer are formed sequentially on the second surface.

[0084] S4, remove the oxide layer and part of the gradient doped structure on the non-gate line region and the oxide layer on the gate line region, and perform crystallization treatment on the gradient doped structure.

[0085] S5, prepare a second electrode that contacts the gradient doped structure in the groove.

[0086] In step S2, a laser process can be used to form the groove. The laser power in the laser process is 30W-70W, and the laser pulse width is 3ns-50ns. The depth of the formed groove is 0.2μm-5μm, preferably 0.2μm-2μm. The width of the groove is 20μm-100μm, preferably 20μm-50μm. The groove within this depth range reduces damage to the silicon substrate, improves the passivation effect of the battery, and facilitates the subsequent setting of the second electrode and the gradient doped structure, increasing the contact area between these two and the groove, reducing contact resistance, and improving battery performance.

[0087] Before step S2, a light-trapping structure can be fabricated on the first and second surfaces of the silicon substrate using a texturing process. Before step S3, the second surface of the silicon substrate is then wet-polished to repair any damage. The light-trapping structure increases optical absorption, thereby improving the efficiency of the solar cell.

[0088] Before or after step S2, preferably after step S2, a first doped layer may be formed on the first surface of the silicon substrate, and a first electrode in contact with the first doped layer may be formed on the first surface before, simultaneously with, or after step S5. The first doped layer may be formed by a diffusion process or deposited by a PECVD process, and the doping concentration of the first doped layer is 1E19cm⁻¹. -3 -9E19cm -3 .

[0089] In step S3, the gradient doped structure comprises multiple layers of doped layers stacked sequentially, with the doping concentration of each layer gradually increasing away from the tunneling layer. The total thickness of the gradient doped structure is 80nm-120nm, wherein the thickness of each doped layer increases away from the tunneling layer. For example, taking four doped layers, the thickness of the doped layers decreases sequentially from the outermost to the innermost (closest to the tunneling layer), with thicknesses ranging from 35nm-45nm, 25nm-35nm, 15nm-25nm, and 5nm-15nm respectively. The doping concentration of the innermost (closest to the tunneling layer) doped layer ranges from 5E18cm⁻¹. -3 -5E19cm -3 The doping concentration of the outermost (farthest from the tunneling layer) doped layer ranges from 5E20cm. -3 -5E21cm -3 .

[0090] In step S4, the oxide layer on the non-gateline region, part of the gradient doped structure, and the oxide layer on the gateline region of the second surface can be removed first by chemical etching. For example, the oxide layer on the surface is first etched using HF, and then the gradient doped structure is cleaned using KOH or NaOH. Then, a high-temperature annealing process is used to anneal the gradient doped structure on the gateline region to crystallize the gradient doped structure. The high-temperature annealing temperature is 880℃-920℃, and the annealing time is 110min-130min, preferably 120min.

[0091] Alternatively, a laser process can be used to remove the oxide layer, part of the gradient doped structure, and the oxide layer on the gate line region of the second surface. The laser used is a picosecond-level laser with a power range of 20W-220W and an overlap ratio range of 0-50%. Then, a high-temperature annealing process is used to anneal the gradient doped structure on the gate line region to crystallize the structure. The high-temperature annealing temperature is 880℃-920℃, and the annealing time is 110min-130min, preferably 120min.

[0092] However, it is understandable that high-temperature annealing processes have the following drawbacks: 1) unstable product quality; 2) long processing time; 3) high requirements for the working environment. These drawbacks may have a certain adverse impact on the fabrication of the solar cells described in this application, such as longer fabrication time and lower fabrication efficiency.

[0093] Based on this, in order to achieve better solar cell fabrication, in step S4 of this application, preferably, a laser process is used to remove the oxide layer, part of the gradient doped structure, and the oxide layer on the grid line region of the second surface. Simultaneously, during the laser removal of the oxide layer on the grid line region, the gradient doped structure on the grid line region can be laser annealed to crystallize the gradient doped structure. The laser power in the laser process is 20W-220W, the laser pulse is a picosecond pulse, the frequency is 100KHz-500KHz, and the overlap rate ranges from 0-50%. The gradient doped structure before laser processing includes multiple layers of sequentially stacked amorphous silicon doped layers. While removing the oxide layer, part of the gradient doped structure, and the oxide layer on the grid line region, the instantaneous high temperature (800℃-1000℃) of the laser excites the doping source of the amorphous silicon doped layer in the groove of the grid line region, crystallizing the amorphous silicon doped layer and transforming it into a polycrystalline silicon doped layer.

[0094] Furthermore, the introduction of gradient doped structures on the non-gateline regions of the second surface of the silicon substrate exacerbates current loss caused by parasitic absorption on the second surface. Although thinning the gradient doped structure can reduce current loss due to parasitic absorption on the second surface, it cannot eliminate the current loss problem and also leads to problems such as reduced passivation performance.

[0095] Based on this, in order to solve the above-mentioned technical problems, the preparation method of this application completely removes the gradient doping structure and tunneling layer on the non-gateline region of the second surface, further reducing the parasitic absorption problem of the second surface.

[0096] It is understandable that directly using laser technology to completely remove the gradient doped structure and tunneling layer in the non-gate region would cause some damage to the second surface during the removal process, thus affecting the performance of the subsequent solar cell. Therefore, in the fabrication method of this application, a laser process is used to remove the oxide layer and part of the gradient doped structure on the non-gate region, retaining a relatively thin gradient doped structure as a laser etching buffer layer. Then, wet cleaning is used to remove the PSG in the non-gate region and the remaining gradient doped structure and tunneling layer that served as the laser etching buffer layer, while simultaneously repairing the second surface. This step can thoroughly clean and remove the gradient doped structure and tunneling layer in the non-gate region without damaging the second surface, reducing parasitic absorption problems.

[0097] The wet cleaning process removes PSG from the non-gate area and the remaining gradient doped structure and tunneling layer that serve as a buffer layer for laser etching. Specifically, it includes the following steps: first, acid washing removes PSG and oxide layer from the surface; then, alkaline washing removes the remaining gradient doped structure; finally, acid washing removes the tunneling layer; then, hydrochloric acid washing removes metal ions; and finally, water washing and drying.

[0098] Before step S5, a second passivation layer and / or a second antireflection layer can also be prepared on the second surface of the silicon substrate. Meanwhile, a first passivation layer and / or a first antireflection layer are prepared on the first surface of the silicon substrate. Both the first passivation layer and the second passivation layer can include one or more combinations of an alumina layer and a gallium oxide layer. Both the first antireflection layer and the second antireflection layer can include one or more combinations of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0099] In step S5, a second electrode in contact with the graded doping structure is prepared in the groove, and the width of the second electrode is smaller than the width of the groove.

[0100] The preparation method of the solar cell of the present utility model will be further described below in conjunction with specific embodiments.

[0101] Embodiment 1:

[0102] 1. Double-sided texturing

[0103] Refer Figure 2a As shown, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 that are oppositely arranged. The second surface S2 includes a grid line region S21 and a non-grid line region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the backlight surface) of the silicon substrate 10. The grid line region S21 is the back metal region, and the non-grid line region S22 is the back non-metal region. The silicon substrate 10 is processed in a texturing chemical liquid tank to form a pyramid texture structure on the first surface S1 and the second surface S2 of the silicon substrate 10 through an alkali texturing process.

[0104] 2. Grooving

[0105] Refer Figure 2b As shown, single-sided patterning treatment is performed on the grid line region S21 of the second surface S2 of the silicon substrate 10 by laser to form a plurality of parallel and equally spaced grooves 12. Among them, the laser power is 30W - 70W, and the laser pulse width is 3ns - 50ns. The etching depth of the formed grooves 12 is 0.2μm - 5μm, preferably 0.2μm - 20μm; the etching width is 20μm - 100μm, preferably 20μm - 50μm. The mask pattern used for grooving needs to be consistent with the mask pattern of screen printing used for subsequent preparation of the second electrode.

[0106] In this embodiment, the grid line region S21 includes a plurality of parallel and equally spaced first sub-regions, the non-grid line region S22 includes a plurality of parallel and equally spaced second sub-regions, and the first sub-regions and the second sub-regions are staggered. One groove 12 is formed in each first sub-region.

[0107] 3. Boron diffusion

[0108] As shown Figure 2c in FIG. 1, a P-type doped first doping layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, in a high-temperature furnace tube, a boron source deposition and propulsion method is used for diffusion. After diffusion, the doping concentration of the first doping layer 11 is 1E19 cm -3 -9E19 cm -3 . In the boron diffusion process, BSG is also formed on the second surface S2 of the silicon substrate.

[0109] 4. Backside polishing

[0110] As shown Figure 2d in FIG. 2, the grooved silicon substrate 10 is cleaned by wet cleaning to remove the patterned textured structure (the textured structure on the non-grid line area and the textured structure on the grid line area), and the damage caused by laser grooving is repaired. Specifically, the grooved silicon substrate 10 is first passed through a single-sided chain device, and the silicon oxide on the second surface is removed by a hydrofluoric acid solution. Then, the second surface is polished with an alkali to remove the edge junction and backside plating (BSG), and finally, it is cleaned again.

[0111] 5. Preparation of backside tunneling passivation structure

[0112] As shown Figure 2e in FIG. 3, a tunneling layer 13, a graded doping structure 14, and an oxide layer 15 are sequentially stacked on the second surface S2.

[0113] Exemplarily, in this embodiment, a silicon oxide tunneling layer is first deposited on the second surface by PECVD process. Among them, the flow rate of N2O introduced is 8000 sccm - 15000 sccm, the power is 8000 W - 15000 W, and the deposition time is 80 s - 150 s.

[0114] Then, multiple layers of phosphorus-doped amorphous silicon layers (doping layers) with different doping concentrations are deposited step by step. Specifically, multiple intrinsic layers (undoped amorphous silicon layers) are first formed, and after each intrinsic layer is formed, the intrinsic layer is subjected to phosphorus doping treatment to form a phosphorus-doped amorphous silicon layer (doping layer). The total thickness of the phosphorus-doped amorphous silicon layer (doping layer) is 80 nm - 120 nm, and the thickness of each phosphorus-doped amorphous silicon layer increases in the direction away from the tunneling layer 13. For the multiple layers of phosphorus-doped amorphous silicon layers with different doping concentrations, the doping concentration gradually increases in the direction away from the silicon oxide tunneling layer. The phosphorus atom content in the phosphorus-doped amorphous silicon layer closest to the silicon oxide tunneling layer is the lowest, and the doping concentration range is 5E18 cm -3 -5E19 cm -3 , and the phosphorus atom content in the phosphorus-doped amorphous silicon layer farthest from the silicon oxide tunneling layer is the highest, and the doping concentration range is 5E20 cm -3 -5E21 cm -3The multi-layer phosphorus-doped amorphous silicon layers with different doping concentrations can be two layers or more than two layers. The doping source - phosphorus source can be PH3 or POCl3.

[0115] The oxide layer can be SiO X , SiO X N Y or SiN X .

[0116] 6. Laser etching and laser annealing

[0117] As shown in Figure 2f , a laser process is used to treat the oxide layer 15, the graded doping structure 14 on the non-gate line region S22, and the oxide layer 15 on the gate line region S21. The laser etching removes the oxide layer 15 and part of the graded doping structure 14 on the non-gate line region S22, and the laser etching removes the oxide layer 15 on the gate line region S21. At the same time, the instantaneous high temperature of the laser excites the P atoms in the graded doping structure 14 in the groove 12 on the gate line region S21, and crystallizes the graded doping structure 14 in the groove 12.

[0118] In this embodiment, the graded doping structure 14 before the laser process treatment includes multiple layers of phosphorus-doped amorphous silicon layers. The laser process can crystallize the phosphorus-doped amorphous silicon layer in the groove 12 and activate phosphorus, converting the phosphorus-doped amorphous silicon layer into a phosphorus-doped polycrystalline silicon layer.

[0119] Specifically, the laser is a picosecond laser, the laser power range is 20W - 220W, the overlap rate range is 0 - 50%, and the frequency is 100KHz - 500KHz. After the laser process treatment, the doping concentration of phosphorus atoms in the phosphorus-doped polycrystalline silicon layer closest to the tunneling layer 13 is 5E18cm -3 -5E19cm -3 , and the doping concentration of phosphorus atoms in the phosphorus-doped polycrystalline silicon layer farthest from the tunneling layer 13 is 5E20cm -3 -5E21cm -3 .

[0120] 7. Wet passivation cleaning

[0121] As shown in Figure 2g , a wet passivation process is used to remove all the graded doping structure 14 and the tunneling layer 13 on the non-gate line region S22, and at the same time remove the edge PSG and repair the damage caused to the second surface during the laser etching process.

[0122] This step specifically includes:

[0123] Pickling: An acid solution is used to remove the surface PSG and oxide layer;

[0124] Alkaline etching: An alkaline solution is used to remove all the graded doping structures 14 on the non-grid line area S22, and at the same time, the front side and the edge overplating are removed;

[0125] Pickling: An acid solution is used to remove the tunneling layer 13 on the non-grid line area S22;

[0126] Finally, hydrochloric acid is used for cleaning to remove metal ions, and then it is washed with water and dried.

[0127] Preferably, the acid solution in this embodiment is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~ 40%) and water in a certain proportion, and the alkaline solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~ 32%) and water in a certain proportion.

[0128] 8. Preparation of the passivation layer

[0129] Refer to Figure 2h As shown, the first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 by the ALD process. Both the first passivation layer 21 and the second passivation layer 22 are alumina passivation layers.

[0130] After the steps of removing overplating and wet chemical etching, there is no passivation layer protection on the second surface. Therefore, while preparing the first passivation layer on the front side (the first surface), it is necessary to simultaneously prepare the second passivation layer on the back side (the second surface).

[0131] 9. Preparation of the antireflection layer

[0132] Refer to Figure 2i As shown, the first antireflection layer 31 and the second antireflection layer 32 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 by the PECVD process. The first antireflection layer 31 and the second antireflection layer 32 can be a stacked film formed by any one or more of silicon nitride layer, silicon oxynitride layer, and silicon oxide layer.

[0133] 10. Printing of metal electrodes

[0134] Refer to Figure 2j As shown, the first electrode 41 and the second electrode 42 are respectively printed on the front side and the back side by the screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form an ohmic contact.

[0135] The first electrode 41 and the second electrode 42 are grid line electrodes in the prior art, and usually include main grid lines and fine grid lines.

[0136] Through the above steps, the TOPCon solar cell can be prepared. Finally, the solar cells are tested, sorted, and stored in the warehouse.

[0137] Example 2

[0138] 1. Double-sided texturing

[0139] As shown Figure 3a As shown, a silicon substrate 10 is provided. The silicon substrate 10 includes a first surface S1 and a second surface S2 which are oppositely arranged. The second surface S2 includes a gate line region S21 and a non-gate line region S22. The first surface S1 is the front surface (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back surface (i.e., the backlight surface) of the silicon substrate 10. The gate line region S21 is a back metal region, and the non-gate line region S22 is a back non-metal region. The silicon substrate 10 is processed in a texturing chemical bath to form a pyramid texturing structure on the first surface S1 and the second surface S2 of the silicon substrate 10 through an alkaline texturing process.

[0140] 2. Boron diffusion

[0141] As shown Figure 3b As shown, a P-type doped first doping layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 through a boron diffusion process. Specifically, diffusion is carried out in a high-temperature furnace tube using a boron source deposition and propulsion method. After diffusion, the doping concentration of the first doping layer 11 is 1E19 cm -3 -9E19 cm -3 . In the boron diffusion process, BSG is also formed on the second surface S2 of the silicon substrate.

[0142] 3. Grooving

[0143] As shown Figure 3c As shown, single-sided patterning treatment is carried out on the gate line region S21 of the second surface S2 of the silicon substrate 10 through a laser to form a plurality of grooves 12 that are parallel and equally spaced. Among them, the laser power is 30W - 70W, and the laser pulse width is 3ns - 50ns. The etching depth of the formed grooves 12 is from 0.2μm to 5μm, preferably from 0.2μm to 20μm; the etching width is from 20μm to 100μm, preferably from 20μm to 50μm. The mask pattern used for grooving needs to be consistent with the mask pattern used for screen printing in the subsequent preparation of the second electrode.

[0144] In this embodiment, the gate line region S21 includes a plurality of first sub-regions that are parallel and equally spaced, the non-gate line region S22 includes a plurality of second sub-regions that are parallel and equally spaced, and the first sub-regions and the second sub-regions are staggered. One groove 12 is formed in each first sub-region.

[0145] 4. Backside polishing

[0146] As shown Figure 3dAs shown, the grooved silicon substrate 10 is subjected to wet cleaning to remove the patterned suede structure (the suede structure on the non-grid line area and the suede structure on the grid line area), and the damage caused by laser grooving is repaired. Specifically, the grooved silicon substrate 10 is first passed through a single-sided chain device, and the silicon oxide on the second surface is removed using a hydrofluoric acid solution, and then the second surface is subjected to alkaline polishing to remove edge junctions and backside plating (BSG), and finally cleaning is performed.

[0147] 5. Preparation of Backside Tunneling Passivation Structure

[0148] Refer Figure 3e As shown, a tunneling layer 13, a graded doping structure 14, and an oxide layer 15 are sequentially stacked on the second surface S2.

[0149] Exemplarily, in this embodiment, a PECVD process is used to first deposit a silicon oxide tunneling layer on the second surface. Among them, the flow rate of N2O introduced is 8000 sccm - 15000 sccm, the power is 8000 W - 15000 W, and the deposition time is 80 s - 150 s.

[0150] Then, multiple layers of phosphorus-doped amorphous silicon layers (doped layers) with different doping concentrations are deposited step by step. Specifically, multiple intrinsic layers (undoped amorphous silicon layers) are first formed, and after each intrinsic layer is formed, the intrinsic layer is subjected to phosphorus doping treatment to form a phosphorus-doped amorphous silicon layer (doped layer). The total thickness of the phosphorus-doped amorphous silicon layer (doped layer) is 80 nm - 120 nm, and the thickness of each phosphorus-doped amorphous silicon layer increases in the direction away from the tunneling layer 13. For multiple layers of phosphorus-doped amorphous silicon layers with different doping concentrations, the doping concentration gradually increases in the direction away from the silicon oxide tunneling layer. The phosphorus atom content in the phosphorus-doped amorphous silicon layer closest to the silicon oxide tunneling layer is the lowest, and the doping concentration range is 5E18 cm -3 -5E19 cm -3 , and the phosphorus atom content in the phosphorus-doped amorphous silicon layer farthest from the silicon oxide tunneling layer is the highest, and the doping concentration range is 5E20 cm -3 -5E21 cm -3 . The multiple layers of phosphorus-doped amorphous silicon layers with different doping concentrations can be two layers or more than two layers. The doping source - phosphorus source can be PH3 or POCl3. The oxide layer can be SiO X , SiO X N Y Or SiN X .

[0151] 6. Laser Etching and High-Temperature Annealing

[0152] Refer Figure 3fAs shown, the oxide layer 15, the graded doping structure 14 on the non-grid line region S22, and the oxide layer 15 on the grid line region S21 are processed by a laser process. The oxide layer 15 and part of the graded doping structure 14 on the non-grid line region S22 are removed by laser etching, and the oxide layer 15 on the grid line region S21 is removed by laser etching. Then, a high-temperature annealing process is used to activate the P atoms in the graded doping structure 14 in the groove 12 on the grid line region S21, and the graded doping structure 14 in the groove 12 is crystallized.

[0153] In this embodiment, the graded doping structure 14 before the high-temperature annealing process includes multiple layers of phosphorus-doped amorphous silicon layers. The high-temperature annealing process can crystallize the phosphorus-doped amorphous silicon layers in the groove 12, activate phosphorus, and convert the phosphorus-doped amorphous silicon layers into phosphorus-doped polycrystalline silicon layers.

[0154] Specifically, the specific conditions of the high-temperature annealing process are: the high-temperature annealing temperature is 880°C - 920°C, the annealing time is 110 min - 130 min, preferably 120 min. After the high-temperature annealing process, the doping concentration of phosphorus atoms in the phosphorus-doped polycrystalline silicon layer closest to the tunneling layer 13 is 5E18 cm -3 -5E19 cm -3 , and the doping concentration of phosphorus atoms in the phosphorus-doped polycrystalline silicon layer farthest from the tunneling layer 13 is 5E20 cm -3 -5E21 cm -3 .

[0155] 7. Wet passivation cleaning

[0156] As shown in Figure 3g , a wet passivation process is used to remove all the graded doping structures 14 and the tunneling layer 13 on the non-grid line region S22, and at the same time remove the edge PSG and repair the damage caused to the second surface during the laser etching process.

[0157] This step specifically includes:

[0158] Pickling: An acid solution is used to remove the PSG and oxide layer on the surface;

[0159] Alkali etching: An alkali solution is used to remove all the graded doping structures 14 on the non-grid line region S22, and at the same time remove the front and edge plating;

[0160] Pickling: An acid solution is used to remove the tunneling layer 13 on the non-grid line region S22;

[0161] Finally, hydrochloric acid is used for cleaning to remove metal ions, and then it is washed with water and dried.

[0162] Preferably, the acid solution in this embodiment is obtained by mixing an industrial-grade hydrofluoric acid solution (mass fraction ~40%) and water in a certain ratio, and the alkali solution is obtained by mixing an industrial-grade sodium hydroxide solution (mass fraction ~32%) and water in a certain ratio.

[0163] 8. Preparation of the passivation layer

[0164] Refer Figure 3h As shown, the first passivation layer 21 and the second passivation layer 22 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 by using the ALD process. Both the first passivation layer 21 and the second passivation layer 22 are alumina passivation layers.

[0165] After the steps of de-wrapping plating and wet chemical etching, there is no passivation layer protection on the second surface. Therefore, while preparing the first passivation layer on the front (first surface), it is necessary to simultaneously prepare the second passivation layer on the back (second surface).

[0166] 9. Preparation of the antireflection layer

[0167] Refer Figure 3i As shown, the first antireflection layer 31 and the second antireflection layer 32 are respectively prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 by using the PECVD process. The first antireflection layer 31 and the second antireflection layer 32 can be a stacked film formed by any one or more of silicon nitride layer, silicon oxynitride layer, and silicon oxide layer.

[0168] 10. Printing of metal electrodes

[0169] Refer Figure 3j As shown, the first electrode 41 and the second electrode 42 are respectively printed on the front and the back by screen printing process, and then sintering and optical injection or electrical injection treatment are carried out to form an ohmic contact.

[0170] The first electrode 41 and the second electrode 42 are grid line electrodes in the prior art, usually including main grid lines and fine grid lines.

[0171] Through the above steps, the TOPCon solar cell can be prepared, and finally the solar cell is tested, sorted, and stored in the warehouse.

[0172] Example 3

[0173] The difference between this embodiment and Example 2 is only that in this embodiment, the oxide layer, the graded doping structure on the non-grid line region S22, and the oxide layer on the grid line region S21 are removed by using the wet chemical etching process, and the P atoms in the graded doping structure in the groove 12 on the grid line region S21 are excited by using the high-temperature annealing process to crystallize the graded doping structure in the groove.

[0174] The specific preparation steps are as follows:

[0175] 1. Double-sided pile fabrication

[0176] A silicon substrate 10 is provided, comprising a first surface S1 and a second surface S2 disposed opposite to each other. The second surface S2 includes a gate line region S21 and a non-gate line region S22. The first surface S1 is the front side (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlighting surface) of the silicon substrate 10. The gate line region S21 is a back metal region, and the non-gate line region S22 is a back non-metal region. The silicon substrate 10 is treated in a texturing chemical bath to form a pyramidal textured structure on the first surface S1 and the second surface S2 of the silicon substrate 10 through an alkaline texturing process.

[0177] 2. Boron diffusion

[0178] A P-type doped first doped layer (i.e., P+ emitter) 11 is formed on the first surface S1 of the silicon substrate 10 by a boron diffusion process. Specifically, the diffusion is carried out in a high-temperature furnace tube using a boron source deposition-propellant method. After diffusion, the doping concentration of the first doped layer 11 is 1E19cm⁻¹. -3 -9E19cm -3 In the boron diffusion process, BSG is also formed on the second surface S2 of the silicon substrate.

[0179] 3. Grooving

[0180] On the gate line region S21 of the second surface S2 of the silicon substrate 10, a single-sided patterning process is performed using a laser to form several parallel and equally spaced grooves 12. The laser power is 30W-70W, and the laser pulse width is 3ns-50ns. The etching depth of the formed grooves 12 is 0.2μm-5μm, preferably 0.2μm-20μm; the etching width is 20μm-100μm, preferably 20μm-50μm. The mask pattern used for grooving must be consistent with the screen-printed mask pattern used for the subsequent fabrication of the second electrode.

[0181] In this embodiment, the grid line region S21 includes multiple parallel and equally spaced first sub-regions, and the non-grid line region S22 includes multiple parallel and equally spaced second sub-regions, with the first and second sub-regions interleaved, and a groove 12 is formed in each first sub-region.

[0182] 4. Backside polishing

[0183] The grooved silicon substrate 10 undergoes wet cleaning to remove the textured surface structure (textured surface structure on non-gateline areas and textured surface structure on gateline areas) caused by patterning, and to repair damage caused by laser grooving. Specifically, the grooved silicon substrate 10 is first passed through a single-sided chain device to remove silicon oxide on the second surface using hydrofluoric acid solution, then the second surface is subjected to alkaline polishing to remove edge junctions and backside girders (BSG), and finally cleaned.

[0184] 5. Preparation of back-side tunneling passivation structure

[0185] A tunneling layer 13, a gradient doped structure 14, and an oxide layer 15 are sequentially stacked on the second surface S2.

[0186] For example, in this embodiment, a silicon oxide tunneling layer is first deposited on the second surface using the PECVD process, wherein the introduced N2O flow rate is 8000sccm-15000sccm, the power is 8000W-15000W, and the deposition time is 80s-150s.

[0187] Then, multiple phosphorus-doped amorphous silicon layers (doped layers) with different doping concentrations are deposited stepwise. Specifically, multiple intrinsic layers (undoped amorphous silicon layers) are first formed, and after each intrinsic layer is formed, it is subjected to phosphorus doping to form a phosphorus-doped amorphous silicon layer (doped layer). The total thickness of the phosphorus-doped amorphous silicon layer (doped layer) is 80nm-120nm, and the thickness of each phosphorus-doped amorphous silicon layer increases from the direction away from the tunneling layer 13. The doping concentration of the multiple phosphorus-doped amorphous silicon layers with different doping concentrations gradually increases from the direction away from the silicon oxide tunneling layer. The phosphorus-doped amorphous silicon layer closest to the silicon oxide tunneling layer has the lowest phosphorus content, with a doping concentration ranging from 5E18cm. -3 -5E19cm -3 The phosphorus atom content is highest in the phosphorus-doped amorphous silicon layer furthest from the silicon oxide tunneling layer, with a doping concentration ranging from 5E to 20cm⁻¹. -3 -5E21cm -3 The multilayer phosphorus-doped amorphous silicon can consist of two or more layers with varying doping concentrations. The doping source—the phosphorus source—can be PH3 or POCl3. The oxide layer can be SiO2. X SiO X N Y Or SiN X .

[0188] 6. Wet chemical etching followed by high-temperature annealing

[0189] A wet chemical etching process is used to process the oxide layer 15 and the gradient doped structure 14 on the non-gate region S22 and the oxide layer 15 on the gate region S21, removing the oxide layer 15 and part of the gradient doped structure 14 on the non-gate region S22, and removing the oxide layer 15 on the gate region S21. Then, a high-temperature annealing process is used to excite the P atoms in the gradient doped structure 14 in the groove 12 on the gate region S21, crystallizing the gradient doped structure 14 in the groove 12.

[0190] In this embodiment, the gradient doped structure 14 before the high-temperature annealing process includes multiple phosphorus-doped amorphous silicon layers. The high-temperature annealing process can crystallize and activate the phosphorus-doped amorphous silicon layers in the groove 12, transforming the phosphorus-doped amorphous silicon layers into phosphorus-doped polycrystalline silicon layers.

[0191] Specifically, the wet chemical etching process is as follows: first, HF is used to etch the oxide layer on the surface, and then KOH or NaOH is used to clean the gradient doped structure. The high-temperature annealing process is as follows: the high-temperature annealing temperature is 880℃-920℃, and the annealing time is 110min-130min, preferably 120min. After the high-temperature annealing process, the phosphorus atom doping concentration in the phosphorus-doped polysilicon layer closest to the tunneling layer 13 is 5E18cm⁻¹. -3 -5E19cm -3 The phosphorus doping concentration in the phosphorus-doped polysilicon layer furthest from tunnel layer 13 is 5E20cm⁻¹. -3 -5E21cm -3 .

[0192] 7. Wet passivation cleaning

[0193] A wet passivation process is used to remove all gradient doped structures 14 and tunneling layers 13 on the non-gate region S22, while removing edge PSG and repairing damage to the second surface caused during laser etching.

[0194] This step specifically includes:

[0195] Pickling: Using an acid solution to remove the PSG and oxide layer from the surface;

[0196] Alkaline etching: Alkaline solution is used to remove all gradient doped structures 14 on the non-gate line region S22, while removing the front and edge plating.

[0197] Pickling: The tunneling layer 13 on the non-gate line region S22 is removed using an acid solution;

[0198] Finally, hydrochloric acid was used to remove metal ions, followed by washing with water and drying.

[0199] Preferably, in this embodiment, the acid solution is obtained by mixing industrial-grade hydrofluoric acid solution (mass fraction ~40%) with water in a certain proportion, and the alkali solution is obtained by mixing industrial-grade sodium hydroxide solution (mass fraction ~32%) with water in a certain proportion.

[0200] 8. Passivation layer preparation

[0201] A first passivation layer 21 and a second passivation layer 22 are prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 using the ALD process. Both the first passivation layer 21 and the second passivation layer 22 are aluminum oxide passivation layers.

[0202] After the de-coating and wet chemical etching steps, there is no passivation layer protection on the second surface. Therefore, while preparing the first passivation layer on the front side (first surface), a second passivation layer needs to be prepared on the back side (second surface) at the same time.

[0203] 9. Preparation of antireflection layer

[0204] A first antireflection layer 31 and a second antireflection layer 32 are prepared on the first surface S1 and the second surface S2 of the silicon substrate 10 using a PECVD process. The first antireflection layer 31 and the second antireflection layer 32 can be stacked films formed by any one or more of silicon nitride layers, silicon oxynitride layers, and silicon oxide layers.

[0205] 10. Printed metal electrodes

[0206] The first electrode 41 and the second electrode 42 are printed on the front and back sides respectively by screen printing, and then sintering and photo-injection or electro-injection are performed to form an ohmic contact.

[0207] The first electrode 41 and the second electrode 42 are gate line electrodes in the prior art, which typically include main gate lines and fine gate lines.

[0208] The TOPCon solar cells can be prepared by following the above steps. Finally, the solar cells are tested, sorted, and stored.

[0209] This application also provides a solar cell prepared by the above-described method for preparing a solar cell.

[0210] refer to Figure 3j and Figure 4As shown, the solar cell in this embodiment is a TOPcon cell, including a silicon substrate 10. The silicon substrate 10 includes a first surface S1 and a second surface S2 disposed opposite to each other. The second surface S2 includes a grid line region S21 and a non-grid line region S22. The first surface S1 is the front side (i.e., the light-receiving surface) of the silicon substrate 10, and the second surface S2 is the back side (i.e., the backlighting surface) of the silicon substrate 10. The grid line region S21 is a metal region on the back side, and the non-grid line region S22 is a non-metallic region on the back side. The silicon substrate 10 in this embodiment is an N-type silicon substrate.

[0211] Furthermore, a light-trapping structure is formed on the first surface S1 of the silicon substrate 10, such as a pyramidal textured structure that can be formed on the first surface S1 of the silicon substrate 10 by alkaline texturing.

[0212] In this embodiment, a first doped layer 11 (i.e., emitter) is formed on the first surface S1 of the silicon substrate 10 by a diffusion process or a PECVD process. For example, the first doped layer 11 is a P-type doped layer (i.e., P+ emitter) formed by a boron doping process, with a doping concentration of 1E19cm⁻¹. -3 -9E19cm -3 .

[0213] In this embodiment, a plurality of grooves 12 are formed on the gate line region S21 of the second surface S2 of the silicon substrate 10. Specifically, the gate line region S21 includes a plurality of parallel and equally spaced first sub-regions, and the non-gate line region S22 includes a plurality of parallel and equally spaced second sub-regions, and the first sub-regions and second sub-regions are staggered. The plurality of grooves 12 are distributed parallel and equally spaced on the plurality of first sub-regions, and each first sub-region corresponds to one groove 12.

[0214] Each groove 12 has a depth of 0.2μm-5μm, preferably 0.2μm-20μm, and a width of 20μm-100μm, preferably 20μm-50μm. A tunneling layer 13 and a gradient-doped structure 14 are sequentially stacked within each groove 12. The sum of the thicknesses of the gradient-doped structure 14 and the tunneling layer 13 is less than the depth of the groove 12, allowing the subsequent second electrode 42 to be formed within the groove 12. This increases the contact area between the second electrode 42 and the gradient-doped structure 14, reducing the contact resistance.

[0215] The tunneling layer 13 is one or a combination of two of the following: a silicon oxide layer and a silicon oxynitride layer, preferably a silicon oxide layer.

[0216] The gradient doping structure 14 includes multiple doped layers with a total thickness of 80 nm to 120 nm, and the thickness of each doped layer increases from the direction away from the tunneling layer 13.

[0217] For example, taking a two-layer doped layer as an example, such as Figure 3j and Figure 4 As shown, from the outermost layer (the second doped layer) to the innermost layer (the third doped layer close to the tunneling layer 13), the thicknesses of the doped layers decrease successively, and the thickness ranges are 15 nm - 25 nm and 5 nm - 15 nm respectively. Both doped layers are phosphorus-doped polysilicon layers, and the doping concentrations of the two doped layers increase in the direction away from the tunneling layer 13. Among them, the doping concentration of phosphorus atoms in the doped layer (the third doped layer) closest to the tunneling layer 13 is 5E18 cm -3 -5E19 cm -3 , and the doping concentration of phosphorus atoms in the doped layer (the second doped layer) farthest from the tunneling layer 13 is 5E20 cm -3 -5E21 cm -3 .

[0218] Preferably, in this embodiment, a first passivation layer 21 and a first antireflection layer 31 are successively stacked on the first surface S1 of the silicon substrate 10, and a second passivation layer 22 and a second antireflection layer 32 are successively stacked on the second surface S2 of the silicon substrate 10. The second passivation layer 22 and the second antireflection layer 32 cover the graded doping structure 14 and extend into the gate line region S21. Exemplarily, both the first passivation layer 21 and the second passivation layer 22 are alumina passivation layers; the first antireflection layer 31 and the second antireflection layer 32 can be a stacked film formed by any one or more of a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer.

[0219] In addition, in this embodiment, the first electrode 41 is located on the first surface S1 of the silicon substrate 10 and contacts the first doped layer 11. The width of the second electrode 42 is smaller than the width of the groove 12, and it is located in the groove 12 on the second surface S2 of the silicon substrate 10 and contacts the graded doping structure 14. Specifically, the bottom surface and the side surface adjacent to the bottom surface of the second electrode 42 located in the groove 12 are both in contact with the graded doping structure 14 in the groove 12. The second electrode 42 is a gate line electrode.

[0220] Embodiment 4:

[0221] Refer Figure 5 and in combination with Figure 6 As shown, the solar cell in this embodiment is substantially the same as that in Embodiment 3, except that the graded doping structure 14 in this embodiment includes three doped layers. From the outermost layer (the second doped layer) to the innermost layer (the third doped layer close to the tunneling layer 13), the thicknesses of the doped layers decrease successively, and the thickness ranges are 25 nm - 35 nm, 15 nm - 25 nm, and 5 nm - 15 nm respectively. All three doped layers are phosphorus-doped polysilicon layers, and the doping concentrations of the three doped layers increase in the direction away from the tunneling layer 13. Among them, the doping concentration of phosphorus atoms in the doped layer (the third doped layer) closest to the tunneling layer 13 is 5E18 cm -3 -5E19 cm -3The phosphorus doping concentration in the doped layer furthest from tunnel layer 13 (the second doped layer) is 5E20cm⁻¹. -3 -5E21cm -3 The phosphorus doping concentration in the fourth doped layer, located between the third and second doped layers, is between that of the third and second doped layers.

[0222] Compared with the prior art, the solar cell preparation method and solar cell of the present invention, by setting a groove and setting a gradient doping structure inside the groove, and printing the second electrode inside the groove, increases the contact area, reduces the contact resistance, and reduces the current loss caused by parasitic absorption.

[0223] The present invention discloses a method for preparing solar cells and a solar cell in which the distribution of doping sources in the gradient doping structure can be accurately controlled by setting up a multilayer doping layer with gradually varying doping concentration, thereby improving the efficiency of TOPcon solar cells.

[0224] The present invention discloses a method for fabricating a solar cell and a solar cell that, through differentiated treatment of the gradient doping structure on the second surface of the silicon substrate in the grid line region and the non-grid line region, completely removes the gradient doping structure in the non-grid line region, effectively reducing the parasitic absorption effect of the gradient doping structure in the non-grid line region and improving the bifaciality of the solar cell.

[0225] The present invention discloses a method for preparing solar cells and a solar cell that uses laser annealing to replace the traditional high-temperature annealing process, thereby avoiding the energy consumption reduction caused by high-temperature annealing, greatly reducing the process time, and improving the preparation efficiency.

[0226] The method for preparing the solar cell and the solar cell of this invention can increase optical absorption and improve the efficiency of the solar cell.

[0227] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0228] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar cell, characterized by, The solar cell comprises: a silicon substrate comprising a first surface and a second surface oppositely arranged, the first surface being provided with light-trapping structures, and the second surface being provided with a groove in a gate line area; a first doped layer on the first surface; a tunneling layer in the groove; a graded doped structure stacked on the tunneling layer, the graded doped structure comprising at least two doped layers, the doped layers having different doping concentrations and gradually changing from one layer to another; a first electrode on the first surface and in contact with the first doped layer; a second electrode in contact with the graded doped structure in the groove.

2. The solar cell according to claim 1, characterized in that, The graded doped structure comprises a third doped layer arranged close to the tunneling layer and a second doped layer arranged away from the tunneling layer, the third doped layer having a doping concentration smaller than that of the second doped layer.

3. The solar cell according to claim 2, characterized in that, The graded doped structure comprises at least one fourth doped layer arranged between the second doped layer and the third doped layer, the fourth doped layer having a doping concentration smaller than that of the second doped layer and larger than that of the third doped layer.

4. The solar cell of claim 1, wherein The tunneling layer is arranged on a bottom wall and a sidewall of the groove.

5. The solar cell of claim 1, wherein The groove has a depth of 0.2-5 μm and a width of 20-100 μm.

6. The solar cell according to claim 5, characterized in that, The second electrode has a width smaller than that of the groove; and / or, The sum of the thicknesses of the graded doped structure and the tunneling layer is smaller than the depth of the groove.

7. The solar cell of claim 2, wherein The graded doped structure has a thickness of 80-120 nm, and the thicknesses of the doped layers in the graded doped structure increase from the direction away from the tunneling layer; and / or, The third doped layer has a doping concentration ranging from 5E18 cm -3 -5E19 cm -3 The second doped layer has a doping concentration ranging from 5E20 cm -3 -5E21 cm -3 .

8. The solar cell of claim 1, wherein, The first doped layer has a doping concentration of 1E19 cm -3 -9E19cm -3 .

9. The solar cell of claim 1, wherein, The solar cell further comprises: a first passivation layer formed on a surface of the first doped layer facing away from the silicon substrate; a first anti-reflection layer formed on a surface of the first passivation layer facing away from the the first doped layer; a second passivation layer formed on the second surface; and a second anti-reflection layer formed on the second passivation layer.

10. The solar cell of claim 9, wherein, The first passivation layer comprises one or more of an aluminum oxide layer, a gallium oxide layer; and / or, The second passivation layer comprises one or more of an aluminum oxide layer, a gallium oxide layer; and / or, The first anti-reflection layer comprises one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer; and / or, The second anti-reflection layer comprises one or more of a silicon nitride layer, a silicon oxynitride layer.

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