Doppler radar for improving signal distortion
By improving the ADC circuit structure of Doppler radar and utilizing a combination of resistor voltage divider, voltage comparator, clock chip and correction unit, the jitter signal distortion problem in the Doppler radar signal conversion process was solved, and efficient signal processing was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-16
- Publication Date
- 2026-03-06
AI Technical Summary
Traditional Doppler radar generates jitter signals during analog-to-digital conversion, leading to signal distortion, and phase detection methods are difficult to implement.
The ADC circuit employs a resistor divider unit, voltage comparator unit, clock chip, sample-and-hold circuit, and correction unit. By using a synchronous switch and loss prediction model, jitter signals are pre-reduced, avoiding the use of registers to eliminate logic errors and ensuring that the conversion is completed under the same timing.
It improves signal processing efficiency, reduces signal distortion, and lowers the difficulty of implementation.
Smart Images
Figure CN223977346U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of Doppler radar signal processing technology, and in particular to a Doppler radar that improves signal distortion. Background Technology
[0002] Traditional Doppler radar generates jitter signals during analog-to-digital conversion, which can easily cause signal distortion. Traditional jitter signal processing methods use timing design and phase detection to eliminate radar pulse signal jitter in real time during sampling. However, phase detection in Doppler radar's ADC conversion process requires real-time monitoring of time-shifted phase differences, which is relatively difficult to implement. Utility Model Content
[0003] In view of this, the main objective of this utility model is to provide a Doppler radar that improves signal distortion.
[0004] The technical solution adopted in this utility model is as follows:
[0005] Improvements to Doppler radar that reduce signal distortion include:
[0006] At least one antenna of at least one radio frequency circuit,
[0007] The radio frequency circuit is configured to receive and down-convert the received radar signals;
[0008] The radio frequency circuit includes an ADC circuit and a correction unit. The ADC circuit receives and down-converts the received radar signal and converts the radar signal into a digital signal.
[0009] The ADC circuit includes:
[0010] The resistor voltage divider unit consists of several resistor voltage dividers connected in parallel. These resistor voltage dividers are used to quantize the input reference voltage threshold into multiple corresponding reference comparison voltages.
[0011] The voltage comparator unit consists of several voltage comparators. One end of each voltage comparator is connected to the same capacitor, and the other end is connected together as the input terminal of the sample-and-hold analog voltage.
[0012] The clock chip is coupled to several voltage comparators to provide reference timing for the voltage comparators;
[0013] A sample-and-hold circuit, coupled to the input of the sample-and-hold analog voltage, is used to sample the analog input signal separately to obtain several sample signals. The sample signals are compared with the reference comparison voltage formed by the resistor voltage divider unit. After the comparison, the signals are input to the encoder according to the same reference timing. The encoder then generates a binary digital signal.
[0014] The correction unit is coupled to the ADC circuit and is used to correct the jitter signal during the conversion process of the signal in the ADC circuit according to the loss prediction model, so as to correct the binary digital signal formed by the encoder.
[0015] Furthermore, several parallel resistor dividers quantize the input reference voltage threshold into multiple corresponding, successively increasing reference comparison voltages according to a set rule.
[0016] Furthermore, the setting rule is to quantify the reference comparison voltage by successively increasing the set reference voltage threshold according to the rated coefficient.
[0017] Furthermore, the voltage divider includes a voltage divider resistor R1 and a voltage divider resistor R2.
[0018] Furthermore, based on the parallel configuration of several parallel resistor voltage dividers, the total resistance value of the voltage dividing resistors R1 and R2 contained in each resistor voltage divider remains unchanged, and according to the parallel configuration, the voltage dividing resistors R1 and R2 change accordingly with the same resistance value.
[0019] Furthermore, the output terminal of the capacitor is coupled to a synchronous switch, the synchronous switch is coupled to a clock chip, and the comparison result obtained by comparing the sampled signal with the reference comparison voltage is output to the encoder via the synchronous switch.
[0020] Furthermore, the correction unit is equipped with a loss prediction model, which is located in the encoder. The loss prediction model pre-subtracts the binary digital signal generated by the encoder according to the set value given by the loss prediction model before outputting it.
[0021] This application employs pre-reduction of the jitter signal generated during the ADC conversion process of Doppler radar to achieve the purpose of signal distortion processing.
[0022] Unlike traditional ADC circuits, this application does not use registers to eliminate logic errors caused by the different processing speeds of multiple voltage comparators. Instead, it uses a synchronous switch based on a synchronous reference clock to compare the output results. On the one hand, this improves signal processing efficiency by not using registers, and on the other hand, it ensures that the entire ADC conversion process is completed under the same timing by using the reference timing. Attached Figure Description
[0023] The following figures are for illustrative purposes only and are not intended to limit the scope of the present invention.
[0024] Figure 1 This is a general schematic diagram of the framework of this utility model;
[0025] Figure 2 This is a schematic diagram of the parallel comparison ADC circuit in this invention. Detailed Implementation
[0026] To make the objectives, technical solutions, design methods, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this utility model.
[0027] Reference Figures 1 to 2 This utility model provides a Doppler radar with improved signal distortion, comprising:
[0028] At least one antenna of at least one radio frequency circuit,
[0029] The radio frequency circuit is configured to receive and down-convert the received radar signals;
[0030] The radio frequency circuit includes an ADC circuit and a correction unit. The ADC circuit receives and down-converts the received radar signal and converts the radar signal into a digital signal.
[0031] The ADC circuit includes:
[0032] The resistor voltage divider unit consists of several resistor voltage dividers connected in parallel. These resistor voltage dividers are used to quantize the input reference voltage threshold into multiple corresponding reference comparison voltages.
[0033] The voltage comparator unit consists of several voltage comparators. One end of each voltage comparator is connected to the same capacitor, and the other end is connected together as the input terminal of the sample-and-hold analog voltage.
[0034] The clock chip is coupled to several voltage comparators to provide reference timing for the voltage comparators;
[0035] A sample-and-hold circuit, coupled to the input of the sample-and-hold analog voltage, is used to sample the analog input signal separately to obtain several sample signals. The sample signals are compared with the reference comparison voltage formed by the resistor voltage divider unit. After the comparison, the signals are input to the encoder according to the same reference timing. The encoder then generates a binary digital signal.
[0036] The correction unit is coupled to the ADC circuit and is used to correct the jitter signal during the conversion process of the signal in the ADC circuit according to the loss prediction model, so as to correct the binary digital signal formed by the encoder.
[0037] In the above, several parallel resistor dividers quantize the input reference voltage threshold into multiple corresponding successively increasing reference comparison voltages according to a set rule.
[0038] In the above, the setting rule is to quantify the reference comparison voltage by successively increasing the set reference voltage threshold according to the rated coefficient.
[0039] In the above, the voltage divider includes voltage divider resistor R1 and voltage divider resistor R2.
[0040] In the above, according to the parallel configuration of several parallel voltage dividers, the total resistance of the voltage divider resistors R1 and R2 contained in each voltage divider remains unchanged, and according to the parallel configuration, the voltage divider resistors R1 and R2 change accordingly with the same resistance value.
[0041] In this application, the resistive voltage divider is used to quantize the input reference voltage threshold into five comparison reference voltages, U1-U5. The specific values of U1-U5 are U1=1Uf / 12, U2=3Uf / 12, U3=5Uf / 12, U4=7Uf / 12, and U5=9Uf / 12, respectively, where Uf is the input reference voltage.
[0042] In this application, the reference voltage threshold setting method is: R2 / (R1+R2). Assuming R1+R2 is 12Ω, based on the parallel connection of several parallel resistor voltage dividers, when setting U1, R1 is set to 11Ω and R2 is set to 1Ω; when setting U2, R1 is set to 9Ω and R2 is set to 2Ω; when setting U3, R1 is set to 7Ω and R2 is set to 5Ω; when setting U4, R1 is set to 5Ω and R2 is set to 7Ω; when setting U5, R1 is set to 3Ω and R2 is set to 9Ω.
[0043] In the above, the output terminal of the capacitor is coupled to the synchronous switch S, the synchronous switch is coupled to the clock chip, and the comparison result obtained by comparing the sampled signal with the reference comparison voltage is output to the encoder via the synchronous switch.
[0044] In the above, the loss prediction model can be trained based on historical data. This historical data can be obtained by acquiring key data from the jitter process, including pulse repetition frequency, simulation time, sampling rate, amplitude, and pulse width.
[0045] In the above, the correction unit is equipped with a loss prediction model, which is located in the encoder. The binary digital signal generated by the encoder is pre-subtracted according to the set value given by the loss prediction model before being output. Jitter is the deviation between the ideal edge and the actual edge of a signal. The sampling clock is the reference for signal communication. The deviation of the actual signal from the ideal situation includes amplitude offset. Jitter is a horizontal error that only exists at the moment of signal edge transition. The signal travels through a long transmission channel between the transmitting and receiving ends. Due to various factors such as crosstalk, scattering effects, impedance mismatch, or signal jitter caused by magic transformation, the signal will not maintain its original characteristics upon reaching the receiving end. Therefore, this application employs pre-subtraction of the jitter signal generated during the ADC conversion process of Doppler radar to achieve the purpose of signal distortion processing.
[0046] Unlike traditional ADC circuits, this application does not use registers to eliminate logic errors caused by the different processing speeds of multiple voltage comparators. Instead, it uses a synchronous switch based on a synchronous reference clock to compare the output results. On the one hand, this improves signal processing efficiency by not using registers, and on the other hand, it ensures that the entire ADC conversion process is completed under the same timing by using the reference timing.
[0047] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.
Claims
1. Doppler radar for improving signal distortion, characterized in that The application relates to an ADC circuit and a correction unit. The ADC circuit comprises: a resistor voltage division unit composed of a plurality of parallel resistor voltage dividers, which quantize an input reference voltage threshold into a plurality of corresponding reference comparison voltages; a voltage comparison unit composed of a plurality of voltage comparators, one end of the plurality of voltage comparators being connected to the same capacitor and the other end being connected together as an input end of a sample-and-hold analog voltage; a clock chip coupled to the plurality of voltage comparators and providing reference timing for the voltage comparators; a sample-and-hold circuit coupled to the input end of the sample-and-hold analog voltage, which samples an analog input signal to obtain a plurality of sample signals, compares the sample signals with the reference comparison voltages formed by the resistor voltage division unit, and inputs the comparison results to an encoder according to the same reference timing; and the correction unit is coupled to the ADC circuit and corrects a jitter signal in the conversion process of the ADC circuit according to a loss estimation model to correct the binary digital signal formed by the encoder. The plurality of parallel resistor voltage dividers quantize the input reference voltage threshold into a plurality of corresponding reference comparison voltages according to a set rule. The set rule is to quantize the reference comparison voltages by increasing the set reference voltage threshold by a rated coefficient. The resistor voltage divider comprises a voltage division resistor R1 and a voltage division resistor R2.
2. The Doppler radar of claim 1, wherein, The resistor values of the voltage division resistor R1 and the voltage division resistor R2 in each resistor voltage divider remain unchanged according to the parallel form of the plurality of parallel resistor voltage dividers, and the voltage division resistor R1 and the voltage division resistor R2 change according to the same resistance value according to the parallel form.
3. The Doppler radar of claim 2 to improve signal distortion, characterized by, The output end of the capacitor is coupled to a synchronous switch, the synchronous switch is coupled to the clock chip, and the comparison results of the sample signals and the reference comparison voltages are output to the encoder through the synchronous switch.
4. The Doppler radar of claim 2 to improve signal distortion, characterized by, The correction unit is provided with a loss estimation model, the loss estimation model is located in the encoder, and the binary digital signal formed by the encoder is pre-subtracted according to the set value given by the loss estimation model and then output.
5. The Doppler radar of claim 4, wherein, 6. The Doppler radar of claim 1, wherein, 7. The Doppler radar of claim 1, wherein,