Structure for preventing PIN of TP power supply based on plug-in and ONCELL

Abstract

The utility model discloses a structure for preventing a TP power supply PIN based on plug-in and ONCELL, comprising a display FPC substrate and a TP interface definition, the TP interface definition is welded on the display FPC substrate, the TP interface definition comprises an IOCC pin, a VCC pin and a GND pin, at least one NC pin is arranged between the IOCC pin and the VCC pin, and the GND pin is welded on the display FPC substrate. And at least one NC second pin is arranged between the IOCC pin or the VCC pin and the GND first pin. According to the utility model, the production yield of products can be improved, the cost is low, and the implementation is simple.

Description

Technical Field

[0001] This utility model belongs to the field of touch screen display module technology, specifically relating to a structure based on external and ONCELL to prevent TP power pins. Background Technology

[0002] In the existing FPC interface design of touch screen display modules, the following defects exist when the power pin (VCC / IOVCC) and the ground pin (GND) are arranged adjacently:

[0003] 1. When the power supply pin and GND are adjacent pins, a short circuit during soldering can easily burn the IC;

[0004] 2. When the power supply PIN (VCC) and the power supply PIN (IOVCC) are adjacent PINs, a short circuit during soldering can easily lead to unstable product testing. Utility Model Content

[0005] The purpose of this invention is to provide a structure based on external mounting and ONCELL to prevent TP power pins, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution: a structure based on external mounting and ONCELL to prevent TP power pins, including a display FPC substrate and a TP interface definition, wherein the TP interface definition is soldered on the display FPC substrate, and the TP interface definition includes an IOCC pin, a VCC pin, and a GND pin, wherein at least one NC pin is provided between the IOCC pin and the VCC pin, and at least one NC pin is provided between the IOCC pin or the VCC pin and the GND pin.

[0007] Preferably, the TP interface definition also includes at least one GND pin.

[0008] The technical effects and advantages of this utility model are as follows:

[0009] 1. By separating VCC and IOVCC using NC, this design avoids the situation where VCC and IOVCC are short-circuited during soldering, and IOVCC is also open-circuited, making it impossible to test correctly.

[0010] 2. Several more GND pins have been added. This design prevents the GND pin from being undetectable during testing if it is slightly open, which would affect the product's functionality. In addition, the addition of two GND pins greatly improves the production soldering yield.

[0011] 3. This design does not change the client interface definition, resulting in low implementation costs.

[0012] 4. By separating the power PIN and GND with NC, short circuits during soldering can easily burn out the IC. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the present invention.

[0014] In the diagram: 1 IOCC, 2 NC-1, 3 VCC, 4 NC-2, 5 GND-1, 6 GND-2. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0016] This utility model provides, for example Figure 1 The diagram illustrates a structure based on external mounting and ONCELL to prevent TP power pin damage. It includes a display FPC substrate and a TP interface definition. The TP interface definition is soldered onto the display FPC substrate. The TP interface definition includes an IOCC1 pin, a VCC3 pin, and a GND-5 pin. At least one NC-2 pin is provided between the IOCC1 pin and the VCC3 pin, separated by NC-2. This design avoids the situation where VCC and IOCC are short-circuited during soldering, and IOCC is also open-circuited, making proper testing impossible. At least one NC-4 pin is provided between the IOCC1 pin or the VCC3 pin and the GND-5 pin, separated by NC-4, to prevent short circuits from easily burning out the IC.

[0017] Specifically, the TP interface definition also includes at least one GND pin 6, which adds several GND pins. This design prevents the GND pin from being undetectable during micro-open circuit testing.

[0018] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A structure for preventing TP power supply PIN based on external hanging and ONCELL, comprising a display FPC substrate, TP interface definition, characterized in that: The TP interface definition is welded on the display FPC substrate, and the TP interface definition comprises an IOCC (1) pin, a VCC (3) pin and a GND one (5) pin, at least one NC one (2) pin is arranged between the IOCC (1) pin and the VCC (3) pin, and at least one NC two (4) pin is arranged between the IOCC (1) pin or the VCC (3) pin and the GND one (5) pin.

2. The structure for preventing TP power supply PIN based on external hanging and ONCELL according to claim 1, characterized in that: The TP interface definition further comprises at least one GND two (6) pin.

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