Server mainboard based on CPLD (Complex Programmable Logic Device) and server

Abstract

The utility model provides a CPLD (Complex Programmable Logic Device)-based server mainboard and a server, which relate to the technical field of computers and comprise a processor, a BIOS (Basic Input Output System) chip, a CPLD module and a BMC (Baseboard Management The CPLD module is connected with the processor through a first SPI interface, a first LPC interface and a first UART interface; the CPLD module is connected with the BMC module through a second SPI interface, a second LPC interface and a second UART interface; and the CPLD module is connected with the BIOS chip through a third SPI (Serial Peripheral Interface). The server mainboard based on the CPLD is high in integration level, the fault response time of the mainboard is shortened, the maintenance workload of a domestic server is reduced, and the reliability and safety of the domestic server are improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to computer technology field especially is based on CPLD's server mainboard and server. BACKGROUND

[0002] Under the background of the rapid development of information technology, as the core equipment of information processing and storage, servers are increasingly widely used in various industries.

[0003] In the traditional server design, a large number of ICs (integrated circuits) are usually used to realize various functional modules, which ensures the stability and functionality of the system, but due to the complex connection between IC chips and the long signal transmission path, it may affect the overall performance of the system. SUMMARY

[0004] The utility model discloses a kind of server mainboard and server based on CPLD, high integration, reduce mainboard fault response time, reduce the maintenance workload of domestic server, improve the reliability and security of domestic server.

[0005] In the first aspect, the utility model provides a kind of server mainboard based on CPLD, including processor, BIOS chip, CPLD module and BMC module;The CPLD module is connected with the processor by first SPI interface, first LPC interface and first UART interface;The CPLD module is connected with the BMC module by second SPI interface, second LPC interface and second UART interface;The CPLD module is connected with the BIOS chip by third SPI interface.

[0006] In optional implementation, the number of BIOS chips is multiple, and each BIOS chip is connected to the CPLD module in parallel through the third SPI interface.

[0007] In optional implementation, the CPLD module is also connected with the BMC module through first GPIO interface, the first GPIO interface is used to transmit at least one enable signal sent by the BMC module, and the enable signal is used to control each BIOS chip.

[0008] In optional implementation, the CPLD module uses Anlogic CPLD EF2L25BG256B chip.

[0009] In optional implementation, the CPLD module is also connected with test equipment through second GPIO interface, to obtain power-on fault information transmitted by the processor and the BMC module through the test equipment.

[0010] In an optional implementation, the CPLD module is used to receive the BIOS chip's operational fault information through the third SPI interface, and send the operational fault information to the BMC module through the second SPI interface.

[0011] In an optional implementation, the BMC module includes a BMC chip and a display module. The BMC chip is connected to the CPLD module through a second SPI interface, a second LPC interface, and a second UART interface, and is connected to the display module through a third GPIO interface.

[0012] In an optional implementation, the display module is used to display the operational fault information.

[0013] In an optional implementation, a printed circuit board is also included, on which the processor, the BIOS chip, the CPLD module, and the BMC module are integrated.

[0014] Secondly, this utility model provides a CPLD-based server, including the CPLD-based server motherboard described in any of the foregoing embodiments.

[0015] The present invention provides the following beneficial effects:

[0016] This invention provides a CPLD-based server motherboard, which includes a processor, a BIOS chip, a CPLD module, and a BMC module. By using the CPLD module to replace a large number of ICs (integrated circuits), the integration is high, reducing the motherboard failure response time, reducing the maintenance workload of domestic servers, and improving the reliability and security of domestic servers.

[0017] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0018] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A structural diagram of a CPLD-based server motherboard provided for an embodiment of this utility model;

[0021] Figure 2 A structural diagram of another CPLD-based server motherboard provided for an embodiment of this utility model;

[0022] Figure 3 This is a structural diagram of a CPLD-based server provided for an embodiment of the present invention.

[0023] icon:

[0024] 101 - Processor; 102 - BIOS chip; 103 - CPLD module; 104 - BMC module; 1041 - BMC chip; 1042 - Display module; 10 - CPLD-based server motherboard. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0026] In recent years, a large number of domestically produced servers have emerged under the current information security environment. Therefore, addressing the issues of complex motherboard design, high cost, low integration, and insufficient performance expansion of management chips in existing domestically produced servers—which fall far short of meeting users' management and maintenance needs—has become a pressing problem for those skilled in the art.

[0027] Based on this, the present invention provides a CPLD-based server motherboard and server that uses a CPLD module to replace a large number of ICs (integrated circuits), resulting in high integration, reduced motherboard failure response time, reduced maintenance workload for domestic servers, and improved reliability and security of domestic servers.

[0028] In the description of this utility model, it should be noted that the terms "first", "second", "third", etc. are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0029] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0030] The following detailed description, in conjunction with the accompanying drawings, outlines some embodiments of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0031] Example 1

[0032] This utility model embodiment provides a server motherboard based on CPLD. Figure 1 This is a structural diagram of a CPLD-based server motherboard provided for an embodiment of the present invention. Figure 1 As shown, the CPLD-based server motherboard may include the following structure: a processor 101, a BIOS (Basic Input / Output System) chip 102, a CPLD (Complex Programmable Logic Device) module 103, and a BMC (Baseboard Management Controller) module 104; the CPLD module 103 is connected to the processor 101 through a first SPI (Serial Peripheral Interface), a first LPC (Low Pin Count) interface, and a first UART (Universal Asynchronous Receiver / Transmitter) interface; the CPLD module 103 is connected to the BMC module 104 through a second SPI interface, a second LPC interface, and a second UART interface; the CPLD module 103 is connected to the BIOS chip 102 through a third SPI interface.

[0033] In this embodiment of the invention, the processor 101 can be a CPU. The CPU features flexible configuration, low power consumption, and high memory access efficiency, and provides industry-leading computing performance, memory bandwidth, and I / O expansion capabilities. The CPU internally supports SPI, LPC, and UART interfaces, meaning bidirectional communication between the processor 101 and the GPLD module 103 can be achieved through the first SPI interface, the first LPC interface, and the first UART interface. The second SPI interface, the second LPC interface, and the second UART interface are used to achieve bidirectional communication between the BMC module 104 and the GPLD module 103, and the third SPI interface is used to achieve bidirectional communication between the BIOS chip 102 and the GPLD module 103. For example, the CPLD module uses the Anlogic CPLD EF2L25BG256B chip. This chip can perform level conversion and flexible signal processing. It features instant power-on, non-volatile storage, and high I / O counting. It also integrates user flash memory and enhanced in-system programmable devices, which can effectively reduce cost and power consumption. At the same time, it provides programmable solutions for applications such as bus bridging, I / O expansion and sequencing control, and device configuration control.

[0034] Specifically, through the first and third SPI interfaces, the processor 101 can obtain fault information and hardware information of the BIOS chip 102. Through the second and third SPI interfaces, the BMC module 104 controls the BIOS chip 102; for example, it can control the BIOS chip to perform read and write operations. Through the first and second LPC interfaces, the processor 101 and the BMC module 104 can exchange signals via the LPC protocol; for example, they can transmit handshake signals and heartbeat signals. Through the first and second UART interfaces, the processor 101 can send fault information of the BIOS chip 102 to the BMC module 104.

[0035] Furthermore, most domestically produced servers currently use a single BIOS chip. If this BIOS chip fails, the server will crash and become unusable, causing serious consequences. Considering the insufficient security performance, in this embodiment of the invention, the number of BIOS chips can be multiple, each connected in parallel to the CPLD module via a third SPI interface. It is understood that the number of third SPI interfaces is the same as the number of BIOS chips, with each BIOS chip having one third SPI interface connected to the CPLD module. By using multiple BIOS chips, the server can continue to operate even if one BIOS chip fails, improving the security of the CPLD-based server motherboard.

[0036] Furthermore, the CPLD module is also connected to the BMC module via a first GPIO interface (General-Purpose Input / Output). This first GPIO interface transmits at least one enable signal sent by the BMC module, which controls each BIOS chip. It is understood that the BMC module has the function of controlling each BIOS chip to perform read / write operations. Before controlling each BIOS chip to perform read / write operations, the BMC module needs to send an enable signal to each BIOS chip. After receiving the enable signal, each BIOS chip begins to perform read / write operations. The enable signals for different BIOS chips are different. After the BMS module sends the enable signal to the CPLD module via the first GPIO interface, the CPLD module determines the BIOS chip corresponding to the received enable signal and sends the enable signal to the corresponding BIOS chip via the third SPI interface. Using enable signals to control BIOS chips enables flexible switching between multiple BIOS chips, improving the flexibility of BIOS chip usage. Simultaneously, in the event of a BIOS chip failure, timely switching of the BIOS chip ensures normal server operation and improves the security of the CPLD-based server motherboard.

[0037] Furthermore, the CPLD module is also connected to the test equipment via the second GPIO interface to obtain power-on fault information transmitted by the processor and the BMC module through the test equipment.

[0038] Power-on fault information refers to fault messages issued by the processor and BMC module during the power-on process of a CPLD-based server motherboard. For example, power-on fault information can describe whether the processor or the BMC module failed to power on properly. The testing device can be an LED display screen. The CPLD module can provide a second GPIO interface. After connecting the testing device to the CPLD module through the second GPIO interface, the power-on fault information can be displayed, allowing technicians to process the fault information. This improves the convenience of maintenance for CPLD-based server motherboard technicians and reduces maintenance workload.

[0039] The CPLD-based server motherboard provided in this embodiment can use the CPLD module as a bridge to replace a large number of ICs (integrated circuits), resulting in high integration, reduced motherboard failure response time, reduced maintenance workload for domestic servers, and improved reliability and security of domestic servers.

[0040] Example 2

[0041] This utility model embodiment also provides another CPLD-based server motherboard; the CPLD-based server motherboard is implemented based on the above embodiment.

[0042] Figure 2 This is a structural diagram of another CPLD-based server motherboard provided as an embodiment of the present invention. (See diagram below.) Figure 2 As shown, the CPLD-based server motherboard includes the following structure: a processor 101, a BIOS chip 102, a CPLD module 103, and a BMC module 104. The BMC module 104 includes a BMC chip 1041 and a display module 1042. The BMC chip 1041 is connected to the CPLD module 103 via a second SPI interface, a second LPC interface, and a second UART interface, and is connected to the display module 1042 via a third GPIO interface. The display module 1042 is used to display the operational fault information.

[0043] The CPLD module 103 is used to receive the operation fault information of the BIOS chip 102 through the third SPI interface, and send the operation fault information to the BMC module 104 through the second SPI interface.

[0044] Specifically, after power-on, the processor of a CPLD-based server motherboard tests the BIOS chip. Operational fault information refers to the fault information detected by the BIOS chip during this test. Specifically, the BIOS chip can send operational fault information to the GPLD module via a third SPI interface. The GPIO module then sends the received operational fault information to the BMC chip via the SPI interface. The BMC chip can provide GPIO interfaces to connect to a display module, which can then send the received operational fault information to the display module for display. Furthermore, the display device can input simple program instructions to the BMC module for remote debugging of the BIOS chip, enabling remote debugging even without CPU support.

[0045] Furthermore, the CPLD-based server motherboard also includes a printed circuit board on which the processor, the BIOS chip, the CPLD module, and the BMC module are integrated.

[0046] The CPLD-based server motherboard provided in this embodiment integrates a display module in the BMC module, enabling it to display operational fault information without connecting an external monitor. This allows relevant technicians to promptly address operational fault information, improving the convenience of maintaining the CPLD-based server motherboard and reducing maintenance workload.

[0047] Example 3

[0048] This utility model embodiment also provides a CPLD-based server; the CPLD-based server is implemented based on the CPLD-based server motherboard of the above embodiment.

[0049] Figure 3 This is a structural diagram of a CPLD-based server provided for an embodiment of the present invention. Figure 3 As shown, the CPLD-based server includes a CPLD-based server motherboard 10.

[0050] The server motherboard based on CPLD includes a processor, a BIOS chip, a CPLD module, and a BMC module. There is at least one BIOS chip, and the CPLD module uses the Anlogic CPLD EF2L25BG256B chip.

[0051] When there are multiple BIOS chips, the CPLD module is also connected to the BMC module through a first GPIO interface. The first GPIO interface is used to transmit at least one enable signal sent by the BMC module, and the enable signal is used to control each of the BIOS chips.

[0052] Furthermore, the CPLD module is also connected to the test equipment via the second GPIO interface to obtain power-on fault information transmitted by the processor and the BMC module through the test equipment.

[0053] Furthermore, the BMC module includes a BMC chip and a display module. The BMC chip is connected to the CPLD module via a second SPI interface, a second LPC interface, and a second UART interface, and to the display module via a third GPIO interface. The display module is used to display operational fault information of the BIOS chip.

[0054] The CPLD-based server provided in this embodiment can use CPLD modules to replace IC circuits on the CPLD-based server motherboard, which has high integration, reduces motherboard failure response time, reduces maintenance workload for domestic servers, and improves the reliability and security of domestic servers.

[0055] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0056] Finally, it should be noted that the above-described embodiments are merely specific implementations of this utility model, used to illustrate the technical solution of this utility model, and not to limit it. The protection scope of this utility model is not limited thereto. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this utility model. These modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A CPLD-based server motherboard, characterized in that, The CPLD module is connected with the processor through a first SPI interface, a first LPC interface and a first UART interface, and is connected with the BMC module through a second SPI interface, a second LPC interface and a second UART interface.

2. The CPLD-based server motherboard of claim 1, wherein, The number of the BIOS chips is multiple, and each BIOS chip is connected with the CPLD module in parallel through a third SPI interface.

3. The CPLD-based server motherboard of claim 2, wherein, The CPLD module is further connected with the BMC module through a first GPIO interface, the first GPIO interface is used for transmitting at least one enable signal sent by the BMC module, and the enable signal is used for controlling each BIOS chip.

4. The CPLD-based server motherboard of claim 1, wherein, The CPLD module adopts an Anlogic CPLD EF2L25BG256B chip.

5. The CPLD-based server motherboard of claim 1, wherein, The CPLD module is further connected with a test device through a second GPIO interface, so as to acquire power failure information transmitted by the processor and the BMC module through the test device.

6. The CPLD-based server motherboard of claim 1, wherein, The CPLD module is used for receiving running failure information of the BIOS chip through the third SPI interface, and sending the running failure information to the BMC module through the second SPI interface.

7. The CPLD-based server motherboard of claim 6, wherein, The BMC module comprises a BMC chip and a display module, the BMC chip is connected with the CPLD module through a second SPI interface, a second LPC interface and a second UART interface, and is connected with the display module through a third GPIO interface.

8. The CPLD-based server motherboard of claim 7, wherein, The display module is used for displaying the running failure information.

9. The CPLD-based server motherboard of claim 1, wherein, Further comprising a printed circuit board, and the processor, the BIOS chip, the CPLD module and the BMC module are integrated on the printed circuit board.

10. A CPLD-based server, characterized by, The CPLD-based server mainboard comprises the server mainboard according to any one of claims 1-9.

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