Logic time sequence interlocking circuit, equipment controller and equipment

Abstract

The embodiment of the utility model provides a logic time sequence interlocking circuit and equipment applying the logic time sequence interlocking circuit, and belongs to the technical field of electronic circuits. According to the logic time sequence interlocking circuit, two dual-optocoupler chips, a Schmidt trigger chip and a monostable chip are adopted, and two independent input signals are converted into one conventional digital quantity output signal and one logic interlocking signal output signal. Only when the second input signal is at a low level in the window time after the falling edge of the first input signal, the logic linkage signal output signal can output a high level, logic and time sequence linkage of the two output signals is achieved, the window time is set through the monostable chip, and misoperation caused by external interference is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic circuit technical field, concretely relates to a kind of logic time sequence interlocking circuit and the equipment of application this logic time sequence interlocking circuit. BACKGROUND

[0002] In production equipment or life equipment, the control signal of interlocking control needs to be guaranteed not to appear failure condition, otherwise serious consequences can be generated.In prior art, the interlocking control signal of control equipment is usually independently generated, and the two independently generated control signals can be designed as logic interlocking mode by software mode or hardware mode.

[0003] The present application inventors found in the process of realizing the utility model that, in prior art, whether by software mode or hardware mode, individual component or individual digital input signal failure exists, which can lead to control logic interlocking failure.The control signal of digital quantity output signal 1 is high level, while actual driving circuit still maintains low level, which can lead to equipment failure. UTILITY MODEL CONTENT

[0004] The purpose of the embodiment of the utility model is to provide a kind of logic time sequence interlocking circuit, for converting independent two-way input signal into two-way output signal of logic interlocking, which can improve the effectiveness of logic interlocking.

[0005] In order to achieve the above-mentioned purpose, the embodiment of the utility model provides a kind of logic time sequence interlocking circuit, for converting independent first input signal and second input signal into two-way output signal of logic interlocking, comprising: first double optocoupler chip, second double optocoupler chip and edge monitoring circuit,

[0006] Wherein, edge monitoring circuit includes monostable multivibrator, for monitoring the falling edge of input digital signal, and output preset time width pulse signal when monitoring falling edge signal;

[0007] First input signal is divided into two ways, one way is connected to the first input end of the first optocoupler of first double optocoupler chip, and the other way is connected to the first input end of the first optocoupler of second double optocoupler chip through edge monitoring circuit;

[0008] Second input signal is connected to the second input end of the second optocoupler of second double optocoupler chip;

[0009] The first optocoupler of second double optocoupler chip and the second optocoupler are connected in series;

[0010] The first output end of the first optocoupler of first double optocoupler chip and the first output end of the first optocoupler of second double optocoupler chip are connected in parallel to output first output signal, and the second output end of the second optocoupler of second double optocoupler chip outputs second output signal.

[0011] Preferably, the edge monitoring circuit further includes an RC filter circuit, and the preset time width of the pulse signal is determined according to the filtering time of the RC filter circuit.

[0012] Preferably, the edge monitoring circuit also includes a Schmitt trigger chip. The first input signal is divided into two paths: one path is directly connected to one input terminal of the monostable chip, and the other path is processed by the Schmitt trigger chip before being connected to the other input terminal of the monostable chip.

[0013] Preferably, the edge monitoring circuit further includes a voltage divider circuit for stabilizing the high and low levels of the monostable chip output.

[0014] Preferably, the Schmitt trigger chip is the SN74HC14D chip, and the third pin of the SN74HC14D chip is connected to the first input signal and processed before being output by the fourth pin.

[0015] Preferably, the monostable chip is the MC74HC4538AD chip, wherein the third and fifth pins of the MC74HC4538AD chip are connected to the first input signal; the fourth pin of the MC74HC4538AD chip is connected to the first input signal output after being processed by the Schmitt trigger chip; and the sixth pin of the MC74HC4538AD chip outputs the obtained pulse signal.

[0016] Furthermore, the first dual optocoupler chip and the second dual optocoupler chip are ELD3H7 chips. The second input terminal of the first optocoupler of the second dual optocoupler chip and the first input terminal of the second optocoupler of the second dual optocoupler chip are shorted together, and the second output terminal of the first optocoupler of the second dual optocoupler chip and the first output terminal of the second optocoupler of the second dual optocoupler chip are shorted together.

[0017] On the other hand, this utility model embodiment also provides a device controller, including the logic timing interlocking circuit of this application. After the two independent control signals are processed by the logic timing interlocking circuit, the output two logic interlocking control signals are applied to the device to be controlled.

[0018] Optionally, the equipment to be controlled can be motor equipment, power equipment, electrical equipment, or electrical appliances.

[0019] On the other hand, this utility model embodiment also provides a device, including the device controller of this application, which receives control signals processed by the device controller and controls the operating parameters of the device through the control signals.

[0020] The above technical solution employs two dual optocoupler chips, a Schmitt trigger chip, and a monostable multivibrator chip to convert two independent input signals into one conventional digital output signal and one logic interlocking output signal. The logic interlocking output signal can only output a high level when the second input signal is low within a window period following the falling edge of the first input signal. This achieves logical and timing interlocking of the two output signals. Furthermore, the monostable multivibrator chip is used to set the window time, reducing malfunctions caused by external interference.

[0021] Other features and advantages of this utility model embodiment will be described in detail in the following detailed description section. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0023] Figure 1 This is a circuit diagram of an embodiment of the logical timing interlocking circuit of this application. Detailed Implementation

[0024] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0025] It should be noted that the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0026] Figure 1 A circuit diagram of a logic timing interlocking circuit provided in an embodiment of this utility model. This logic timing interlocking circuit is used to convert two input signals into two logically interlocked output signals. The first input signal is... Figure 1 The first input signal is generated by the microcontroller's DO1 terminal, and the second input signal is generated by the microcontroller's DO2 terminal. However, this application is not limited to this; the two input signals can be any two signals generated independently or in conjunction. The two signals can be directly generated digital signals or digital signals obtained through AD conversion. The purpose of this application is to keep the first of the two input signals unchanged, and convert the second signal into a control signal interlocked with the first signal.

[0027] In this embodiment, the logic timing interlocking circuit includes a first dual optocoupler chip Q1, a second dual optocoupler chip Q2, and an edge monitoring circuit, such as... Figure 1 As shown, both the first and second dual optocoupler chips are ELD3H7 chips, but this application is not limited to this; it is sufficient to include two independent optocouplers. The edge monitoring circuit is used to monitor the falling edge of the input digital signal and outputs a pulse signal with a preset time width when the falling edge signal is detected. The first input signal DO1 is divided into two paths, one of which is connected to the first pin of Q1, and the other is connected to the first pin of Q2 via the edge monitoring circuit. The second input signal DO2 is connected to the fourth pin of Q2. The first optocoupler of Q2 is connected in series with the second optocoupler, that is, the second and third pins of Q2 are shorted, and the sixth and seventh pins are shorted. The eighth pins of Q1 and Q2 are connected in parallel to output the first output signal DO_PIN1, and the fifth pin of Q2 outputs the second output signal DO_PIN2.

[0028] It should be noted that in this embodiment, the edge monitoring circuit includes a monostable multivibrator chip MC74HC4538AD and a Schmitt trigger chip SN74HC14D. The first input signal DO1, which enters and exits Q2, is processed by the edge monitoring circuit and then divided into two paths. One path is directly connected to the third and fifth pins of the MC74HC4538AD, and the other path is connected to the fourth pin of the MC74HC4538AD via the SN74HC14D. This edge monitoring circuit outputs a pulse when a falling edge occurs in the first input signal DO1. Simultaneously, since the second pin of the MC74HC4538AD is also connected to the resistor and capacitor of the filter circuit, it is used to determine the width of the generated pulse signal. During this pulse signal period, when the second input signal DO2 is low, DO_PIN2 can output a high level. Even if the first input signal DO1 generates multiple falling edges, no new pulse signal will be generated until the pulse signal width is completed. Alternatively, this pulse signal width can be referred to as the window time. This application achieves logical and timing interlocking of the two digital input signals DO1 and DO2 within the window time, reducing malfunctions caused by external interference.

[0029] In this embodiment, opto-isolation of the input and output terminals is achieved through dual optocoupler chips. A 3.3V DC power supply is used on the input side, and a 24V DC power supply is used on the output side. Resistor R1 is a pull-up resistor used to raise the input voltage of Q1 and MC74HC4538AD. Resistor R2 is a current-limiting resistor used to limit the input current of the first optocoupler of Q1, and also limit the current of the first signal DO1 output by the microcontroller. Resistor R4 is a current-limiting resistor used to limit the input current of the second optocoupler of Q2, and also limit the current of the second signal DO2 output by the microcontroller. Resistor R3 is a voltage-limiting resistor connected between the first pin of Q2 and resistor R4 to limit the voltage applied to the input side of Q2 and prevent voltage overshoot. Resistor R5 is a current-limiting resistor connected to the output power supply for overall current limiting. Resistor R6 is a current-limiting resistor used to limit the output current of the first optocoupler of Q1. Resistor R7 is a current-limiting resistor used to limit the output current of the optocoupler of Q2. Resistors R8 and R9 are voltage divider resistors connected to the output terminal (pin 6) of the monostable multivibrator chip MC74HC4538AD. They are used to stabilize the high and low levels of the pulse signal output by the monostable multivibrator chip. Resistors R8 and R9 determine the high and low output levels, respectively. Resistor R10 is a resistor in the filter circuit; its value is determined based on the desired filtering time, t, which is equal to 0.7 * R10 * C1.

[0030] Compared with the prior art, the technical advantages of this embodiment are as follows:

[0031] 1. The falling edge of the first input signal is monitored by the edge monitoring circuit, and a pulse signal with a fixed time window is generated. Within this time window, DO_PIN2 can only output a high level when the second input signal is low.

[0032] 2. By setting the time window width, malfunctions caused by external interference are reduced.

[0033] 3. The device uses dual optocouplers, which include two independent optocouplers, reducing the probability of device failure in discrete optocouplers and improving the reliability of logic interlock signals.

[0034] 4. Shorting pins 6 and 7 of Q2 enables the series connection of the two optocoupler outputs, ensuring the reliability of the logic interlock.

[0035] 5. Multiple resistors are used to limit voltage and current respectively, ensuring the overall safety of the circuit. Integrated resistors are used to further reduce resistance drift caused by temperature, ensuring output stability and low variation.

[0036] This utility model embodiment also provides a device controller, including the logic timing interlocking circuit of this application. After the two independent control signals are processed by the logic timing interlocking circuit, the output two logic interlocking control signals are applied to the device to be controlled.

[0037] In some implementations, the device to be controlled is a motor, power, electrical equipment, or electrical appliance.

[0038] On the other hand, this utility model embodiment also provides a device, including the device controller of this application, which receives control signals processed by the device controller and controls the operating parameters of the device through the control signals.

[0039] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0040] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A logic sequential chain circuit for converting independent first and second input signals into two output signals in a logic chain, characterized by, include: The first dual optocoupler chip, the second dual optocoupler chip, and the edge monitoring circuit. The edge monitoring circuit includes a monostable chip, which is used to monitor the falling edge of the input digital signal and output a pulse signal with a preset time width when the falling edge signal is detected. The first input signal is divided into two paths, one of which is connected to the first input terminal of the first optocoupler of the first dual optocoupler chip, and the other is connected to the first input terminal of the first optocoupler of the second dual optocoupler chip via the edge monitoring circuit. The second input signal is connected to the second input terminal of the second optocoupler of the second dual optocoupler chip; The first optocoupler and the second optocoupler of the second dual optocoupler chip are connected in series; The first output terminal of the first optocoupler of the first dual optocoupler chip and the first output terminal of the first optocoupler of the second dual optocoupler chip are connected in parallel to output a first output signal, and the second output terminal of the second optocoupler of the second dual optocoupler chip outputs a second output signal.

2. The logic sequential circuit according to claim 1, wherein The edge monitoring circuit also includes an RC filter circuit, and the preset time width of the pulse signal is determined according to the filtering time of the RC filter circuit.

3. The logic sequential circuit according to claim 2, wherein The edge monitoring circuit also includes a Schmitt trigger chip. The first input signal is divided into two paths: one path is directly connected to one input terminal of the monostable chip, and the other path is processed by the Schmitt trigger chip before being connected to the other input terminal of the monostable chip.

4. The logic sequential circuit according to claim 3, wherein The edge monitoring circuit also includes a voltage divider circuit for stabilizing the high and low levels output by the monostable chip.

5. The logic sequential circuit according to claim 3, wherein The Schmitt trigger chip is an SN74HC14D chip. The third pin of the SN74HC14D chip is connected to the first input signal and processed before being output by the fourth pin.

6. The logic sequential circuit according to claim 5, wherein, The monostable chip is the MC74HC4538AD chip. The third and fifth pins of the MC74HC4538AD chip are connected to the first input signal. The fourth pin of the MC74HC4538AD chip is connected to the first input signal output after being processed by the Schmitt trigger chip; The pulse signal obtained by the output of the sixth pin of the MC74HC4538AD chip.

7. The logic sequential circuit according to claim 6, wherein The first dual optocoupler chip and the second dual optocoupler chip are ELD3H7 chips. The second input terminal of the first optocoupler of the second dual optocoupler chip is shorted to the first input terminal of the second optocoupler of the second dual optocoupler chip, and the second output terminal of the first optocoupler of the second dual optocoupler chip is shorted to the first output terminal of the second optocoupler of the second dual optocoupler chip.

8. A device controller, characterized by The system includes a logic timing interlocking circuit according to any one of claims 1 to 7, wherein after the two independent control signals are processed by the logic timing interlocking circuit, the output two logic interlocking control signals are applied to the device to be controlled.

9. The device controller of claim 8, wherein, The equipment to be controlled is motor equipment, power equipment, electrical equipment, or electrical appliance equipment.

10. An apparatus, comprising: Includes the device controller according to claim 8 or 9, which receives control signals processed by the device controller and controls the operating parameters of the device through the control signals.

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