Coupler

Abstract

A coupler relates to the technical field of industrial control. The coupler comprises a protocol bus interface, a communication processing module, a data processing module and an expansion bus interface. The protocol bus interface is used for performing data interaction with a protocol network; the communication processing module is used for sending bus data to the data processing module, or the communication processing module is used for obtaining backboard data sent by the data processing module and sending the backboard data to the protocol bus interface; the input end of an uplink unit in the data processing module is connected with the communication processing module, and the output end of the uplink unit is connected with the expansion bus interface so as to send bus data to the expansion bus interface; the input end of the downlink unit is connected with the expansion bus interface, and the output end of the downlink unit is connected with the communication processing module so as to obtain backboard data sent by the expansion bus interface; and the expansion bus interface is used for connecting at least one preset expansion module to send the bus data to each expansion module, so that the coupler with high interaction efficiency is provided.

Description

Technical Field

[0001] This application relates to the field of industrial control technology, and specifically to a coupler. Background Technology

[0002] Industrial control applications require extensive data transmission, demanding not only high-capacity I / O but also extremely stringent real-time performance. PROFINET is an open industrial Ethernet communication protocol, primarily proposed by Siemens and the PROFIBUS & PROFINET international association. This protocol offers higher real-time performance and faster transmission rates compared to fieldbus technologies.

[0003] In recent years, with the continuous advancement of Industry 4.0, PROFINET bus-based devices have become a mainstream trend in industrial manufacturing. There are two main implementation schemes based on the PROFINET interface bus, both domestically and internationally, which can be categorized according to their hardware architecture and protocol stack implementation: one is based on a communication soft core, implementing the PROFINET protocol stack in a general-purpose microprocessor; the other is based on a dedicated ASIC communication chip or module, where the PROFINET protocol stack is handled by a dedicated chip or module.

[0004] Both of the above-mentioned PROFINET protocol processing methods are quite complex. Using a communication soft core would not meet the high real-time requirements, so currently, a dedicated ASIC is preferred for protocol stack processing. However, a single dedicated ASIC system architecture, due to its processor resource limitations, cannot handle large amounts of data effectively. Summary of the Invention

[0005] This application provides a coupler with a simpler circuit and higher real-time performance, aiming to solve the problems of limited processing resources and low real-time performance of existing couplers using ASIC systems.

[0006] According to one aspect of this application, one embodiment provides a coupler, including: a protocol bus interface, a communication processing module, a data processing module, and an expansion bus interface;

[0007] The protocol bus interface is used for data interaction with the protocol network;

[0008] The communication processing module connects the protocol bus interface and the data processing module; the communication processing module is used to acquire bus data sent by the protocol bus interface and send the bus data to the data processing module, or the communication processing module is used to acquire backplane data sent by the data processing module and send the backplane data to the protocol bus interface.

[0009] The data processing module communicates serially with the communication processing module. The data processing module includes an uplink unit and a downlink unit. The input terminal of the uplink unit is connected to the communication processing module, and the output terminal of the uplink unit is connected to the extended bus interface to send the bus data to the extended bus interface. The input terminal of the downlink unit is connected to the extended bus interface, and the output terminal of the downlink unit is connected to the communication processing module to obtain the backplane data sent by the extended bus interface.

[0010] The extended bus interface is used to connect at least one preset extended module to send the bus data to each extended module.

[0011] In one embodiment, the communication processing module further includes a first serial communication unit, and the data processing module further includes a second serial communication unit. One end of the second serial communication unit is connected to the input terminal of the uplink unit and the output terminal of the downlink unit, and the other end of the second serial communication unit is connected to one end of the first serial communication unit.

[0012] In one embodiment, the uplink unit includes:

[0013] A verification circuit, the input of which is connected to the input of the uplink unit, is used to verify the integrity of the bus data;

[0014] A first data buffer circuit, the input of which is connected to the output of the verification circuit, is used to store and match the bus data in terms of bit width.

[0015] A filtering circuit, wherein the input terminal of the filtering circuit is connected to the output terminal of the first data buffer circuit, is used to filter the bus data;

[0016] An encoding circuit, the input of which is connected to the output of the filtering circuit, is used to encode the bus data;

[0017] A first format conversion circuit, wherein the input of the first format conversion circuit is connected to the encoding circuit and the output of the first format conversion circuit is connected to the extended bus interface, is used to convert the format of the bus data to adapt to the extended bus interface.

[0018] In one embodiment, the downlink unit includes:

[0019] The second format conversion circuit, whose input is connected to the extended bus interface, is used to convert the backplane data to a format suitable for the communication processing module.

[0020] A decoding circuit, the input of which is connected to the output of the second format conversion circuit, is used to decode the backplane data;

[0021] A data verification circuit, the input of which is connected to the output of the decoding circuit, is used to perform integrity verification on the backplane data;

[0022] The second data buffer circuit has its input connected to the output of the data verification circuit and its output connected to the output of the downlink unit. It is used to store and match the bit width of the backplane data.

[0023] In one embodiment, the communication processing module is further connected to a first crystal oscillator to provide a clock signal to the communication processing module; and / or, the data processing module is further connected to a second crystal oscillator to provide a clock signal to the data processing module.

[0024] In one embodiment, the communication processing module is further connected to a first reset chip for resetting the communication processing module when a fault occurs; and / or, the data processing module is further connected to a second reset chip for resetting the data processing module when a fault occurs.

[0025] In one embodiment, the communication processing module is further connected to a first extended peripheral device for functional expansion of the communication processing module; and / or, the data processing module is further connected to a second extended peripheral device for functional expansion of the data processing module.

[0026] In one embodiment, the extended bus interface is an E_BUS bus interface.

[0027] In one embodiment, the protocol bus interface is a Profinet bus interface, and the protocol network is the Profinet protocol.

[0028] In one embodiment, the communication processing module is an ASIC chip, and the data processing module is an FPGA.

[0029] The coupler according to the above embodiments includes a protocol bus interface, a communication processing module, a data processing module, and an expansion bus interface. The protocol bus interface is used for data interaction with a protocol network, and the communication processing module sends bus data sent by the protocol bus interface to the data processing module, or sends backplane data sent by the data processing module to the protocol bus interface. The data processing module includes an uplink unit and a downlink unit. The uplink unit sends bus data to the expansion bus interface, and the downlink unit sends backplane data to the communication processing module. The expansion bus module connects to expansion modules to send bus data to each expansion module. This application utilizes the communication processing module for communication and the data processing module for data processing and interaction, thereby enabling more efficient use of processor resources and improving response speed. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of an ASIC+ARM architecture in one embodiment;

[0031] Figure 2 A schematic diagram of the coupler structure in one embodiment. Figure One ;

[0032] Figure 3 This is a schematic diagram of the communication processing module in one embodiment;

[0033] Figure 4 This is a schematic diagram of the data processing module in one embodiment;

[0034] Figure 5 A schematic diagram of the coupler structure in one embodiment. Figure Two . Detailed Implementation

[0035] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0036] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments, and the operational steps involved in each embodiment can also be rearranged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the specification and drawings are only for clearly describing a particular embodiment and do not imply that they represent the necessary components and / or order.

[0037] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0038] Please refer to Figure 1 The slave station solution, employing a dual-core ASIC+ARM system architecture, solves the problem of insufficient chip resources hindering the development of complex Profinet protocols. However, existing ASIC+ARM coupler products based on the Profinet protocol still have shortcomings. Specifically, the coupler needs to expand its I / O capacity to accommodate various modules, such as analog, digital, temperature, and pulse modules. A significant amount of code is required in the ARM architecture to handle adaptation and data interaction. Furthermore, in low-latency processing scenarios, ASIC+ARM technology lacks real-time performance in RT (RT communication, for data exchange between sensors (remote I / O devices) and actuators, where response time requirements are more stringent, approximately 1-10ms) and IRT (IRT communication, in field-level communication, motion control has the highest real-time requirements; Profinet's synchronous real-time technology can meet the high-speed communication needs of motion control, with a response time of less than 1ms and a jitter error of less than 1μs for 100 nodes).

[0039] In one embodiment, in order to ensure the efficiency of the communication system in RT and IRT, this application uses ASIC+FPGA to implement the Profinet protocol. By distributing the communication protocol and application data, a dedicated communication chip is used to run the communication protocol, and the FPGA performs a large amount of data calculation and data interaction applications, thereby enabling the program to use CPU resources more efficiently and improving the program's response speed. The details are described below.

[0040] Please refer to Figure 2 In one embodiment, the coupler 100 provided in this application includes a protocol bus interface 110, a communication processing module 120, a data processing module 130, and an expansion bus interface 140.

[0041] In one embodiment, the protocol bus interface 110 is used to interact with the protocol network, wherein the protocol bus interface 110 is a Profinet bus interface and the protocol network is the Profinet protocol.

[0042] It should be noted that the coupler 100 is essentially a data bridging device used to connect different types of buses or data interfaces. The main function of the coupler 100 provided in this application is to convert the data stream processed in the data processing module 130 between the data and the Profinet bus interface. The Profinet bus is an industrial Ethernet, and Profinet slaves and masters are connected to the Profinet bus. Within the coupler 100, the Profinet bus is represented by the industrial Ethernet interface connected to the communication processing module 120, which is also the Profinet bus interface. The communication processing module 120, as a communication chip, connects to the Profinet protocol through the Profinet bus interface, thereby interacting with the Profinet protocol for data exchange.

[0043] In one embodiment, the communication processing module 120 connects the protocol bus interface 110 and the data processing module 130, wherein serial communication is used between the communication processing module 120 and the data processing module 130. The communication processing module 120 is used to acquire Profinet bus data (i.e., bus data) sent by the protocol bus interface 110 and send the bus data to the data processing module 130. The communication processing module 120 is also used to acquire backplane data sent by the data processing module 130 and send the backplane data to the protocol bus interface 110.

[0044] It should be noted that the communication processing module 120 is an ASIC chip specifically designed to run the Profinet protocol. Because the Profinet protocol itself requires high real-time performance and high reliability, the ASIC chip provides customized hardware support, ensuring that the protocol stack processing is not limited by general-purpose processors, thus maintaining low latency in both RT and IRT modes. The ASIC chip is mainly used to communicate with and receive backplane data sent by the data processing module 130, while also sending bus data to the data processing module 130 for further processing. The communication processing module 120 uses the Profinet bus interface to realize data communication and system control between the Profinet slave and the Profinet master station, such as receiving data sent by the Profinet master station in real time and performing data identification and processing through the protocol stack.

[0045] Please refer to Figure 3In one embodiment, the communication processing module 120 includes a bottom buffer 121, a slot / subslot 122, a backplane data transmission module 123, a memory space 124, a bus data transmission module 125, and a first serial communication unit 126.

[0046] In one embodiment, the underlying buffer 121 is used for data caching, protocol conversion, data parsing, and encapsulation of data in the ASIC chip. In the slot / subslot 122, a slot represents a physical or logical module of the device, which can be a socket, functional unit, or interface module; a subslot represents a specific functional unit or data channel within the slot.

[0047] In one embodiment, the communication processing module 120 temporarily stores the backplane data sent by the data processing module 130 into the memory space 124 via the first serial communication unit 126. The memory space 124 then sends the backplane data to the backplane data transmission module 123. The backplane data transmission module 123 maps the backplane data to corresponding slots / sub-slots 122, where data from different modules is stored in different slots / sub-slots 122. The slots / sub-slots 122 send the backplane data to the underlying buffer 121, which performs transmission format conversion on the backplane data and uploads it to the protocol bus interface 110. The communication processing module 120 also acquires the bus data sent by the protocol bus interface 110. The underlying buffer 121 extracts the bus data and stores the extracted data in the slots / sub-slots 122 according to different functional modules. Slot / subslot 122 then sends the data to bus data transmission module 125, bus data transmission module 125 sends the bus data to memory space 124, and memory space 124 sends the bus data to data processing module 130 through first serial communication unit 126.

[0048] Please refer to Figure 4 In one embodiment, the data processing module 130 includes an uplink unit 131 and a downlink unit 132. The input of the uplink unit 131 is connected to the communication processing module 120, and the output of the uplink unit 132 is connected to the extended bus interface 140 to send bus data to the extended bus interface 140. The input of the downlink unit 132 is connected to the extended bus interface 140, and the output of the downlink unit 132 is connected to the communication processing module 120 to obtain backplane data sent by the extended bus interface 140.

[0049] In one embodiment, the data processing module 130 further includes a second serial communication unit 133. The input terminal of the uplink unit 131 is connected to one end of the second serial communication unit 133. One end of the second serial communication unit 133 is also connected to the output terminal of the downlink unit 132. The other end of the second serial communication unit 133 is connected to one end of the first serial communication unit 126, so as to realize the serial communication connection between the data processing module 130 and the communication processing module 120.

[0050] It should be noted that the data processing module 130 is an FPGA, mainly used for large-scale data computation and data interaction applications. The FPGA has parallel computing capabilities, enabling it to process multiple data streams in parallel at the hardware level for complex calculations or data exchange. After receiving bus data from the Profinet master station, the FPGA parses the non-cyclic data that does not require repeated processing or does not change periodically. Once it is determined that the configuration data of the expansion module matches the configuration data set by the Profinet master station, the FPGA processes the bus data through the uplink unit 131 and transmits the bus data to the corresponding configuration data expansion module connected to the expansion bus interface 140 via the expansion bus interface 140. Simultaneously, the downlink unit 132 of the data processing module 130 reads back and reverses the backplane data from the expansion bus interface 140, sending the backplane data to the protocol bus interface 110 via the communication processing module 120.

[0051] In one embodiment, the expansion bus interface 140 is used to connect at least one preset expansion module to send bus data to the expansion module.

[0052] It should be noted that the expansion bus interface 140 is an E-BUS bus interface, which can realize various I / O functions, including digital input / output, analog input / output, and temperature acquisition. The specific expansion modules can be configured according to the required expansion functions of the coupler 100, and are not limited here.

[0053] In one embodiment, the uplink unit 131 includes a verification circuit 1311, a first data buffer circuit 1312, a filtering circuit 1313, an encoding circuit 1314, and a first format conversion circuit 1315. The input of the verification circuit 1311 is connected to the input of the uplink unit and is used to verify the integrity of the bus data. The input of the first data buffer circuit 1312 is connected to the output of the verification circuit 1311 and is used to store and match the bit width of the bus data. The input of the filtering circuit 1313 is connected to the output of the first data buffer circuit 1312 and is used to filter the bus data. The input of the encoding circuit 1314 is connected to the output of the filtering circuit 1313 and is used to encode the bus data. The input of the first format conversion circuit 1315 is connected to the encoding circuit 1314, and the output of the first format conversion circuit 1315 is connected to the extended bus interface 140, used to convert the format of the bus data to adapt to the extended bus interface 140.

[0054] In one embodiment, the first data cache circuit 1312, in addition to storing bus data using a buffer, also stores data read from external DRAM memory cells or data to be written, and reassembles the data through hardware logic to ensure that the data matches the bit width of the FPGA. If the bus bit width between the FPGA and the external DRAM memory cells is inconsistent, the FPGA will implement bit width matching through hardware logic. For example, if the data bus inside the FPGA is 32 bits, while the bus of the external DRAM memory cell is 16 bits, the FPGA needs to divide or merge the data to ensure correct data transmission.

[0055] It should be noted that the verification circuit 1311, the first data buffer circuit 1312, the filtering circuit 1313, the encoding circuit 1314, and the first format conversion circuit 1315 are all implemented based on the internal hardware resources of the FPGA. For example, the verification circuit 1311 can use the XOR logic gate in the FPGA to calculate the parity of the bus data, thereby realizing parity verification of the bus data. The buffer area of ​​the first data buffer circuit 1312 can use the BRAM inside the FPGA. BRAM is an on-chip storage resource inside the FPGA used for storing data, buffering information, etc. The filtering circuit 1313 can use an FIR filter, which can be implemented using a shift register and a multiply-accumulate. The encoding circuit 1314 can use XOR logic to implement data conversion. The first format conversion circuit 1315 can use a shift register to convert serial data into parallel data.

[0056] In one embodiment, the downlink unit 132 includes a second format conversion circuit 1321, a decoding circuit 1322, a data verification circuit 1323, and a second data buffer circuit 1324. The input of the second format conversion circuit 1321 is connected to the expansion bus interface 140 and is used to convert the backplane data format to adapt to the communication processing module 120. The input of the decoding circuit 1322 is connected to the output of the second format conversion circuit 1321 and is used to decode the backplane data. The input of the data verification circuit 1323 is connected to the output of the decoding circuit 1322 and is used to perform integrity verification on the backplane data. The input of the second data buffer circuit 1324 is connected to the output of the data verification circuit 1323, and the output of the second data buffer circuit is connected to the output of the downlink unit 132, used to store and match the bit width of the backplane data.

[0057] In one embodiment, the second data cache circuit 1324, in addition to storing backplane data using a buffer, also stores data read from external DRAM memory cells or data to be written, and reassembles the data through hardware logic to ensure that the data matches the bit width of the FPGA. If the bus bit width between the FPGA and the external DRAM memory cells is inconsistent, the FPGA will implement bit width matching through hardware logic.

[0058] It should be noted that the second format conversion circuit 1321, the decoding circuit 1322, the data verification circuit 1323, and the second data buffer circuit 1324 are all implemented based on the internal hardware resources of the FPGA. For example, the second format conversion circuit 1321 can use a shift register to convert parallel data into serial data. The decoding circuit 1322 can also use a shift register to decode serial data. The data verification circuit 1323 can use an adder-accumulator to calculate the data checksum. The buffer area of ​​the second data buffer circuit 1324 is the same as that of the first data buffer circuit, and can also be implemented using the BRAM inside the FPGA.

[0059] Please refer to Figure 5 In one embodiment, the communication processing module 120 is also connected to a first crystal oscillator to provide a clock signal for the communication processing module. The first crystal oscillator provides a stable clock source for the ASIC, ensuring that the various modules within the ASIC can operate synchronously according to a fixed timing sequence. The data processing module 130 is also connected to a second crystal oscillator to provide a clock signal for the data processing module. All operations of the data processing module 130 require a clock signal for synchronous execution. The second crystal oscillator outputs a stable clock signal for use by the timing circuits within the data processing module 130, ensuring the correctness and stability of data transmission and processing. The first and second crystal oscillators can be passive or active crystal oscillators.

[0060] In one embodiment, the communication processing module 120 is further connected to a first reset chip for resetting the communication processing module 120 in the event of a fault. The data processing module 130 is further connected to a second reset chip for resetting the data processing module 130 in the event of a fault. When the coupler 100 is powered on or power is restored, the first and second reset chips provide a stable reset signal to the communication processing module 120 and the data processing module 130 to ensure they start working from a known initial state and prevent operation before full initialization. Simultaneously, if the coupler 100 detects an abnormality or error, the first and second reset chips can trigger a reset operation to ensure the coupler 100 returns to its initial state, preventing data errors or instability caused by abnormal conditions.

[0061] It should be noted that the first reset chip and the second reset chip can be the same chip or two different chips. If the same reset chip is used, a multi-output reset chip such as the TPS3808 or ADM8318 can be used to reset the communication processing module 120 and the data processing module 130 with different delays. If two different reset chips are used, the reset timing of the communication processing module 120 and the data processing module 130 can be controlled separately by the two reset chips.

[0062] In one embodiment, the communication processing module 120 is further connected to a first extended peripheral for functional expansion. The data processing module 130 is further connected to a second extended peripheral for functional expansion. The first and / or second extended peripherals connected to the data processing module 130 include test interfaces, run indicator lights, etc. Simultaneously, the data processing module 130 and the communication processing module 120 interact, transmitting large amounts of data through the serial ports on the first and / or second extended peripherals. From a hardware perspective, this application uses an FPGA for expansion, which makes circuit routing more convenient and concise. Using an FPGA allows for easy construction of basic communication interfaces, saving hardware costs and PCB board space.

[0063] It should be noted that the first and second extended peripherals can be storage devices, communication interfaces, input / output devices, and sensors, etc., to enhance the functionality and performance of the coupler 100. The storage device is used to provide large-capacity data storage, or for data caching and program loading, and can be SRAM, DRAM, or Flash memory. The communication interface is used to enable communication between the FPGA or ASIC and external devices, such as a host computer, other processors, or sensors. The communication interface can be a serial port, I2C, SPI, Ethernet, USB, or PCIe. The input / output devices are used for user interaction or to indicate the status of the coupler 100. Input / output devices can be LED indicators, buttons, LCD / LED displays, or general-purpose I / O ports. The sensor is used to acquire environmental data to provide feedback control; the sensor can be a temperature sensor, accelerometer, photoelectric sensor, or analog-to-digital converter.

[0064] The coupler 100 provided in this application adopts an ASIC+FPGA system architecture, which has significant advantages over the dual-core ASIC+ARM system architecture in terms of data processing, application processing, switching difficulty, and supported IO capacity.

[0065] When processing data, ARM's data flow is typically limited by memory latency and instruction-level parallelism. Even in multi-core ARM processors, parallel processing mainly relies on the operating system scheduling threads. In contrast, FPGA's data processing method is hardware-level parallelism, where each data stream can be processed by an independent hardware unit, reducing processing time.

[0066] In terms of application processing, ARM is suitable for general-purpose computing tasks, while FPGA is mainly used for specialized computing tasks, especially those applications with high requirements for performance, latency, and parallelism. In industrial control applications, real-time requirements are extremely stringent. In such scenarios, FPGA-designed circuits can be optimized for low power consumption and achieve optimal computing power.

[0067] In terms of development difficulty, ARM processor development is relatively simple, while FPGA development is more difficult, with a more complex debugging and verification process. However, in this application, there are many types of expansion modules. Developing with ARM requires configuring and processing different types of module data and channel data, making development more difficult and computationally intensive due to the large volume of data transmission between different types. FPGA, on the other hand, allows for general-purpose development, creating a unified interface without requiring extensive development for different types of modules. Furthermore, FPGA's hardware acceleration capabilities are extremely powerful, providing processing speeds several times or even hundreds of times faster than ARM for certain tasks.

[0068] Regarding the supported I / O capacity, this application uses the E-BUS bus for data interaction with the expansion modules. The handshake mechanism and data transmission protection mechanism of the E-BUS bus can effectively ensure the security and effectiveness of data transmission between modules. In addition, this expansion mode can achieve a data cycle of 250μs when 32 expansion modules are connected.

[0069] The above-described specific examples are for illustrative purposes only and are not intended to limit the scope of this invention. Those skilled in the art to which this invention pertains can make various simple deductions, modifications, or substitutions based on the concept of this invention.

Claims

1. A coupler, characterized by, include: Protocol bus interface, communication processing module, data processing module, and expansion bus interface; The protocol bus interface is used for data interaction with the protocol network; The communication processing module is connected to the protocol bus interface and the data processing module; The communication processing module is used to acquire bus data sent by the protocol bus interface and send the bus data to the data processing module; or, the communication processing module is used to acquire backplane data sent by the data processing module and send the backplane data to the protocol bus interface. The data processing module is communicatively connected to the communication processing module. The data processing module includes an uplink unit and a downlink unit. The input terminal of the uplink unit is connected to the communication processing module, and the output terminal of the uplink unit is connected to the extended bus interface to send the bus data to the extended bus interface. The input terminal of the downlink unit is connected to the extended bus interface, and the output terminal of the downlink unit is connected to the communication processing module to obtain the backplane data sent by the extended bus interface. The extended bus interface is used to connect at least one preset extended module to send the bus data to each extended module.

2. The coupler of claim 1, wherein, The communication processing module further includes a first serial communication unit, and the data processing module further includes a second serial communication unit. One end of the second serial communication unit is connected to the input terminal of the uplink unit and the output terminal of the downlink unit, and the other end of the second serial communication unit is connected to one end of the first serial communication unit.

3. The coupler of claim 1, wherein, The uplink unit includes: A verification circuit, the input of which is connected to the input of the uplink unit, is used to verify the integrity of the bus data; A first data buffer circuit, the input of which is connected to the output of the verification circuit, is used to store and match the bus data in terms of bit width. A filtering circuit, wherein the input terminal of the filtering circuit is connected to the output terminal of the first data buffer circuit, is used to filter the bus data; An encoding circuit, the input of which is connected to the output of the filtering circuit, is used to encode the bus data; A first format conversion circuit, wherein the input of the first format conversion circuit is connected to the encoding circuit and the output of the first format conversion circuit is connected to the extended bus interface, is used to convert the format of the bus data to adapt to the extended bus interface.

4. The coupler of claim 3, wherein, The downlink unit includes: The second format conversion circuit, whose input is connected to the extended bus interface, is used to convert the backplane data to a format suitable for the communication processing module. A decoding circuit, the input of which is connected to the output of the second format conversion circuit, is used to decode the backplane data; A data verification circuit, the input of which is connected to the output of the decoding circuit, is used to perform integrity verification on the backplane data; A second data buffer circuit, an input end of the second data buffer circuit being connected to an output end of the data check circuit, an output end of the second data buffer circuit being connected to an output end of the downstream unit, and the second data buffer circuit being configured to store and match bit widths of the backplane data.

5. The coupler of claim 1, wherein, The communication processing module is further connected with a first crystal oscillator, configured to provide a clock signal for the communication processing module; and / or the data processing module is further connected with a second crystal oscillator, configured to provide a clock signal for the data processing module.

6. The coupler of claim 1, wherein, The communication processing module is further connected with a first reset chip, configured to reset the communication processing module when a fault occurs in the communication processing module; and / or the data processing module is further connected with a second reset chip, configured to reset the data processing module when a fault occurs in the data processing module.

7. The coupler of claim 1, wherein, The communication processing module is further connected with a first expansion peripheral, configured to expand the function of the communication processing module; and / or the data processing module is further connected with a second expansion peripheral, configured to expand the function of the data processing module.

8. The coupler of claim 1, wherein, The expansion bus interface is an E_BUS bus interface.

9. The coupler of claim 1, wherein, The protocol bus interface is a Profinet bus interface, and the protocol network is a Profinet protocol.

10. The coupler of claim 1, wherein, The communication processing module is an ASIC chip, and the data processing module is an FPGA.

Images