Junction box structure, perovskite and crystalline silicon laminated battery assembly and photovoltaic system
By designing a junction box structure with parallel wires in the perovskite and crystalline silicon tandem solar cell module, voltage matching and physical isolation were achieved, solving the problems of high cable cost and low compatibility of four-terminal tandem solar cell modules, reducing cable cost and improving the compatibility and stability of downstream products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2026-03-20
AI Technical Summary
Four-terminal perovskite-crystalline silicon tandem solar cell modules have high cable costs and low compatibility with downstream products due to the use of separate junction boxes.
The design employs a junction box structure, which connects the energy of the perovskite and crystalline silicon tandem solar cell modules in parallel via parallel wires, reducing the number of junction boxes. Two parallel conductive paths, arranged coaxially or side by side, are used to connect the electrodes of the terminals, achieving voltage matching and physical isolation.
It reduces cable costs, improves compatibility with downstream products, and enhances the stability and safety of parallel output.
Smart Images
Figure CN224021689U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to new energy technology field especially relates to a junction box structure, perovskite and crystal silicon laminated battery assembly and photovoltaic system. BACKGROUND
[0002] In photovoltaic cells, four-terminal perovskite-crystal silicon laminated battery assembly has been mass-produced and applied because of simple process (perovskite assembly and crystal silicon assembly only need to be mechanically stacked), but because perovskite assembly and crystal silicon assembly in four-terminal laminated structure need to be independently connected to junction box, cable cost is high and downstream product compatibility is low. SUMMARY
[0003] The utility model discloses at least one of the technical problems existing in the prior art is solved. To this end, the utility model provides a junction box structure, perovskite and crystal silicon laminated battery assembly and photovoltaic system, can realize parallel output, reduce the number of junction box, thereby reduce cable cost and improve the compatibility of downstream product.
[0004] In one aspect, the utility model embodiment provides a junction box structure, is applied to perovskite and crystal silicon laminated battery assembly, the junction box structure includes:
[0005] Junction box;
[0006] Parallel wire, is connected with the junction box, the parallel wire has two conductive paths, and the first end of the two conductive paths is extended to the junction box;
[0007] Terminal, is connected with the parallel wire, and the terminal has first electrode and second electrode, and the first electrode and the second electrode are connected to the second end of the two conductive paths respectively.
[0008] According to some embodiments of the utility model, the two conductive paths are coaxially arranged, and an insulating layer is arranged between the two conductive paths.
[0009] According to some embodiments of the utility model, the first electrode and the second electrode are coaxially arranged.
[0010] According to some embodiments of the utility model, the first electrode and the second electrode are distributed in the axial direction.
[0011] According to some embodiments of the utility model, the two conductive paths are arranged side by side, and an insulating layer is arranged between the two conductive paths.
[0012] According to some embodiments of the utility model, the terminal includes first terminal and second terminal arranged adjacent, the first electrode is arranged in the first terminal, and the second electrode is arranged in the second terminal.
[0013] According to some embodiments of the present invention, the terminal block is a male connector, or the terminal block is a female connector, and the male connector and the female connector are mutually compatible.
[0014] According to some embodiments of this utility model, the two conductive paths of the parallel wire are integrated into one unit.
[0015] On the other hand, this utility model embodiment provides a perovskite and crystalline silicon tandem solar cell module, including the junction box structure described above.
[0016] In another aspect, this utility model provides a photovoltaic system including the above-mentioned perovskite and crystalline silicon tandem cell module.
[0017] The embodiments of this utility model have at least the following beneficial effects:
[0018] The junction box is connected with parallel wires, which have two conductive paths. The two conductive paths are respectively connected to the first electrode and the second electrode of the terminal block. The parallel wires can be used to output the energy of the perovskite-crystalline silicon tandem solar cell module in parallel, reducing the number of junction boxes, thereby reducing cable costs and improving the compatibility of downstream products.
[0019] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0020] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:
[0021] Figure 1 This is a schematic diagram of the stacked structure of a perovskite and crystalline silicon tandem solar cell module according to an embodiment of the present invention.
[0022] Figure 2 This is a schematic diagram of the structure of a perovskite and crystalline silicon tandem solar cell module according to an embodiment of the present invention;
[0023] Figure 3 for Figure 2 A perspective view of the perovskite and crystalline silicon tandem solar cell assembly is shown (one of the junction boxes is hidden).
[0024] Figure 4 for Figure 2 Cross-sectional schematic diagrams of two examples of parallel wires in a perovskite and crystalline silicon tandem solar cell assembly are shown.
[0025] Figure 5 for Figure 2The middle circle shows a local enlarged view of position A;
[0026] Figure 6 For Figure 2 The middle circle shows a local enlarged view of position B;
[0027] Figure 7 For the structure diagram of the terminal of some embodiments of the utility model;
[0028] Figure 8 For Figure 3 The middle circle shows a local enlarged view of position B;
[0029] Figure 9 For Figure 8 The middle circle shows a local enlarged view of position D.
[0030] Reference signs:
[0031] The crystalline silicon cell layer 100, the first positive bus bar 110, the first negative bus bar 120, the perovskite cell layer 200, the second positive bus bar 210, the second negative bus bar 220, the first segment 211, the second segment 212, the third segment 213, the encapsulating material layer 300, the first light-transmitting protective layer 400, the first void hole 401, the second void hole 402, the second light-transmitting protective layer 500, the junction box 600, the parallel wire 610, the first passage 611, the second passage 612, the insulating layer 613, the first electrode 614, the second electrode 615, the first terminal 616, and the second terminal 617. DETAILED DESCRIPTION
[0032] The embodiments of the utility model are described in detail below, examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary, only for explaining the utility model, and cannot be understood as limiting the utility model.
[0033] In the description of the utility model, it is understood that the orientation description, such as up, down, front, back, left, right and the like, is based on the orientation or position relationship shown in the drawings, only for the convenience of describing the utility model and simplifying the description, and cannot be understood as limiting the indicated device or element to have a specific orientation, a specific orientation and operation, therefore, cannot be understood as limiting the utility model.
[0034] In the description of the utility model, the meaning of "several" is one or more, the meaning of "multiple" is two or more, greater than, less than, exceed and the like are understood as not including the number, "above", "below", "within" and the like are understood as including the number. If there is a description to "first", "second" and the like, it is only used for distinguishing technical features for the purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.
[0035] In the description of the utility model, unless otherwise explicitly limited, the words such as "set", "install", "connect" should be broadly understood, and the person skilled in the art can reasonably determine the specific meaning of the above words in the utility model according to the specific content of the technical scheme.
[0036] Solar energy as a clean, renewable energy has been widely concerned. As a key device for converting solar energy into electrical energy, the conversion efficiency and stability of solar cells have always been the focus of research. Perovskite and crystalline silicon cells are two important technologies in the field of solar cells at present. Perovskite cells have the advantages of low cost, high conversion efficiency and flexible preparation, while crystalline silicon cells have mature technology and high stability. By stacking perovskite cells and crystalline silicon cells, the advantages of both can be fully utilized to improve the overall performance of solar cells. However, traditional stacked cells have technical bottlenecks in current matching and process compatibility, which limit their development.
[0037] The wiring structure design of perovskite and crystalline silicon stacked cells is directly related to the efficiency, cost and compatibility with downstream industry chain of the cell module. The current mainstream technology route is two-end stacking and four-end stacking, and the wiring mode, busbar lead-out and junction box quantity of the two are significantly different.
[0038] The core of the structure design of two-end stacked cells is to connect perovskite cells and crystalline silicon cells in series through a tunneling connection layer (compound junction) to form a single circuit output (i.e. one positive and one negative electrode), and its wiring characteristics include:
[0039] 1) Internal series connection: perovskite cell layer and crystalline silicon cell layer are directly connected through a tunneling junction without external wiring, and current transmission is completed inside the stack;
[0040] 2) Simplified electrode: only one layer of transparent conductive electrode (such as TCO, Transparent Conductive Oxide) is needed, avoiding the metal grid design of traditional crystalline silicon cells and reducing light absorption loss;
[0041] 3) No need for laser scribing: the electrode uses a conductive film + grid line process, which is directly integrated with the crystalline silicon substrate, eliminating the P1~P3 laser scribing steps of perovskite single-junction cells.
[0042] In terms of busbars and junction boxes, since the two-end stacked battery outputs single positive and negative poles, the busbars are usually led out from the edges of the assembly, and only one junction box is needed.
[0043] The structural design core of the four-end stacked battery is that the independent perovskite battery layer and the crystalline silicon battery layer are mechanically stacked, the circuits are independent of each other, and the wiring features include:
[0044] 1) Parallel optical coupling: the perovskite battery layer and the crystalline silicon assembly battery layer are only optically coupled (i.e., sharing incident light), the circuits are not directly connected, and external wiring is needed to realize energy output;
[0045] 2) Dual-circuit output: the perovskite battery layer and the crystalline silicon battery layer each have a pair of positive and negative poles, i.e., a total of four poles (two positive and two negative).
[0046] In terms of busbars and junction boxes, since the mechanical stacking process is adopted, the perovskite battery layer and the crystalline silicon battery layer do not need to consider the matching of voltage and current, and only the busbars need to be independently led out, the busbars are arranged up and down along the stacking direction, and are isolated by the packaging material. Due to the need for independent wiring, the amount of cables and junction boxes is significantly higher than that of the two-end stacked battery, leading to an increase in material costs, and the wiring is complex, making it difficult for downstream products to be compatible.
[0047] In terms of application, the two-end stacked battery is compatible with the existing industry chain and has lower cost, and is suitable for large-scale promotion, but the current matching problem needs to be solved; while the four-end stacked battery is easier to realize mass production in the short term due to the simple process (only mechanical stacking), but faces the challenge of industry chain adaptation due to the design of separate wiring and four junction boxes.
[0048] Please refer to Figure 2 , Figure 4 and Figure 5 , the embodiment discloses a junction box structure applied to a perovskite and crystalline silicon stacked battery assembly, the junction box structure includes a junction box 600, parallel wires 610 and junction terminals, the parallel wires 610 are connected with the junction box 600, the parallel wires 610 have two conductive paths, and the first ends of the two conductive paths are extended into the junction box 600; the junction terminals are connected with the parallel wires 610, the junction terminals have first electrodes 614 and second electrodes 615, and the first electrodes 614 and the second electrodes 615 are respectively connected to the second ends of the two conductive paths. The junction box 600 is connected with the parallel wires 610, the parallel wires 610 have two conductive paths, and the two conductive paths are respectively connected to the first electrodes 614 and the second electrodes 615 of the junction terminals. The energy of the perovskite and crystalline silicon stacked battery assembly can be output in parallel by using the parallel wires 610, the number of the junction boxes 600 is reduced, the cable cost is reduced, and the compatibility of downstream products is improved.
[0049] In order to facilitate the understanding of the technical concept of the junction box structure of the present embodiment, the following is described from the perspective of a photovoltaic system. The present embodiment discloses a photovoltaic system comprising a perovskite and crystalline silicon stacked cell assembly, which can reduce the number of junction boxes, thereby reducing the cost of cables and improving the compatibility of downstream products.
[0050] Please refer to Figure 1 , Figure 2 and Figure 3 , the perovskite and crystalline silicon stacked cell assembly comprises a crystalline silicon cell layer 100, a perovskite cell layer 200, an encapsulant layer 300 (such as EVA, Ethylene Vinyl Acetate Copolymer) and a first light-transmitting protective layer 400. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are distributed in a stacked manner and have a mutually matched rated output voltage. The perovskite cell layer 200 and the crystalline silicon cell layer 100 are both provided with positive and negative bus bars, and the bus bars of the same polarity have a safety gap (as shown by mark L in Figure 3 ) on the projection plane in the stacking direction; the encapsulant layer 300 is stacked between the crystalline silicon cell layer 100 and the perovskite cell layer 200; the first light-transmitting protective layer 400 covers the crystalline silicon cell layer 100, and the first light-transmitting protective layer 400 is provided with positive and negative junction boxes 600, the junction boxes 600 are provided with parallel wires 610, and the parallel wires 610 have two conductive paths, which are respectively conductively connected to the bus bars of the same polarity of the crystalline silicon cell layer 100 and the perovskite cell layer 200.
[0051] Exemplarily, the crystalline silicon battery layer 100 is located below the stack of the perovskite battery layer 200, the surface of the perovskite battery layer 200 is covered with the second light-transmissive protective layer 500, the crystalline silicon battery layer 100 and the perovskite battery layer 200 adopt the design concept of four-terminal stack, and the crystalline silicon battery layer 100 and the perovskite battery layer 200 are processed in a mechanical stacking manner, which is simple in process and enables the crystalline silicon battery layer 100 and the perovskite battery layer 200 to have independent positive and negative electrodes, i.e., the crystalline silicon battery layer 100 is provided with the first positive bus bar 110 and the first negative bus bar 120, and the perovskite battery layer 200 is provided with the second positive bus bar 210 and the second negative bus bar 220, which can ensure the working independence of the crystalline silicon battery layer 100 and the perovskite battery layer 200 and eliminate the need to consider the current matching problem. Different from the conventional four-terminal stack battery, the crystalline silicon battery layer 100 and the perovskite battery layer 200 are voltage-matched in the embodiment, i.e., the crystalline silicon battery layer 100 and the perovskite battery layer 200 have mutually matched rated output voltages, and the spatial layout of the bus bars of the same polarity of the crystalline silicon battery layer 100 and the perovskite battery layer 200 is adjusted, i.e., the bus bars of the same polarity have a safety gap on the projection plane in the stack direction, for example, the first positive bus bar 110 and the second positive bus bar 210 have a first safety gap on the projection plane in the stack direction, and the first negative bus bar 120 and the second negative bus bar 220 have a second safety gap on the projection plane in the stack direction. The bus bars of the same polarity are connected and output through the parallel conductive wire 610 of the same junction box 600, wherein the parallel conductive wire 610 has two conductive paths connected in parallel, which can ensure the independence of the outputs of the crystalline silicon battery layer 100 and the perovskite battery layer 200, and the voltage matching design can reduce the voltage difference between the two conductive paths, thereby reducing the potential difference during parallel transmission and avoiding the current loop or power loss caused by voltage imbalance, which is conducive to improving the stability of energy transmission. Moreover, the projection plane of the bus bars of the same polarity in the stack direction is provided with a safety gap, which weakens the electric field coupling and leakage current interference between the conductors through physical isolation, reduces the risk of short circuit, and meets the insulation redundancy requirements under complex conditions such as high humidity and mechanical deformation. The parallel connection of the bus bars of the same polarity of the crystalline silicon battery layer 100 and the perovskite battery layer 200 through the parallel conductive wire 610 with double conductive paths can also reduce the number of junction boxes 600, simplify the processing process, and reduce the cost of cable materials; the integration of the same polarity outputs of the double battery layers through a single junction box 600 reduces the number of connection nodes, avoids the impedance mismatch and thermal failure caused by multiple-point contact, and improves the compatibility of downstream products (such as inverters or energy storage devices).
[0052] To ensure the stability of the double battery layer of the same polarity parallel output, the voltage matching design is needed for the double battery layer. In the embodiment, the perovskite battery layer 200 is divided into multiple battery units based on the scribe division method, and the multiple battery units are connected in series to obtain the rated output voltage matched with the crystalline silicon battery layer 100. It is worth mentioning that the open circuit voltage (Voc) of the perovskite battery layer 200 can be estimated according to the band gap (Eg) of the perovskite material, the temperature (T), the Boltzmann constant (k) and other parameters by using formula (1), wherein ni is the intrinsic carrier concentration, NA and ND are the acceptor and donor impurity concentrations respectively, and q is the basic charge.
[0053] Formula (1):
[0054] The related art optimizes the open circuit voltage of the perovskite battery layer 200 by adjusting the band gap and impurity concentration of the material, thereby increasing the rated output voltage. However, the voltage matching of the two battery layers by adjusting the band gap and impurity concentration of the material has high process requirements. According to formula (1), the open circuit voltage of the solar cell assembly is determined by the material under the condition that the temperature is unchanged, that is, the open circuit voltage is basically unchanged under the condition that the material is determined. For perovskite materials, under the condition that the product area is certain, different rated output voltages can be obtained by dividing into multiple battery units and connecting the multiple battery units in series, for example, assuming that the rated output voltage of the crystalline silicon battery layer 100 is determined as 240V in the design stage, and the material of the perovskite battery layer 200 is perovskite methylammonium lead iodine (MAPbI3) with an open circuit voltage of about 1.2V for a product with an area of 1600*1200mm. The perovskite methylammonium lead iodine battery panel can be laser scribed to divide into 200 battery units, and the 200 battery units are connected in series to form the perovskite battery layer 200, thereby obtaining a rated output voltage of about 240V. It should be noted that the perovskite battery layer 200 and the crystalline silicon battery layer 100 are independent parallel outputs in the embodiment, and a safety gap is provided between the bus bars of the same polarity, so that the voltage matching of the perovskite battery layer 200 and the crystalline silicon battery layer 100 allows a certain range of voltage difference between them, which is beneficial to increase the redundancy of voltage matching and reduce the design difficulty and processing difficulty of voltage matching. In this way, by scribing and cutting and connecting multiple battery units in series, different rated output voltages can be formed, and the voltage matching difficulty of the voltage double battery layer is reduced. In actual processing, scribing and cutting the crystalline silicon battery layer 100 causes greater damage to the photoelectric conversion efficiency of the battery layer, while scribing and cutting the perovskite battery layer 200 has relatively low difficulty and damage to the photoelectric conversion efficiency, so the rated output voltage of the crystalline silicon battery layer 100 is set first in the design stage, and then the perovskite battery layer 200 is scribed and cut for voltage matching. The open circuit voltage reflects the theoretical voltage output capability of the battery, and the output voltage reflects the voltage output of the battery under actual working conditions, and the output voltage is always less than or equal to the open circuit voltage.
[0055] Please refer to Figure 4 The two conductive paths of the parallel wire 610 are coaxially arranged, and the two conductive paths are Figure 4(a) shows a first path 611 and a second path 612. The first path 611 is located radially inside the second path 612, which can effectively reduce the self-inductance and mutual inductance of the parallel conductor 610, reduce battery interference, and solve battery compatibility issues. The coaxial arrangement can also ensure that the current is evenly distributed in the two conductive paths, avoiding local overheating and current congestion, which is beneficial to improving the service life and safety of the conductor. An insulating layer 613 is provided between the two conductive paths, which can control the capacitive effect between the conductors, improve the stability and reliability of transmission, and has good mechanical strength and bending resistance, which is beneficial to improving the durability of the parallel conductor 610. In some other application examples, the two conductive paths of the parallel conductor 610 can be arranged side by side, such as Figure 4 (b) shows a first passage 611 and a second passage 612, with an insulating layer 613 disposed between the first passage 611 and the second passage 612.
[0056] In some application examples, the two conductive paths of the parallel wire 610 are respectively connected to the first electrode 614 and the second electrode 615, and the first electrode 614 and the second electrode 615 are coaxially arranged. Please refer to... Figure 5 , Figure 5 In the terminal block shown, the first electrode 614 is disposed on the inner wall of the terminal block, and the second electrode 615 is located radially inside the first electrode 614, and protrudes from the terminal block relative to the first electrode 614 in the axial direction. Please refer to... Figure 6 , Figure 6 The first electrode 614 in the terminal block shown is disposed on the outer wall of the terminal block, and the second electrode 615 ( Figure 6 Not shown in the image, please refer to the image below. Figure 5 The first electrode 614 is recessed into the terminal block relative to the first electrode 614 in the axial direction. The coaxial arrangement of the first electrode 614 and the second electrode 615 enables parallel output of the dual battery layers, reduces the number of terminals, and improves the compatibility of downstream products.
[0057] In other application examples, please refer to Figure 7 The parallel conductor 610 has two conductive paths connected to adjacent first terminals 616 and 617, respectively. A first electrode 614 is disposed within the first terminal 616, and a second electrode 615 is disposed within the second terminal 617. The first electrode 614 and the second electrode 615 are respectively disposed within the adjacent first terminal 616 and second terminal 617, which increases the safety gap between the first electrode 614 and the second electrode 615 and reduces the risk of short circuits. The two conductive paths within the parallel conductor 610 can be arranged coaxially or side-by-side.
[0058] Please refer to Figure 2 ,Figure 5 and Figure 6 The positive polarity junction box 600 is connected with a junction male head (as shown in the circled position A in Figure 2 ), and the negative polarity junction box 600 is connected with a junction female head (as shown in the circled position B in Figure 2 ), and the junction male head and the junction female head are adapted to each other. For example, Figure 5 the junction terminal shown in Figure 6 is a junction female head, and the first positive bus bar 110 and the second positive bus bar 210 are connected to the junction male head through the corresponding parallel conductive wire 610 of the positive polarity junction box 600, and the first negative bus bar 120 and the second negative bus bar 220 are connected to the junction female head through the corresponding parallel conductive wire 610 of the negative polarity junction box 600. It should be noted that the junction box 600 is not distinguished between positive polarity and negative polarity before assembly, and when the junction box 600 is connected with the positive polarity bus bar, the polarity of the junction box 600 becomes positive, and when the junction box 600 is connected with the negative polarity bus bar, the polarity of the junction box 600 becomes negative. In application, the number of perovskite and crystalline silicon stacked battery assemblies is multiple to form a photovoltaic array, and adjacent perovskite and crystalline silicon stacked battery assemblies can be connected in series through the cooperation of the junction male head and the junction female head.
[0059] The two conductive paths of the parallel conductive wire 610 are integrated, which is conducive to improving the mechanical strength of the parallel conductive wire 610, reducing the number of conductive wires, reducing the wiring complexity in application, keeping the wiring neat and simple, thereby reducing the error rate and cost in the wiring process. At the same time, simplifying the wiring structure is also conducive to improving the reliability and maintainability of use, and reducing the fault points that may occur due to complex wiring.
[0060] Please refer to Figure 3 , Figure 8 and Figure 9The first light-transmitting protective layer 400 is provided with the first avoidance hole 401 and the second avoidance hole 402 arranged adjacently, the first avoidance hole 401 extends to the crystalline silicon cell layer 100, the second avoidance hole 402 penetrates through the encapsulating material layer 300 and extends to the perovskite cell layer 200, the bus bar of the crystalline silicon cell layer 100 is arranged in the first avoidance hole 401, and the bus bar of the perovskite cell layer 200 is arranged in the second avoidance hole 402. The bus bar of the crystalline silicon cell layer 100 and the bus bar of the perovskite cell layer 200 extend to the surface of the first light-transmitting protective layer 400 through the first avoidance hole 401 and the second avoidance hole 402 respectively to enter the junction box 600, the bus bar can be protected through the first light-transmitting protective layer 400 and the encapsulating material layer 300, and the positions of the first avoidance hole 401 and the second avoidance hole 402 are both avoided from the crystalline silicon cell layer 100 and the perovskite cell layer 200, so that the crystalline silicon cell layer 100 and the perovskite cell layer 200 can be prevented from being damaged or blocked, and the photoelectric conversion efficiency of the crystalline silicon cell layer 100 and the perovskite cell layer 200 can be ensured.
[0061] Wherein, please refer to Figure 9 The bus bar of the perovskite cell layer 200 has the first segment 211, the second segment 212 and the third segment 213, the first segment 211 is located in the perovskite cell layer 200, the second segment 212 is located in the second avoidance hole 402, and the third segment 213 is located in the junction box 600, the first segment 211 and the third segment 213 are both located on the same side of the second segment 212 and are both connected with the second segment 212 at an angle. In this way, the first segment 211, the second segment 212 and the third segment 213 can form a 180° bending structure, the spatial distance between the bus bar of the perovskite cell layer 200 and the bus bar of the crystalline silicon cell layer 100 in the stacking direction (as shown by mark H in Figure 9 The bus bar of the perovskite cell layer 200 has the first segment 211, the second segment 212 and the third segment 213, the first segment 211 is located in the perovskite cell layer 200, the second segment 212 is located in the second avoidance hole 402, and the third segment 213 is located in the junction box 600, the first segment 211 and the third segment 213 are both located on the same side of the second segment 212 and are both connected with the second segment 212 at an angle. In this way, the first segment 211, the second segment 212 and the third segment 213 can form a 180° bending structure, the spatial distance between the bus bar of the perovskite cell layer 200 and the bus bar of the crystalline silicon cell layer 100 in the stacking direction (as shown by mark H in
[0062] The above embodiment of the utility model is explained in detail in combination with the drawings, but the utility model is not limited to the above embodiment, and various changes can be made within the knowledge range possessed by ordinary skilled in the art without departing from the purpose of the utility model.
Claims
1. A junction box structure, characterized in that, The junction box structure, used in perovskite and crystalline silicon tandem solar cell modules, includes: Junction box (600); A parallel wire (610) is connected to the junction box (600). The parallel wire (610) has two conductive paths, and the first end of each of the two conductive paths extends into the junction box (600). A terminal block is connected to the parallel wire (610). The terminal block has a first electrode (614) and a second electrode (615). The first electrode (614) and the second electrode (615) are respectively connected to the second end of the two conductive paths.
2. The junction box structure according to claim 1, characterized in that, The two conductive paths are arranged coaxially, and an insulating layer (613) is provided between the two conductive paths.
3. The junction box structure according to claim 1 or 2, characterized in that, The first electrode (614) and the second electrode (615) are coaxially arranged.
4. The junction box structure according to claim 3, characterized in that, The first electrode (614) and the second electrode (615) are offset along the axial direction.
5. The junction box structure according to claim 1, characterized in that, The two conductive paths are arranged side by side, and an insulating layer (613) is provided between the two conductive paths.
6. The junction box structure according to claim 1 or 5, characterized in that, The terminal block includes a first terminal (616) and a second terminal (617) arranged adjacent to each other. The first electrode (614) is disposed in the first terminal (616), and the second electrode (615) is disposed in the second terminal (617).
7. The junction box structure according to claim 1, characterized in that, The terminal block is a male connector, or the terminal block is a female connector, and the male connector and the female connector are compatible with each other.
8. The junction box structure according to claim 1, characterized in that, The two conductive paths of the parallel conductor (610) are integrated into one.
9. A perovskite and crystalline silicon tandem solar cell module, characterized in that, Includes the junction box structure as described in any one of claims 1 to 8.
10. A photovoltaic system, characterized in that, Includes the perovskite and crystalline silicon tandem solar cell module as described in claim 9.