Semiconductor electronic device
By arranging multiple doped portions in the semiconductor body to form an edge termination region, the manufacturing process of MOSFET devices is simplified, manufacturing costs are reduced, and breakdown voltage and electrical performance are maintained or improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-05
- Publication Date
- 2026-03-20
AI Technical Summary
Existing power MOSFET devices require additional photolithography and implantation steps during manufacturing due to the presence of edge termination regions, resulting in high manufacturing costs.
By employing multiple doped portions arranged at certain distances from each other along different directions in the semiconductor body, edge termination regions and deep body regions are formed through alternating epitaxial growth and dopant implantation steps, simplifying the manufacturing process.
This reduces the manufacturing cost of devices while maintaining or improving their breakdown voltage and electrical performance, especially for superjunction MOSFET devices.
Smart Images
Figure CN224022143U_ABST
Abstract
Description
[0001] Priority Application
[0002] This application claims priority from Italian patent application No. 102024000004948 filed on March 6, 2024, the contents of which are incorporated herein by reference in its entirety to the maximum extent permitted by law. TECHNICAL FIELD
[0003] The present utility model relates to a semiconductor electronic device, and in particular to a vertical conduction device with an edge termination region. BACKGROUND
[0004] As is known, semiconductor electronic devices used in power applications, such as MOSFET transistors, need to withstand high voltages, for example even higher than 400 V.
[0005] In power supply applications, high breakdown voltage and low on-resistance are parameters required to improve the electrical performance of electronic devices.
[0006] Figure 1 A silicon-based MOSFET device 1 for power applications is shown in a Cartesian reference system XYZ.
[0007] The MOSFET device 1 is a vertical conduction device and has a super-junction type structure (based on the principle of charge compensation) which allows the MOSFET device 1 to overcome the classic limits of silicon, i.e. to obtain a good trade-off between high breakdown voltage and low on-resistance.
[0008] The MOSFET device 1 is formed in a die including an active region 2 and an edge region 3.
[0009] The MOSFET device 1 comprises a semiconductor body 4 made of silicon, having a front surface 4A and a back surface 4B, and having an N-type doping. The semiconductor body 4 comprises a substrate 6 and an epitaxial region 8 grown on the substrate 6.
[0010] Figure 1 Only one component of the active region 2 is shown, which is configured to house, in use, a conduction channel of the MOSFET device 1.
[0011] The edge region 3 extends around the active region 2 in a peripheral portion of the die between the active region 2 and an outer edge 10 of the semiconductor body 4.
[0012] The MOSFET device 1 comprises, in the active region 2, a plurality of surface body regions 11 having a P-type doping, which extend inside the epitaxial region 8 along the Z axis from the front surface 4A.
[0013] The surface body regions 11 extend at a distance from each other along the X axis.
[0014] The source regions 12 with N-type doping each extend inside the respective surface body region 11.
[0015] The deep body regions 13 with P-type doping extend along the Z axis deep into the epitaxial region 8, each starting from a respective surface body region 11. The presence of the deep body regions 13 defines a super-junction structure of the MOSFET device 1.
[0016] The insulating regions 15 extend onto the front surface 4A of the semiconductor body 4, and the gate insulating regions 16 are arranged inside the insulating regions 15, above the front surface 4A.
[0017] Each gate insulating region 16 is arranged between two adjacent surface body regions 11, partially covering the surface body regions 11.
[0018] The conductive regions 18 extend into the openings of the insulating regions 15, in contact with the source regions 12.
[0019] The edge region 3 comprises an edge termination region 20 with P-type doping, which extends at the surface of the epitaxial region 8, starting from the front surface 4A, and has an annular shape surrounding the active area 2. The edge termination region 20 extends continuously along the X axis from the active area 2 to the outer edge 10. The width of the edge termination region 20 along the X axis is between 50 pm and 200 pm.
[0020] The MOSFET device 1 further has an equipotential ring 21 with N-type doping, which extends at the surface of the epitaxial region 8 at the outer edge 10 of the semiconductor body 4, and a conductive region 22, which extends onto the front surface 4A in contact with the equipotential ring 21.
[0021] The super-junction structure allows to obtain a high breakdown voltage of the MOSFET device 1, for example up to 1000 V and above. The presence of the annular region 20 contributes to increase the breakdown voltage of the MOSFET device 1.
[0022] However, the presence of the annular region 20 requires additional manufacturing steps (lithography, implantation and diffusion) with respect to the manufacturing steps that cause the formation of the surface 11 and deep 13 body regions. Therefore, the MOSFET device 1 has a high manufacturing cost.
[0023] Figure 2 Another example of a MOSFET device 50 is shown, also a vertically conductive and super-junction type device. The MOSFET device 50 has the same structure as the MOSFET device 1 of Figure 1 ; therefore, the common elements are indicated by the same reference numerals.
[0024] In the MOSFET device 50, the edge region 3 further comprises a further edge termination region forming a plurality of pillars 51 having a P-type doping, which pillars extend in depth into the semiconductor body 4 starting from the front surface 4A.
[0025] The pillars 51 extend continuously along the Z-axis, from the front surface 4A through the ring region 20 and the epitaxial region 8.
[0026] However, the MOSFET device 50 also has a high manufacturing cost.
[0027] There is a need in the art to provide a power MOSFET overcoming the above-mentioned drawbacks. SUMMARY
[0028] In one embodiment, a semiconductor electronic device comprises: a semiconductor body having a first conductivity type, a front surface, and a back surface extending at a distance from the front surface in a first direction, the semiconductor body further having a lateral edge; an active region configured to comprise a conductive channel of the semiconductor electronic device; and an edge termination region extending around the active region between the active region and the lateral edge of the semiconductor body in a second direction transverse to the first direction; wherein the edge termination region comprises a plurality of doped portions having a second conductivity type different from the first conductivity type and arranged at a distance from each other in the semiconductor body in the first direction or in the first and second directions.
[0029] In one embodiment, the plurality of doped portions comprises surface doped portions extending into the semiconductor body starting from the front surface, wherein the surface doped portions are spaced at a distance from each other in the second direction.
[0030] In one embodiment, the plurality of doped portions comprises deep doped portions extending into the semiconductor body at a distance from the front surface, and wherein the deep doped portions are spaced at a distance from each other in the second and first directions.
[0031] In one embodiment, the plurality of doped portions comprises deep doped portions extending into the semiconductor body at a distance from the front surface, and wherein the deep doped portions are spaced at a distance from each other in the first direction.
[0032] In one embodiment, the doped portions face each other and are aligned with each other in the first direction.
[0033] In one embodiment, the doped portions at least partially face each other in the first direction.
[0034] In one embodiment, the edge termination region has a uniform density of doped portions.
[0035] In one embodiment, the edge termination region has a non-uniform density of doped portions.
[0036] In one embodiment, the edge termination region has a first density of doped portion near the active region and a second density of doped portion near the lateral edge of the semiconductor body, which is greater than the first density.
[0037] In one embodiment, the edge termination region has a doped density that increases from the active region toward the lateral edge along a second direction.
[0038] In one embodiment, the edge termination region has a doped density that increases from the front surface toward the rear surface along a first direction.
[0039] In one embodiment, the edge termination region has a width along a second direction, which decreases along a first direction from the front surface toward the rear surface.
[0040] In one embodiment, each doped portion has a width along the second direction, which is between 1 μm and 10 μm.
[0041] In one embodiment, the device is a vertically conductive MOSFET device.
[0042] In one embodiment, the device is a superjunction MOSFET device having at least one deep body region extending along a first direction at a distance from the front surface into the active region.
[0043] This invention provides a semiconductor electronic device that overcomes the above-mentioned shortcomings. Attached Figure Description
[0044] To better understand this invention, embodiments thereof will now be described by way of non-limiting example with reference to the accompanying drawings, in which:
[0045] Figure 1 A cross-section of a MOSFET device is shown;
[0046] Figure 2 A cross-section of another MOSFET device is shown;
[0047] Figure 3 A top view of a semiconductor electronic device according to one embodiment is shown;
[0048] Figure 4 It shows Figure 3 The device along Figure 3 The cross section of section line IV-IV;
[0049] Figures 5A-5G This shows the subsequent manufacturing steps. Figure 4 Devices;
[0050] Figure 6 and Figure 7 a cross-section of a semiconductor electronic device is shown, according to other embodiments; and
[0051] Figure 8 and Figure 9 a top view of a semiconductor electronic device is shown, according to further embodiments. DETAILED DESCRIPTION
[0052] Figure 3 and Figure 4 a semiconductor electronic device, hereinafter simply device 100, in a Cartesian reference system XYZ having axes X, Y, Z orthogonal to each other, in a Cartesian reference system XYZ having axes X, Y, Z orthogonal to each other, is shown.
[0053] The device 100 is a silicon-based semiconductor device; however, the device 100 can be a semiconductor device based on different materials, such as silicon carbide or other simple or compound semiconductor materials.
[0054] The device 100 is formed as a die 101, which can be obtained after a dicing step of a semiconductor wafer.
[0055] The die 101 comprises an edge 102 physically delimiting the die 101. In fact, the edge 102 is a lateral edge laterally delimiting the die 101.
[0056] The device 100 comprises an active area 103 and an edge region 104 extending around the active area 103.
[0057] In particular, the edge region 104 structurally extends in continuity with the active area 103.
[0058] Typically, the active area 103 can extend to a central portion of the die 101, as well as to an edge region of a peripheral portion of the die 101.
[0059] In fact, the edge region 104 extends between the active area 103 and the edge 102 of the die 101, and is externally delimited by the edge 102.
[0060] The active area 103 is configured to house, in use, a conductive channel of the device 100.
[0061] The edge region 104 can comprise functional elements for reducing or preventing crowding of electric field lines outside the active area 103, which will be better described and illustrated hereinafter with reference to Figure 4 In fact, the edge region 104 is configured to not house, in use, a conductive channel of the device 100.
[0062] As Figure 4In cross-section, the device 100 can be a MOSFET device, in particular a vertically conducting MOSFET device, even more particularly a super-junction MOSFET device.
[0063] The device 100 can be an electronic device for power applications, in particular for high voltages, e.g. higher than 400 V.
[0064] Figure 4 Only a portion of the active region 103 is shown, in particular a portion of the active region 103 close to the edge region 104. The dotted line separating the active region 103 from the edge region 104 is to be understood as qualitative.
[0065] The device 100 comprises a semiconductor body 110, in particular of silicon or silicon carbide or other semiconductor material, having an N-type doping, and having a front surface 110A and a back surface 110B at a distance from each other along the Z-axis.
[0066] The front surface 110A forms a front side of the semiconductor body 110 and bounds it upwardly. The back surface 110B forms a back side of the semiconductor body 110 and bounds it downwardly.
[0067] In fact, the front surface 110A and the back surface 110B are opposite each other along the Z-axis.
[0068] The semiconductor body 110 further has a lateral edge extending from the active region 103 at a distance along the X- and Y-axes. In fact, the lateral edge can physically bound the semiconductor body 110, e.g. in a plane transverse to the front surface 110A and the back surface 110B. The lateral edge of the semiconductor body 110 can coincide with the edge 102 of the die 101, and is therefore indicated with the same reference sign in the following.
[0069] In the shown embodiment, the semiconductor body 110 comprises a substrate 111 and a structural region 112 extending onto the substrate 111. For example, the structural region 112 can be epitaxially grown on the substrate 111; therefore, in the following, the structural region 112 is also referred to as epitaxial region 112.
[0070] The epitaxial region 112 forms a drift region of the device 100 in the active region 103.
[0071] The substrate 111 and the epitaxial region 112 can be of the same semiconductor material, and have the same conductivity type (here, N-type).
[0072] The substrate 111 can have a higher doping level than the epitaxial region 112.
[0073] The device 100 comprises, in the active region 103, surface body regions 115 having a P-type doping; deep body regions 116 having a P-type doping; source regions 117 having an N-type doping; and gate regions 118.
[0074] For simplicity, in the following Figure 4 , only two surface body regions 115, two deep body regions 116, two source regions 117 and two gate regions 118 are shown. However, it is clear that the device 100 can comprise further surface body regions 115, deep body regions 116, source regions 117 and gate regions 118 in the active region 103.
[0075] The surface body regions 115 extend from the front surface 110A into the semiconductor body 110, in particular into the epitaxial region 112, at a distance from each other along the X-axis.
[0076] The source regions 117 extend at least partially inside the respective surface body regions 115.
[0077] The deep body regions 116 extend deeply into the semiconductor body 110, in particular into the epitaxial region 112, along the Z-axis, each from a respective surface body region 115.
[0078] The deep body regions 116 extend from the front surface 110A at a distance, in direct contact with the surface body regions 115.
[0079] In practice, the deep body regions 116 extend into the semiconductor body 110 at a depth (measured along the Z-axis from the front surface 110A) greater than the depth (measured along the Z-axis from the front surface 110A) of the surface body regions 115.
[0080] The width (along the X-axis in the cross-section of Figure 4 ) of the deep body regions 116 can be less than the width (along the X-axis in the cross-section of Figure 4 ) of the surface body regions 115.
[0081] The gate regions 118 comprise a gate insulating portion 119 and a gate conductive portion 120, and extend onto the front surface 110A partially covering the surface body regions 115 along the Z-axis.
[0082] A drain region, not shown here, of conductive material extends at the back surface 110B, forming a drain terminal D of the device 100.
[0083] In practice, in use, the surface body regions 115 are configured to host a conductive channel of the device 100, so as to form, between the front surface 110A and the back surface 110B, a conductive path extending through the semiconductor body 110 along the Z-axis, as Figure 4The dashed arrows are shown in an exemplary and illustrative manner.
[0084] The insulating region 123 extends onto the front surface 110A of the semiconductor body 110, for example, in both the active region 103 and the edge region 104.
[0085] The conductive region 124 extends onto the semiconductor body 110 and makes electrical contact with the source region 117. In fact, the conductive region 124 is the source contact region and forms the source terminal S of the device 100. For example, the conductive region 124 may extend through an opening in the insulating region 123, through the thickness of the insulating region 123, and reach the front surface 110A.
[0086] The conductive region 124 can be used for different sections of the device 100, for example, not shown here, and also contacts the surface body region 115 to achieve a body-source short circuit.
[0087] Device 100 includes an edge termination region 130 in edge region 104, which extends within semiconductor body 110 surrounding active region 103.
[0088] The edge termination region 130 includes a plurality of pits 132 with P-type doping that extend into the semiconductor body 110, particularly within the epitaxial region 112.
[0089] The edge termination region 130 may have a width W t The width is along the direction extending between the active area and the lateral edge 102. Figure 4 The width W is measured along the X-axis of the cross-section, for example, between 50 μm and 200 μm. t A larger value can be useful for device 100 that can operate at high voltage.
[0090] In fact, the width W t It can be defined as the width occupied by the recess 132 inside the semiconductor body 110 between the active region 103 and the lateral edge 102, for example, the maximum width.
[0091] To maximize the breakdown voltage, the cavity 132 can have, for example, a voltage of 5 × 10⁻⁶. 15 at / cm 3 With 5×10 17 at / cm 3 The doping levels between them.
[0092] The recesses 132 extend at a certain distance from each other along the Z-axis. For example, the distance W between two adjacent recesses 132 along the Z-axis is... v It can be between 3μm and 8μm.
[0093] The cavities 132 also extend along the X axis at a distance from each other. For example, the distance W between two adjacent cavities 132 along the X axis is comprised between 2 pm and 6 pm. h It can be comprised between 2 pm and 6 pm.
[0094] The cavities 132 can each have a width W along the X axis comprised between 1 pm and 10 pm. p For example, it is comprised between 2 pm and 6 pm.
[0095] In this embodiment, the cavities 132 are distributed in the semiconductor body 110 so that the edge termination region 130 has, at least as a first approximation (i.e. except for process variability), a uniform P-type cavity density (number of cavities per unit area or unit volume) inside the width W t In fact, at least as a first approximation (that is, except for process variability), the cavities 132 are all arranged along the X axis at the same mutual distance W h and along the Z axis at the same mutual distance W v and have, at least as a first approximation, the same width W p .
[0096] In detail, the plurality of cavities 132 comprises surface cavities 132A extending into the semiconductor body 110 at the front surface 110A, and deep (or buried) cavities 132B extending into the semiconductor body 110 at a distance from the front surface 110A.
[0097] The surface cavities 132A extend from the front surface 110A towards the inside of the semiconductor body 110, in particular towards the inside of the epitaxial region 112.
[0098] The surface cavities 132A extend along the X axis at a distance from each other. In particular, at least as a first approximation (i.e. except for process variability), the surface cavities 132A are all extended along the X axis at the same distance from each other.
[0099] The deep cavities 132B extend into the semiconductor body 110, in particular into the epitaxial region 112, at a distance from the front surface 110A of the semiconductor body 110.
[0100] The deep cavities 132B extend along the X axis and along the Z axis at a distance from each other.
[0101] In this embodiment, the deep cavities 132B are arranged in groups extending along the Z axis, each group being located underneath a respective surface cavity 132A.
[0102] In particular, in the example of Figure 4 four deep cavities 132B are arranged underneath each surface cavity 132A.
[0103] In detail, in the embodiment of Figure 4 the deep recesses 132B are aligned with each other along the Z axis and are also aligned with the respective surface recesses 132A along the Z axis. However, the recesses 132 can be wholly or partially facing each other along the Z axis.
[0104] The fact that the deep recesses 132B are uniformly distributed, in particular having the same mutual distance W h along the X axis and the same mutual distance W v along the Z axis, can ensure a simpler design and manufacture of the device 100.
[0105] As shown in Figure 3 the surface recesses 132A extend continuously around the active region 103. In other words, the surface recesses 132A have a substantially circular shape and form a plurality of concentric rings that completely surround the active region 103.
[0106] In a plan view (for example, on a plane parallel to the XY plane), the deep recesses 132B can have the same or different shape with respect to the surface recesses 132A.
[0107] According to one embodiment, the deep recesses 132B (all of them or only some of them) can also extend continuously around the active region 103; this can allow the device 100 to obtain a high breakdown voltage in use.
[0108] The presence of the surface recesses 132A can be considered optional, where the device comprises only deep recesses 132B spaced apart from the surface 110A and located around the active region 103.
[0109] The device 100 can optionally comprise an end region 140 arranged in the edge region 104 at the outer edge 102.
[0110] The end region 140 comprises a doped region 141 having N-type doping, which extends into the semiconductor body 110 at the front surface 110A; and a conductive region 142, which extends onto the front surface 110A in electrical contact with the doped region 141. The end region 140 can have the function of forming an equipotential ring with the drain terminal of the device 100 on the outer edge 102 of the die 101.
[0111] The inventors have verified that the plurality of recesses 132 forming the edge termination region 130 are distanced from each other along the Z axis, which in use allows a high breakdown voltage of the device 100 and therefore excellent electrical performance.
[0112] In particular, the fact that the recesses 132 extend from the front surface 110A into the semiconductor body 110 with a high depth, for example between 20 pm and 80 pm, can ensure that the breakdown voltage of the device 100 is further increased.
[0113] Moreover, the inventors have verified that the recesses 132 extend along the X axis at a distance from each other along the X axis, which contributes to increasing the electrical robustness of the device 100 in use. For example, the device 100 can have a high breakdown voltage higher than or equal to 1000 V in use.
[0114] Moreover, the fact that the recesses 132 extend at a distance from each other along the X axis also allows to reduce the manufacturing costs of the device 100, in particular if the device 100 is a super-junction MOSFET device. In fact, as discussed below with reference to Figures 5A-5G In detail, the distance along the X axis allows to avoid using additional masks to form the annular regions extending continuously along the X axis, instead of what discussed for the known devices 1 and 50. Figure 1 and Figure 2 .
[0115] In the following, reference is made to Figures 5A to 5G , reference is made to the cross-section shown in Figure 4 , which shows the manufacturing steps of the device 100.
[0116] In Figure 5A , a silicon wafer 200 is provided, having a front surface 200A and a back surface 200B opposite to the front surface 200A parallel to the Z axis; alternatively, the wafer 200 can be of a different semiconductor material, for example silicon carbide or other simple or compound semiconductor material.
[0117] The wafer 200 comprises a substrate, again indicated by 111, on which an epitaxial layer 201 has been grown.
[0118] The epitaxial layer 201 and the substrate 111 are of the same material (silicon); however, they can be made of different materials.
[0119] The epitaxial layer 201 and the substrate 111 have the same conductivity type, here with N-type doping.
[0120] The epitaxial layer 201 forms the front surface 200A of the wafer 200.
[0121] Moreover, a doped portion 203 with P-type doping has been formed in the wafer 200, which will form the deep body region 116, and a P-type doped portion, again indicated by 132B, which will form the deepest row of the deep recesses 132B.
[0122] For example, the doped portion 203, 132B can be formed by implanting a P-type dopant into the epitaxial layer 201, for example by using a photomask to selectively implant the P-type dopant into the desired regions.
[0123] Subsequently, as shown in Figure 5B , an epitaxial layer 205 is grown on the epitaxial layer 201. The epitaxial layer 205 has the same material as the epitaxial layer 201 (here, silicon); however, it can be a different material.
[0124] The epitaxial layer 205 forms a new front surface of the wafer 200, again indicated by 200A for simplicity. For clarity, in Figure 5B , a dashed line separates the epitaxial layer 205 from the epitaxial layer 201.
[0125] In Figure 5C , a doped portion 207 is formed in the epitaxial layer 205, above and in contact with the doped portion 203. For example, the doped portion 207 can be formed by implanting a P-type dopant into the epitaxial layer 205, for example by using a photomask to selectively implant the P-type dopant into the desired regions.
[0126] In Figure 5D , an epitaxial layer 209 is grown on the front surface 200A, on the epitaxial layer 205.
[0127] The epitaxial layer 209 has the same material as the epitaxial layer 205 (here, silicon); however, it can be a different material.
[0128] The epitaxial layer 209 forms a new front surface of the wafer 200, again indicated by 200A for simplicity. For clarity, in Figure 5D , a dashed line separates the epitaxial layer 205 from the epitaxial layer 209.
[0129] In Figure 5E , a doped portion 211 with P-type doping is formed in the epitaxial layer 209, above and in contact with the doped portion 207. In addition, a P-type doped portion is also formed in the epitaxial layer 209, which will form another row of deep pits 132B, and is therefore again indicated by 132B.
[0130] For example, the doped portion 211, 132B can be formed by implanting a P-type dopant into the epitaxial layer 209, for example by using a photomask to selectively implant the P-type dopant into the desired regions.
[0131] In Figure 5FIn this configuration, epitaxial layer 213 is grown on the front surface 200A, above epitaxial layer 209. Epitaxial layer 213 has the same material as epitaxial layer 209 (here, silicon); however, it can be a different material.
[0132] Epitaxial layer 213 forms the new front surface of wafer 200, again designated 200A for simplicity. For clarity, in... Figure 5F In the middle, the dashed line separates epitaxial layer 213 from epitaxial layer 209.
[0133] exist Figure 5F After its growth, it has been referenced Figures 5C to 5E The described content is repeated sequentially until the surface recess 132A of the edge termination region 130 and the deep body region 116 is formed. Figure 5G ).
[0134] In addition, Figure 5G In this process, continuous epitaxial layers grown on top of each other form the epitaxial region 112 of the device 100.
[0135] In fact, the recess 132 and the deep bulk region 116 can be formed simultaneously through alternating epitaxial growth steps and dopant implantation steps.
[0136] Figures 5C to 5E The steps are repeated multiple times, depending on the desired thickness of the epitaxial region 112, the desired thickness of the deep body region 116, and the desired number of recesses 132 in the edge termination region 130.
[0137] One or more annealing steps can be performed to activate the cavities 132A, 132B and the deep body region 116.
[0138] Subsequently, a reference can be formed in a manner not shown here. Figure 4 The remaining regions of the device 100 described include the surface body region 115, the source region 117, and the gate region 117118.
[0139] Finally, the next steps are manufacturing processes known in themselves, such as dicing the wafer 200 and forming electrical contacts, thereby forming the device 100.
[0140] The described manufacturing process allows for a reduction in the manufacturing cost of device 100, particularly when device 100 is a MOSFET device with a superjunction structure. In fact, the recess 132 of the edge termination region 130 can be formed using the same mask and the same implantation steps used to form the deep body region 116, without the need for additional dedicated photolithography and implantation steps.
[0141] In addition, with Figure 1 and Figure 2The described process can also have reduced complexity and execution time compared to the manufacturing process of known devices.
[0142] Figure 6 Different embodiments of the present electronic device are shown, here indicated with 300. The electronic device 300 has a general structure similar to that of the device 100; therefore, common elements are indicated with the same reference numerals and are not described in detail again.
[0143] The device 300 is also a super-junction type vertical conduction MOSFET device.
[0144] In detail, the device 300 comprises a semiconductor body 110 and has, in the active region 103, a surface body region 115, a deep body region 116, a source region 117 and a gate region 118.
[0145] The device 300 comprises, in the edge region 104, an edge termination region 330 which extends inside the semiconductor body 110 around the active region 103.
[0146] Here, the edge termination region 330 also comprises a plurality of pockets 332 of conductive type (P) opposite to the conductive type (N) of the semiconductor body 110, including surface pockets 332A and deep pockets 332B which extend into the semiconductor body 110, in particular inside the epitaxial region 112.
[0147] The edge termination region 330 can have a width W t .
[0148] In a plan view parallel to the XY plane, around the active region 103, the pockets 332 can have the same trends as discussed with reference to the pockets 132 of the device 100. For example, the pockets 332 can each have a circular shape around the active region 103, in particular forming concentric circles with each other. Figure 3
[0149] The pockets 332 can have a variable pitch and width at the surface, compared to what has been shown and described for the device 100.
[0150] The pockets 332 are distributed in the semiconductor body 110 in such a way that the edge termination region 330 has a non-uniform P-type pocket density (number of pockets per unit area or unit volume) within the width W t .
[0151] In detail, the recesses 332 can have an increasing density moving parallel to the X axis from the active region 103 towards the outer edge 102 of the die 101. For example, the width of the recesses 332 and / or the distance along the X axis between two adjacent recesses 332 can have a decreasing trend moving parallel to the X axis from the active region 103 and towards the outer edge 102.
[0152] For example, as shown in Figure 6 the two adjacent recesses 332 along the x axis can be arranged at a distance W' h at a distance W" h at a distance W"' h near the edge 102, wherein W"' h < W" h < W' h .
[0153] For example, the distance W' h may be comprised between 3 pm and 8 pm. For example, the distance W" h may be comprised between 1 pm and 6 pm.
[0154] The edge termination region 330 allows the device 300 to have a high breakdown voltage in use.
[0155] In particular, the fact that the density of the recesses 332 is not uniform in the edge termination region 330, even more in particular greater further from the active region 103, can ensure high electrical performances.
[0156] Figure 7 A further embodiment of the electronic device is shown, indicated here with 400. The electronic device 400 has a general structure similar to that of the device 100; therefore, common elements are indicated with the same reference numerals and are not described in detail again.
[0157] The device 400 is also a super-junction type vertical conduction MOSFET device.
[0158] In detail, the device 400 comprises, in the active region 103, a surface body region 115, a deep body region 116, a source region 117 and a gate region 118.
[0159] The device 400 comprises, in the edge region 104, an edge termination region 430 which extends inside the semiconductor body 110 around the active region 103.
[0160] The edge termination region 430 comprises a plurality of recesses 432 extending into the semiconductor body 110, here also of the opposite conductivity type (with P-type doping) with respect to the conductivity type of the semiconductor body 110 (with N-type doping).
[0161] In a plan view parallel to the XY plane, the recesses 432 surrounding the active region 103 can have the same tendencies as discussed for the recesses 132 of the reference Figure 3 device, e.g. so that each recess forms a circle surrounding the active region 103. The circles formed by the recesses 332B of each row can here also be concentric to each other.
[0162] In detail, the plurality of recesses 432 comprises surface recesses 432A extending at the front surface 110A, and deep recesses 432B extending at a distance from the front surface 110A.
[0163] The edge termination region 430 has a width measured along a direction extending between the active region 103 and the outer edge 102 (X-axis in Figure 7 ), which is variable as a function of the depth in the semiconductor body 110. In particular, the width decreases along the Z-axis from the front surface 110A towards the back surface 110B.
[0164] In detail, at the front surface 110A, the surface recesses 432A define an upper width W t,f of the edge termination region 430, for example comprised between 50 pm and 200 pm.
[0165] The deep recesses 432B define a back width W t,b of the edge termination region 430, for example between 30 pm and 120 pm, at the depth of the epitaxial region 112.
[0166] The upper width W t,f is greater than the back width W t,b ; in particular, the upper width W t,f defines a maximum width of the edge termination region 430, and the back width W t,b defines a minimum width of the edge termination region 430.
[0167] Further, the recesses 432 can be arranged so that the edge termination region 430 has a non-uniform density of recesses 432, for example greater at greater depths from the front surface 110A within the epitaxial region 112. This can ensure a high breakdown voltage of the device 400 in use.
[0168] For example, moving from the front surface 110A parallel to the Z-axis towards the back surface 110B, the recesses 432 can have a decreasing width measured along the X-axis.
[0169] The electrical simulations carried out by the Applicant have verified that the tendency to reduce the width of the edge termination region 430 can contribute to ensuring, in use, excellent electrical performances of the device 400.
[0170] In fact, with reference to the devices 100, 300, 400, the respective edge termination regions 130, 330, 430 are formed by a plurality of recesses 132, 332, 432 having a different conductivity type from the conductivity type of the semiconductor body 110 and arranged at a distance from each other along the Z axis or both along the Z axis and along the X axis, this fact confers a high design versatility to the edge termination regions. Therefore, the present electronic devices can be suitable for a plurality of applications.
[0171] It is also clear to the person skilled in the art, with reference to the devices 100, 300, 400, that the recesses 132, 332, 432 can be arranged in a continuous manner around the active region 103. Figures 5A to 5G The manufacturing steps described can be suitable for the manufacture of the devices 300, 400.
[0172] Figure 8 and Figure 9 Other embodiments of the present semiconductor electronic device are shown, respectively indicated by 500 and 600.
[0173] The devices 500 and 600 comprise, in the edge region 104 around the active region, an edge termination region having P-type recesses (indicated by 502 and 602, respectively).
[0174] The distribution of the recesses 502, 602 in the semiconductor body 110 can be equal to or different from the distribution discussed for the recesses 132( Figure 4 ), 332( Figure 6 ) and 432( Figure 7 ).
[0175] In particular, the devices 500 and 600 differ from the device 100 of Figure 3 and Figure 4 in the distribution of the recesses 502, 602 around the active region 103.
[0176] In detail, in the devices 500 and 600, the recesses 502, 602 extend discontinuously around the active region 103, thus forming a plurality of portions separated from each other.
[0177] The discontinuous distribution of the recesses 502 or 602 around the active region 103 can simplify the design steps of the devices 500 and 600, in particular the design steps of the photolithographic masks.
[0178] Finally, it is clear that modifications and changes can be made to the semiconductor electronic devices described and shown herein and to the manufacturing processes thereof, without departing from the scope of the present utility model, as defined in the appended claims.
[0179] For example, the surface recesses and / or the deep recesses of the edge termination region can be (all or only some) floating or have a dedicated area for biasing to a specific potential. In particular, the surface recesses and the deep recesses can be (for example, all) floating; in this case, the actual potential of the recesses can be determined in the design step by appropriate dimensions as a function of the specific application. Moreover, the use of floating recesses makes the manufacturing of the device simpler.
[0180] For example, the edge termination region can have a different number and distribution of recesses than described.
[0181] For example, the deep body region and / or the doped recesses of the edge termination region can be manufactured, instead of or in addition to the subsequent steps of epitaxial growth and dopant implantation, by forming a trench in the wafer 200 and filling the trench with doped semiconductor material.
[0182] For example, the gate region 118 can be of the trench type (i.e., extending into the semiconductor body 110 along the Z axis).
[0183] For example, depending on the specific application of the semiconductor electronic device, the active area 103 can also accommodate elementary cells of devices other than MOSFETs.
[0184] For example, the utility model is also applicable to semiconductor electronic devices other than super-junction vertical-conducting MOSFETs, for example, lateral-conducting MOSFETs, vertical-conducting MOSFETs and non-super-junction types, or devices other than MOSFETs, for example, trench FETs, diodes, triodes, MESFETs, MISFETs, IGBTs, etc.
[0185] The conductivity types P and N can be opposite to those discussed above. For example, the semiconductor body can be P-type, while the recesses of the edge termination region can be N-type.
[0186] Finally, the different embodiments described and shown above can be combined to provide further solutions.
Claims
1. A semiconductor electronic device, comprising: A semiconductor body has a first conductivity type, a front surface, and a rear surface extending at a certain distance from the front surface along a first direction; the semiconductor body also has a lateral edge. The active region is configured to include a conductive channel of the semiconductor electronic device; as well as An edge termination region extends around the active region between the active region and the lateral edge of the semiconductor body along a second direction transverse to the first direction; The edge termination region includes multiple doped portions having a second conductivity type different from the first conductivity type, and are arranged in the semiconductor body at a certain distance from each other along the first direction or along both the first and second directions.
2. The semiconductor electronic device according to claim 1, characterized in that, The plurality of doped portions include surface doped portions extending from the front surface into the semiconductor body, wherein the surface doped portions are spaced apart from each other along the second direction.
3. The semiconductor electronic device according to claim 1, characterized in that, The plurality of doped portions include deeply doped portions extending into the semiconductor body at a certain distance from the front surface, wherein the deeply doped portions are spaced apart from each other along the second direction and the first direction.
4. The semiconductor electronic device according to claim 1, characterized in that, The plurality of doped portions include deeply doped portions extending into the semiconductor body at a distance from the front surface, and wherein the deeply doped portions are spaced apart from each other along the first direction.
5. The semiconductor electronic device according to claim 1, characterized in that, The doped portions face each other and are aligned with each other along the first direction.
6. The semiconductor electronic device according to claim 1, characterized in that, The doped portions at least partially face each other along the first direction.
7. The semiconductor electronic device according to claim 1, characterized in that, The edge termination region has a doped portion with a uniform density.
8. The semiconductor electronic device according to claim 1, characterized in that, The edge termination region has a doped portion with uneven density.
9. The semiconductor electronic device according to claim 8, characterized in that, The edge termination region has a first density of doped portion near the active region, and a second density of doped portion near the lateral edge of the semiconductor body, which is greater than the first density.
10. The semiconductor electronic device according to claim 1, characterized in that, The edge termination region has a doping density that increases from the active region toward the lateral edge along the second direction.
11. The semiconductor electronic device according to claim 1, characterized in that, The edge termination region has a doped density that increases from the front surface toward the rear surface along the first direction.
12. The semiconductor electronic device according to claim 1, characterized in that, The edge termination region has a width along the second direction, which decreases along the first direction from the front surface toward the rear surface.
13. The semiconductor electronic device according to claim 1, characterized in that, Each of the doped portions has a width along the second direction, the width being between 1 μm and 10 μm.
14. The semiconductor electronic device according to claim 1, characterized in that, The device is a vertically conductive MOSFET device.
15. The semiconductor electronic device according to claim 1, characterized in that, The device is a superjunction MOSFET device, which has at least one deep body region that extends along the first direction at a distance from the front surface into the active region.