Resource board card and testing machine
By introducing a main control module and a group operation module into the resource board, parallel register configuration of multiple peripheral modules was achieved, solving the problem of low communication efficiency in traditional test machines and improving test efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-03-24
AI Technical Summary
In traditional semiconductor test machines, the communication efficiency of resource boards is low, resulting in a long time consumption for register configuration.
The design employs a main control module and a group operation module. By sending configuration data to peripheral modules in parallel, and using group identification information to obtain channel indicator flags from pre-stored cached data, parallel register configuration of multiple peripheral modules is achieved.
It improves test communication efficiency, reduces register configuration time, and enhances test efficiency.
Smart Images
Figure CN224035551U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor testing, in particular to a resource board card and a test machine. BACKGROUND
[0002] Semiconductor automatic testing refers to detecting various parameter indexes of a chip by using an automatic test equipment (ATE) to remove defective products to control the quality of semiconductor products. Before chip testing, due to the PMU (precision measurement unit) function of the test machine, a large number of channels need to be configured with registers and read the registers repeatedly. In the traditional test machine, the registers of each channel are configured in series, and the host computer software side needs to send commands and wait for feedback from the resource board card, which has the disadvantage of low communication efficiency. CONTENT OF THE UTILITY MODEL
[0003] Therefore, it is necessary to provide a resource board card and a test machine that can improve communication efficiency in view of the above problems.
[0004] The first aspect of the present application provides a resource board card, comprising:
[0005] a main board card configured to receive a downlink message and send the downlink message to a sub-board card;
[0006] at least one sub-board card, comprising a master control module and a group operation module, the master control module being connected to the main board card and the group operation module, and the group operation module being connected to a peripheral module;
[0007] When the instruction type carried in the downlink message is a peripheral instruction, the master control module sends the downlink message to the group operation module, the group operation module analyzes the downlink message to obtain group identification information and configuration data, acquires corresponding channel indication flags from pre-stored group operation identification cache data based on the group identification information, and sends the configuration data to the corresponding peripheral module in parallel according to the channel indication flags for register configuration.
[0008] In one embodiment, the peripheral module comprises a PE chip; the group operation module comprises a peripheral data cache analysis unit, a group identification cache unit and a group operation unit, the peripheral data cache analysis unit being connected to the master control module and the group operation unit, and the group operation unit being connected to the group identification cache unit and the peripheral module;
[0009] The peripheral device data buffer analysis unit analyzes the downlink message to obtain group identification information and configuration data, and sends the group identification information to the group operation unit; the group operation unit obtains a corresponding channel indication flag from group operation identification buffer data stored in the group identification buffer unit based on the group identification information; and the group operation unit simultaneously sends configuration data to each PE chip in parallel according to the channel indication flag.
[0010] In one of the embodiments, the PE chip is provided with a group channel register, and the group operation unit further generates a channel number register value according to the channel indication flag and sends the channel number register value to the group channel register in the corresponding PE chip; and the PE chip performs channel data configuration in parallel according to the received configuration data and the channel number register value stored in the internal group channel register.
[0011] In one of the embodiments, the host module is further connected to the group identification buffer unit, and receives group operation identification buffer data sent by the mainboard card and stores the group operation identification buffer data in the group identification buffer unit.
[0012] In one of the embodiments, the peripheral device data buffer analysis unit is further connected to each peripheral module; and the peripheral device data buffer analysis unit serially sends configuration data to the corresponding peripheral module when it is determined that the current operation is a single read-write operation.
[0013] In one of the embodiments, the host module is a PFGA, an MCU or a CPU.
[0014] In one of the embodiments, the resource board card further comprises a communication module, and the mainboard card is connected to the host module in the subboard card through the communication module.
[0015] In one of the embodiments, the resource board card further comprises a peripheral module connected to the group operation module, and the peripheral module comprises at least one of a PE chip, an ADC, a DAC and a storage chip.
[0016] The second aspect of the present application provides a test machine comprising a communication board card and the above-mentioned resource board card.
[0017] In one of the embodiments, the test machine further comprises a host computer, and the host computer is connected to the mainboard card through the communication board card and sends a downlink message to the mainboard card.
[0018] The resource board card and the test machine, in the sub-board card of the resource board card, the main control module is connected with the main board card and the group operation module, and the group operation module is connected with the peripheral module. When the instruction type carried by the downlink message is a peripheral instruction, the main control module sends the downlink message to the group operation module, the group operation module analyzes the downlink message to obtain group identification information and configuration data, and based on the group identification information, the corresponding channel indication flag is obtained from the pre-stored group operation identification cache data, and the configuration data is sent to the corresponding peripheral module in parallel according to the channel indication flag for register configuration. After the group operation identification cache data is set in advance, the group operation can be performed according to the group identification information in the downlink message, and the configuration data is sent to the corresponding peripheral module in parallel for register configuration. The register configuration operation of multiple peripheral modules can be performed at the same time, the communication time is reduced, and the test communication efficiency is improved. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 It is a structural block diagram of the resource board card in an embodiment.
[0020] Figure 2 It is a structural schematic diagram of the resource board card in an embodiment. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0023] It can be understood that, in the following embodiments, “connection” between the circuits, modules, units, etc. connected with each other should be understood as “electrical connection”, “communication connection” and the like if there is an electrical signal or data transmission between the circuits, modules, units, etc.
[0024] As used herein, the singular forms “a”, “an” and “the” can include plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise / contain” or “have” or the like specify the presence of stated features, integers, operations, components, parts or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, operations, components, parts or combinations thereof.
[0025] In one embodiment, as Figure 1As shown, a resource board card is provided, including a main board card 100 and at least one sub-board card 200, the main board card 100 receives a downlink message and sends it to the sub-board card 200; the sub-board card 200 includes a master control module 220 and a group operation module 240, the master control module 220 is connected to the main board card 110 and the group operation module 240, and the group operation module 240 is connected to the peripheral module. When the master control module 220 is in the type of instruction carried by the downlink message is a peripheral instruction, the downlink message is sent to the group operation module 240, the group operation module 240 parses the downlink message to obtain group identification information (Group ID) and configuration data, and based on the group identification information, the corresponding channel indication flag is obtained from the pre-stored group operation identification cache data, and the configuration data is sent to the corresponding peripheral module according to the channel indication identification for register configuration in parallel.
[0026] Specifically, the number of sub-board cards 200 can be one or more, the main board card 100 is connected to the master control module 220 in each sub-board card 200, and the main board card 100 is connected to the host computer through the communication board card, or can be directly connected to the host computer, receives the downlink message and forwards it to the sub-board card 200. In addition, the resource board card further includes a communication module 300, and the main board card 100 is connected to the master control module 220 in the sub-board card 200 through the communication module 300, and the master control module 220 can be PFGA, MCU or CPU, etc. The resource board card further includes a peripheral module connected to the group operation module 240, and the type and number of peripheral modules are not unique, such as Figure 2 As shown, the peripheral module can include a PE (Pin Electronics Driver / Comparator, pin circuit) chip provided with a PMU, and can also include an ADC, a DAC, and a storage chip (such as a FLASH chip), etc.
[0027] The group operation identification cache data representing the correspondence between the group identification information and the channel indication flag can be generated by the host computer software before the chip test is performed, and the group operation identification cache data is communicated with the resource board card through the Dbus bus, and is then sent to the main board card 100, and then sent to the group operation module 240 by the host control module 220 for storage. In actual test data read / write operation, the host computer executes the test item according to the parameters input by the test personnel, obtains the test pin, generates the group identification information based on the correspondence between the test pin and the test channel, fills the corresponding group identification information (Group ID) as the Group bit field of the Dbus message, fills the board card type to be operated, selects the corresponding register address, and fills the instruction type, encapsulates the message according to the Dbus broadcast message protocol format to generate the downlink message, and transmits the downlink message to the resource board card through the Dbus bus. Those skilled in the art can know that the board card type corresponding to different test channels can be different, so the board card type is part of the downlink message, and the downlink message is transmitted to each resource board card. In this embodiment, the host computer software is the host computer software and the driver software.
[0028] It can be understood that in other embodiments, the host computer can also send the group operation identification cache data and the downlink message to the resource board card simultaneously during actual test data read / write operation. The group operation module 240 can directly obtain the corresponding channel indication flag from the group operation identification cache data according to the group identification information after analyzing the downlink message to obtain the group identification information and the configuration data, and then sends the configuration data to the corresponding peripheral module for register configuration in parallel. The group operation identification cache data can also be stored in the internal cache unit of the group operation module 240, and the group operation module 240 extracts the corresponding channel indication flag from the internal cache unit according to the group identification information, and sends the configuration data to the corresponding peripheral module for register configuration in parallel. By using the internal cache unit to store the group operation identification cache data, it is convenient to perform register configuration on the peripheral module according to the downlink message sent by the host computer in the future.
[0029] In the resource board card, the main board card 100 receives the downlink message and transmits it to the sub-board card 200. The main control module 220 of the sub-board card 200 analyzes the instruction type carried in the downlink message. If it is a peripheral instruction, the downlink message is sent to the group operation module 240. If it is not a peripheral instruction, it means that the downlink data is not configuration data sent to the peripheral module, and the main control module 220 can perform local data configuration processing according to the downlink message. The group operation module 240 analyzes whether the group operation or single read-write operation needs to be executed after receiving the downlink message, for example, parses the downlink message. If the group identification information is included in the downlink message, it means that the group operation needs to be executed. Based on the group identification information, the corresponding channel indication flag is obtained from the pre-stored group operation identification cache data, and the configuration data is sent to the corresponding peripheral module for register configuration in parallel according to the channel indication flag. Since the register parameters of different peripheral module channels may be the same, the registers of the peripheral module can be configured in parallel through the group operation, which can reduce the register parameter transmission time, thereby reducing the transmission times of the same data and improving the test efficiency.
[0030] In one embodiment, as shown in Figure 2 The group operation module 240 includes a peripheral data cache analysis unit 242, a group identification cache unit 244, and a group operation unit 246. The peripheral data cache analysis unit 242 is connected to the main control module 220 and the group operation unit 246. The group operation unit 246 is connected to the group identification cache unit 244 and the peripheral module. Taking the PE chip with a built-in PMU as an example, the peripheral data cache analysis unit 242 analyzes the downlink message to obtain the group identification information and configuration data and sends it to the group operation unit 246. The group operation unit 246 obtains the corresponding channel indication flag from the group operation identification cache data stored in the group identification cache unit 244 based on the group identification information. The group operation unit 246 simultaneously sends the configuration data to each PE chip in parallel according to the channel indication flag.
[0031] In this process, after determining that the instruction type carried in the downlink message is a peripheral instruction, the main control module 220 further checks whether the channel configuration of the PE chip is consistent with the previous channel configuration. If the channel used remains unchanged, it directly sends the downlink message to the peripheral data cache parsing unit 242 to perform channel configuration operations. If the channel used has changed, it first configures the corresponding channel valid register of the PE chip, and then sends the downlink message to the group identifier cache unit 244 to perform channel configuration operations. Furthermore, the main control module 220 is also connected to the group identifier cache unit 244, receiving group operation identifier cache data sent by the motherboard card 100 and storing it in the group identifier cache unit 244. Similarly, before chip testing, the main control module 220 can store the group operation identifier cache data sent by the host computer into the group identifier cache unit 244, or during actual data read / write operations, the main control module 220 can receive the group operation identifier cache data and downlink message synchronously sent by the host computer and store the group operation identifier cache data into the group identifier cache unit 244. If the main control module 220 determines that the channel configuration of the PE chip is the same as the previous channel configuration based on the group identifier information (Group ID), it directly sends a download message to the peripheral data cache parsing unit 242. If the main control module 220 determines that the channel configuration of the PE chip is different from the previous channel configuration, it configures the group operation identifier cache data in the group identifier cache unit 244, and then sends a download message to the peripheral data cache parsing unit 242.
[0032] In addition, the peripheral data cache parsing unit 242 is also connected to various peripheral modules, such as PE chips, DACs, and FLASH chips. When the peripheral data cache parsing unit 242 determines that the current operation is a single read / write operation, it serially sends the configuration data to the corresponding peripheral module.
[0033] Specifically, such as Figure 2 As shown, before chip testing, the main control module 220 receives group operation identifier cache data and data storage address from the host computer, and stores the group operation identifier cache data into the corresponding address in the group identifier cache unit 244 according to the data storage address. The group operation identifier cache data includes multiple group identifier information, such as Group ID 0, Group ID 1, etc. Each group identifier information corresponds to several bits of data (e.g., 32 bits). Each bit represents whether the corresponding channel of the PE chip needs to be configured. For example, the least significant bit in the 32 bits corresponds to channel 0, the most significant bit corresponds to channel 31, and when the bit is a specific indicator (e.g., 1), it means that the channel needs to be configured.
[0034] In actual chip testing, when the master module 220 receives the downlink message, it is determined whether the current instruction is a peripheral instruction. If so, whether it is a group operation or a single read-write instruction, the downlink message is distributed to the peripheral data buffer analysis unit 242. The peripheral data buffer analysis unit 242 determines whether it is a single read-write operation (non-Group instruction) or not. If so, the peripheral data buffer analysis unit 242 sends configuration data to each peripheral module in turn, and serially configures the related peripheral registers. If it is a group operation (Group instruction), the group operation unit 246 first reads the channel indication flag from the group identification buffer unit 244 according to the group identification information, and according to the read channel identification, it can be known which channels in the PE chip need to be configured, and then the configuration data is simultaneously sent to the corresponding registers in the PE chip, realizing the parallel configuration of multiple PE chips and improving the data configuration efficiency.
[0035] Further, the group channel register is arranged in the PE chip, and the group operation unit 246 also generates the channel number register value according to the channel indication flag and sends it to the group channel register in the corresponding PE chip; the PE chip performs channel data configuration in parallel according to the received configuration data and the channel number register value stored in the internal group channel register, realizes the parallel configuration of multiple channels in the PE chip, and further improves the data configuration efficiency.
[0036] Among them, the group operation unit 246 judges according to the channel indication flag (32bit data). Specifically, one sub-board card includes 4 PE chips, each PE chip includes 8 test channels, and the channel numbers of each test channel are 0-7, 8-15, 16-23, and 24-31. Then, in the channel indication flag (32bit), if there is a bit with a specific mark (such as 1), it means that the channel corresponding to the bit with the specific mark needs to be configured, and then based on the specific mark, the PE chip where the channel to be configured is located can be determined. If only one channel needs to be configured in each PE, the configuration data can be directly sent to multiple PE chips in parallel. If the number of channels to be configured in one PE chip is greater than 1, first generate the channel number register value and send it to the internal group channel register of the corresponding PE chip, and then send the configuration data to each PE chip in parallel. Based on the group channel register, each PE chip configures multiple channels in parallel. In other embodiments, if only one channel needs to be configured, the number of valid channels in each PE chip can also be determined, and the channel number register value is directly generated and sent to the group channel register of the corresponding PE chip, and then the data is configured in parallel.
[0037] In one embodiment, a test machine is also provided, comprising the communication board card and the resource board card described above. The test machine further comprises a host computer, which is connected with the main board card through the communication board card and sends the downlink message to the main board card. The host computer can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices, and the portable wearable device can be a smart watch, a smart bracelet, a head-mounted device, etc.
[0038] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure as long as the combination does not result in contradictions.
[0039] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the utility model patent. It should be noted that, for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A resource board card, characterized by, include: The motherboard card receives downlink messages and sends them to the daughterboard card. At least one of the sub-boards includes a main control module and a group operation module, wherein the main control module is connected to the motherboard and the group operation module, and the group operation module is connected to a peripheral module; When the instruction type carried in the downlink message is a peripheral instruction, the main control module sends the downlink message to the group operation module. The group operation module parses the downlink message to obtain group identification information and configuration data. Based on the group identification information, it retrieves the corresponding channel indicator flag from the pre-stored group operation indicator cache data. According to the channel indicator flag, it sends the configuration data to the corresponding peripheral module in parallel for register configuration.
2. The resource board card of claim 1, wherein, The peripheral module includes a PE chip; the group operation module includes a peripheral data cache parsing unit, a group identifier cache unit, and a group operation unit. The peripheral data cache parsing unit is connected to the main control module and the group operation unit, and the group operation unit is connected to the group identifier cache unit and the peripheral module. The peripheral data cache parsing unit parses the downlink message to obtain group identifier information and configuration data, and sends them to the group operation unit. The group operation unit obtains the corresponding channel indicator flag from the group operation identifier cache data stored in the group identifier cache unit based on the group identifier information. The group operation unit simultaneously sends configuration data to each PE chip in parallel according to the channel indicator flag.
3. The resource board card of claim 2, wherein, The PE chip is equipped with a group channel register. The group operation unit also generates a channel quantity register value according to the channel indicator flag and sends it to the group channel register in the corresponding PE chip. The PE chip performs channel data configuration in parallel according to the received configuration data and the channel quantity register value stored in the internal group channel register.
4. The resource board card of claim 2, wherein, The main control module is also connected to the group identifier cache unit, and receives group operation identifier cache data sent by the motherboard card and stores it in the group identifier cache unit.
5. The resource board card of claim 2, wherein, The peripheral data cache parsing unit is also connected to each peripheral module; when the peripheral data cache parsing unit determines that the current operation is a single read / write operation, it serially sends the configuration data to the corresponding peripheral module.
6. The resource board card of any of claims 1-5, wherein, The main control module is a PFGA, MCU, or CPU.
7. The resource board card of any of claims 1-5, wherein, It also includes a communication module, through which the motherboard card is connected to the main control module in the sub-board.
8. The resource board card of any of claims 1-5, wherein, It also includes a peripheral module connected to the group operation module, the peripheral module including at least one of a PE chip, an ADC, a DAC and a memory chip.
9. A testing machine characterized by, It includes communication boards and resource boards as described in any one of claims 1-8.
10. The testing machine of claim 9, wherein, It also includes a host computer, which is connected to the motherboard card through the communication board and sends downlink messages to the motherboard card.