Impedance multiplication structure
By setting parallel resistors and impedance adjustment electrodes on the chip resistor, combined with laser truncation technology, a 10-fold adjustment of the total impedance value was achieved, solving the problems of resistance value deviation and insufficient heat dissipation, and improving the applicability and stability of the chip resistor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-03-24
AI Technical Summary
Traditional chip resistors have resistance value deviations during the manufacturing process, and the methods for repairing resistance are limited, resulting in a small range for increasing resistance value and insufficient heat dissipation performance.
By employing an impedance multiplication structure, multiple resistors and impedance adjustment electrodes are set on the substrate and connected in parallel. Combined with laser cutting to adjust the total impedance value, the total impedance value can be adjusted by 10 times while also taking into account heat dissipation performance.
It enables rapid adjustment of the total impedance value of the chip resistor, expands the adjustment range by 10 times, improves heat dissipation efficiency and stability, solves the problems of concentrated current heating and melting, and expands the scope of application.
Smart Images
Figure CN224036169U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a chip resistor, especially to an impedance multiplication structure for a chip resistor. BACKGROUND
[0002] Chip resistors have the advantages of small size, easy installation and mass production, and are widely used in small devices such as consumer electronic products. In the production process of chip resistors, there will be slight resistance value deviation between chip resistors of the same batch, and further resistance adjustment is needed to ensure that each chip resistor reaches the target resistance value.
[0003] The traditional resistance adjustment method is to cut the resistance to increase the resistance value by cutting length, or to use materials with different resistance coefficients to increase the resistance value. However, the longer the cutting length, the worse the power bearing effect, and the range of resistance value increase is also very limited. SUMMARY
[0004] In view of the above problems, the utility model provides an impedance multiplication structure and a manufacturing method thereof, which can adjust the total impedance of the chip resistor to increase by a multiple, so that the total impedance value approaches the target value, and the adjustment range of the total impedance of the chip resistor is increased to 10 n times, and the heat dissipation performance of the chip resistor is also considered.
[0005] The utility model provides a kind of impedance multiplication structure, it includes:
[0006] A substrate;
[0007] A first outer electrode and a second outer electrode are respectively arranged on both sides of a first surface of the substrate;
[0008] A plurality of surface resistors are arranged on the first surface of the substrate and are spaced apart from each other, the plurality of surface resistors are attached to the first outer electrode, and the plurality of surface resistors have a distance from the second outer electrode;And
[0009] A plurality of impedance adjustment electrodes are respectively arranged between the second outer electrode and the plurality of surface resistors;
[0010] Wherein the impedance multiplication structure adjusts the total impedance value of the impedance multiplication structure by cutting off at least one of the plurality of impedance adjustment electrodes.
[0011] Preferably, the impedance multiplication structure further comprises: a third outer electrode and a fourth outer electrode, respectively arranged on both sides of the second surface of the substrate.
[0012] Preferably, the impedance multiplication structure further comprises a back resistance, the back resistance is disposed on the second surface of the substrate, the back resistance connects the third external electrode and the fourth external electrode.
[0013] Preferably, the impedance multiplication structure further comprises a first side electrode and a second side electrode, the first side electrode connects the first external electrode and the third external electrode, the second side electrode connects the second external electrode and the fourth external electrode.
[0014] Preferably, the plurality of surface resistances have resistance values that differ by 10 times or more from each other, and a resistance value of the back resistance is 10 times or more of a maximum value among the plurality of surface resistances.
[0015] Preferably, the impedance multiplication structure further comprises an inner protective layer, the inner protective layer is disposed on the plurality of surface resistances and the plurality of impedance adjustment electrodes, and exposes the first external electrode and the second external electrode.
[0016] Preferably, the inner protective layer is a transparent glass protective layer.
[0017] Preferably, the impedance multiplication structure further comprises an outer protective layer, the outer protective layer is disposed on the inner protective layer, the third external electrode, the fourth external electrode and the back resistance, and exposes the plurality of impedance adjustment electrodes.
[0018] Preferably, the outer protective layer is an insulating ink protective layer. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 is a top view of the impedance multiplication structure of the utility model;
[0020] Figure 2 is a bottom view of the impedance multiplication structure of the utility model;
[0021] Figure 3 is Figures 1-2 is a sectional view of the impedance multiplication structure of the utility model along the line A-A';
[0022] Figures 4A-4H is a schematic diagram of the manufacturing method of the impedance multiplication structure of the utility model;
[0023] Figure 5 is a flow chart of the manufacturing method of the impedance multiplication structure of the utility model.
[0024]
Explanation of reference signs
[0025] 1, impedance multiplication structure; 10, substrate; 11, first surface; 12, second surface; 21, first outer electrode; 22, second outer electrode; 23, third outer electrode; 24, fourth outer electrode; 30, surface resistance; 40, impedance adjustment electrode; 41, first impedance adjustment electrode; 42, second impedance adjustment electrode; 43, third impedance adjustment electrode; 50, inner protective layer; 60, outer protective layer; 81, first side electrode; 82, second side electrode; A-A', line; D1, first distance; D2, second distance; R1, first surface resistance; R2, second surface resistance; R3, third surface resistance; R4, back resistance. DETAILED DESCRIPTION
[0026] The following embodiments are used to illustrate the spirit of the present application, so that those skilled in the art can clearly understand the technology of the present application, but are not used to limit the scope of the present application, and the scope of the patent right of the present application should be defined by the claims. It is particularly emphasized that the drawings are only for illustration and do not represent the actual size or quantity of the components, and some details may not be completely drawn in order to simplify the drawings.
[0027] For the sake of simplicity, a rectangular resistor is taken as an example, but it should be understood that it is used for illustration and not for limitation of the present application. The resistor of the present application can be implemented in any shape.
[0028] Please refer to Figures 1-3 , Figure 1 is a top view of the impedance multiplication structure of the present application, Figure 2 is a bottom view of the impedance multiplication structure of the present application, Figure 3 is Figures 1-2 a sectional view of the impedance multiplication structure of
[0029] The present application provides an impedance multiplication structure 1, which comprises a substrate 10, a first outer electrode 21, a second outer electrode 22, a surface resistance 30, an impedance adjustment electrode 40, a third outer electrode 23, a fourth outer electrode 24, a back resistance R4, a first side electrode 81, a second side electrode 82, an inner protective layer 50 and an outer protective layer 60, so as to adjust the total impedance of the chip resistance to increase by a multiple, so that the total impedance value tends to approach the target value, and the adjustment range of the total impedance of the chip resistance is increased to 10 n times, and at the same time, the heat dissipation performance of the chip resistance is also considered.
[0030] Please refer to Figures 4A-5 , Figures 4A-4H is a schematic diagram of the manufacturing method of the impedance multiplication structure of the present application, Figure 5 is a flow chart of the manufacturing method of the impedance multiplication structure of the present application.
[0031] The manufacturing method of the impedance multiplication structure 1 of this utility model is as follows:
[0032] Step S100: Set a substrate 10, the material of which can be alumina.
[0033] Step S101, as follows Figure 4A As shown, the first external electrode 21 and the second external electrode 22 are printed on both sides of the first surface 11 of the substrate 10, and the third external electrode 23 and the fourth external electrode 24 are printed on both sides of the second surface 12 of the substrate 10, forming electrode patterns respectively. The size and position of the third external electrode 23 and the fourth external electrode 24 can correspond to or be aligned with the first external electrode 21 and the second external electrode 22 respectively.
[0034] The materials of the first external electrode 21, the second external electrode 22, the third external electrode 23 and the fourth external electrode 24 are conductive inks. The conductive inks can be nickel-copper paste, pure copper paste, silver-palladium paste, pure silver paste, platinum paste or combinations thereof.
[0035] Step S102, as follows Figure 4B As shown, a plurality of resistors 30 are printed on the first surface 11 of the substrate 10 and arranged parallel to or spaced apart from each other. The plurality of resistors 30 are attached to the first external electrode 21. The plurality of resistors 30 and the second external electrode 22 have a first distance D1. The length of the first distance D1 can be 5% to 30% of the length of the resistor. Then the plurality of resistors 30 are baked and hardened. The plurality of resistors 30 can be printed and baked and hardened one by one, or printed and baked and hardened simultaneously.
[0036] For ease of explanation, the diagram uses three resistors 30 as an example. The number of resistors 30 can be two or more, such as three, four, five, six, ..., i, and so on. The specific number can be adjusted according to the substrate size and resistor size, preferably three to five.
[0037] The resistance values of a plurality of meter resistors 30 can be the same or different, and the resistance values of the plurality of meter resistors 30 can differ from each other by 1 to 10. n The ratio is 10 times, preferably 10 times. n The resistance values of the complex number of meters are: R1 < R2 < R3, and so on. For example, if R1 is 10Ω, then R2 is 100Ω and R3 is 1000Ω.
[0038] The materials of the plurality of meter resistors 30 can be the same or different resistor pastes. The materials of the plurality of meter resistors 30 can be nickel copper paste, silver palladium paste, palladium / silver oxide, ruthenium dioxide, Bi2Ru2O7, Pb2Ru2O6 or combinations thereof.
[0039] Step S103, as shown in Figure 4C The plurality of impedance adjustment electrodes 40 are printed between the second outer electrode 22 and the plurality of surface resistors 30, to electrically connect the second outer electrode 22 and the plurality of surface resistors 30.
[0040] The length of the plurality of impedance adjustment electrodes 40 can be equal to or greater than the first distance D1, the width of the plurality of impedance adjustment electrodes 40 can be equal to or less than the width of the plurality of surface resistors 30, preferably, the width of the plurality of impedance adjustment electrodes 40 is 50% to 120% of the width of the plurality of surface resistors 30.
[0041] The number of the plurality of impedance adjustment electrodes 40 corresponds to the number of the plurality of surface resistors 30, which can be 2 or more, for example, 3, 4, 5, 6, …, i, and so on, and the specific number can be adjusted according to the size of the substrate and the size of the resistor, preferably 3 to 5. For the sake of understanding, Figure 4C Taking 3 as an example, that is, the first impedance adjustment electrode 41, the second impedance adjustment electrode 42 and the third impedance adjustment electrode 43, the utility model is not limited to this.
[0042] The material of the plurality of impedance adjustment electrodes 40 can be the same or different conductive ink, the material of the plurality of impedance adjustment electrodes 40 can be the same material as the first surface electrode and / or the second surface electrode, the material of the plurality of impedance adjustment electrodes 40 can be nickel copper paste, pure copper paste, silver palladium paste, pure silver paste, platinum gold paste or a combination thereof.
[0043] Step S104, as shown in Figure 4D The inner protective layer 50 is printed on the plurality of surface resistors 30 and the plurality of impedance adjustment electrodes 40, and the first outer electrode 21 and the second outer electrode 22 are exposed.
[0044] The inner protective layer 50 is transparent glass protective ink, which can be silicon dioxide, silicon dioxide or a combination thereof.
[0045] Step S105, as shown in Figure 4E The back resistor R4 is printed on the second surface 12 of the substrate 10, and the back resistor R4 is electrically connected to the third outer electrode 23 and the fourth outer electrode 24.
[0046] The resistance value of the back resistor R4 can be 1 to 10 m times greater than the maximum value of the resistance value of the plurality of surface resistors 30, preferably 10 mThe resistance value of the back resistor R4 is 10000Ω, for example, if the first surface resistor R1 is 10Ω, the second surface resistor R2 is 100Ω, and the third surface resistor R3 is 1000Ω.
[0047] The material of the back resistor R4 can be the same or different from the material of the plurality of surface resistors 30, and the material of the back resistor R4 can be palladium / silver oxide, ruthenium dioxide, Bi2Ru2O7, Pb2Ru2O6, or a combination thereof.
[0048] As shown in FIG. 1, the inner protective layer 50 is printed on the plurality of surface resistors 30, the first outer electrode 21, the second outer electrode 22, the third outer electrode 23, and the fourth outer electrode 24. Figure 4F As shown in FIG. 1, the inner protective layer 50 is printed on the plurality of surface resistors 30, the first outer electrode 21, the second outer electrode 22, the third outer electrode 23, and the fourth outer electrode 24.
[0049] The outer protective layer 60 exposes the plurality of impedance adjustment electrodes 40 at a second distance D2, which can be equal to or less than the first distance D1, and the length of the second distance D2 can be 50% to 100% of the length of the first distance D1.
[0050] The outer protective layer 60 is an insulating ink, and preferably the insulating ink is black, and the insulating ink can be an epoxy resin.
[0051] As shown in FIG. 1, the inner protective layer 50 is printed on the plurality of surface resistors 30, the first outer electrode 21, the second outer electrode 22, the third outer electrode 23, and the fourth outer electrode 24.
[0052] The material of the first side electrode 81 and the second side electrode 82 can be the same or different, and the material of the plurality of first side electrodes 81 and the second side electrodes 82 can be nickel-chromium, nickel, or tin.
[0053] As shown in FIG. 1, the inner protective layer 50 is printed on the plurality of surface resistors 30, the first outer electrode 21, the second outer electrode 22, the third outer electrode 23, and the fourth outer electrode 24. Figure 4H As shown in FIG. 1, the inner protective layer 50 is printed on the plurality of surface resistors 30, the first outer electrode 21, the second outer electrode 22, the third outer electrode 23, and the fourth outer electrode 24. x The total resistance value of the chip resistor can be adjusted in the range of 1 to 10 Figure 4H For the purpose of illustration, one of the plurality of impedance adjustment electrodes 40 is truncated, but the present application is not limited thereto.
[0054] The inner protective layer 50 can be penetrated by laser, and the conduction path of the specific impedance adjustment electrode 40 is cut off to select the impedance value generated by the chip resistor of the utility model, and the surface resistance 30 of the cut-off conduction path cannot provide parallel connection, but can still be used as a heat dissipation layer of the whole chip resistor to improve the heat dissipation performance.
[0055] The resistance multiplication structure of the utility model forms multiple parallel resistors on the first surface 11 and the second surface 12 of the chip resistor, and the total impedance value tends to be equal to the minimum value of the multiple parallel resistors 30 and the back resistor R4, as shown in mathematical formula 1.
[0056] [mathematical formula 1]
[0057]
[0058] wherein, R total is the total impedance value of the chip resistor, R1-Ri is the resistance value of the i-th resistor, and i is a positive integer of 2-6.
[0059] For example, when the first surface resistor R1 is 10Ω, the second surface resistor R2 is 100Ω, the third surface resistor R3 is 1000Ω, and the back resistor R4 is 10000Ω, the conduction path of the specific impedance adjustment electrode 40 is cut off to make the adjustable range of the total impedance value of the chip resistor be 9-10 4 Ω, and there are five kinds of impedance values that can be selected, that is, about (i-1)!+1 kinds of impedance values, and the difference between each impedance value selection can reach 10 times.
[0060] [Table 1]
[0061]
[0062] Therefore, the resistance multiplication structure of the chip resistor of the utility model can quickly adjust the total impedance value by 10 times, and the cut-off resistor can be converted into a cooling fin to improve the heat dissipation efficiency under high power operation, improve the application range and stability of the chip resistor, so the resistance multiplication structure of the utility model has a synergistic effect, and also solves the technical bottleneck of the past current concentration in the traditional laser resistance adjustment area and heating and fusing, has the benefits of easy production and quality durability. In addition, since the total resistance value can be formed by cutting at least one impedance adjustment electrode, a chip resistor product can be cut according to the resistance value of the corresponding impedance adjustment electrode according to the circuit demand, so as to realize various circuit system requirements, and reduce the space of the circuit and the number of resistance bodies used.
[0063] The printing, baking hardening, vacuum sputtering and laser cutting processes used in the utility model can be performed by using the existing technology to achieve the same effect, and the utility model is not described in detail in order to make the description concise.
[0064] The expression "tends to" used in the present utility model means "substantially equal to" and "about", and indicates that two values are equal or approximately equal, and can indicate values within a range of ±1-10% of each other.
Claims
1. An impedance multiplication structure, characterized in that, It includes: One substrate; A first external electrode and a second external electrode are respectively disposed on both sides of a first surface of the substrate; A plurality of resistors are disposed on the first surface of the substrate and spaced apart from each other. The plurality of resistors are attached to the first external electrode, and a distance is maintained between the plurality of resistors and the second external electrode. A plurality of impedance adjustment electrodes are respectively disposed between the second external electrode and the plurality of meter resistors; The impedance multiplier structure adjusts the total impedance value of the impedance multiplier structure by cutting off at least one of the plurality of impedance adjustment electrodes.
2. The impedance multiplication structure according to claim 1, characterized in that, It further includes: a third external electrode and a fourth external electrode, respectively disposed on both sides of a second surface of the substrate.
3. The impedance multiplication structure according to claim 2, characterized in that, It further includes: a back resistor disposed on the second surface of the substrate, the back resistor being connected to the third external electrode and the fourth external electrode.
4. The impedance multiplication structure according to claim 3, characterized in that, It further includes: a first side electrode and a second side electrode, the first side electrode being connected to the first external electrode and the third external electrode, and the second side electrode being connected to the second external electrode and the fourth external electrode.
5. The impedance multiplication structure according to claim 4, characterized in that, The resistance values of the plurality of meter resistors differ from each other by a factor of 10 or more, and the resistance value of the back resistor is a factor of 10 or more of the maximum value among the plurality of meter resistors.
6. The impedance multiplication structure according to claim 3, characterized in that, It further includes: an inner protective layer disposed on the plurality of meter resistors and the plurality of impedance adjustment electrodes, and exposing the first outer electrode and the second outer electrode.
7. The impedance multiplication structure according to claim 6, characterized in that, The inner protective layer is a transparent glass protective layer.
8. The impedance multiplication structure according to claim 6, characterized in that, It further includes: an outer protective layer disposed on the inner protective layer, the third outer electrode, the fourth outer electrode and the back resistor, and exposing the plurality of impedance adjustment electrodes.
9. The impedance multiplication structure according to claim 8, characterized in that, The outer protective layer is an insulating ink protective layer.