Electronic device

Abstract

An electronic device includes a common pin pair and a bandwidth expansion circuit. The electronic device receives or transmits a signal through the common pin pair. The signal is a differential signal. The bandwidth expansion circuit is electrically coupled with the common pin pair and comprises a first inductor pair, a second inductor pair, a first capacitor pair and a second capacitor pair. The first inductor pair is electrically connected between the common pin pair and the node pair. The second inductor pair is electrically connected with the first inductor pair through the node pair. The first capacitor pair is electrically connected between the node pair and the grounding point. The second capacitor pair is electrically connected between the common pin pair and the grounding point. The first inductor pair comprises a first inductor and a second inductor. The second inductor pair comprises a third inductor and a fourth inductor. A coupling effect exists between the first inductor and the second inductor. A coupling effect exists between the third inductor and the fourth inductor.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic device, especially electronic device for improving impedance matching bandwidth of common pin. BACKGROUND

[0002] In the prior art of integrated circuit (IC) design, a T-coil circuit is often used to increase the bandwidth of a circuit, and a node between two inductors in the T-coil circuit is often directly electrically connected to a receiving circuit and a transmitting circuit. However, since the node between the two inductors in the T-coil circuit is simultaneously connected to the receiving circuit and the transmitting circuit, the parasitic capacitances of the receiving circuit and the transmitting circuit are all superimposed on the node, which increases the equivalent capacitance connected to the node and causes the bandwidth to decrease or the increased bandwidth to be limited. SUMMARY

[0003] The electronic device according to the embodiments of the utility model includes a common pin pair and a bandwidth extension circuit. The electronic device receives or transmits a signal through the common pin pair. The signal is a differential signal. The bandwidth extension circuit is electrically coupled to the common pin pair and includes a first inductor pair, a second inductor pair, a first capacitor pair, a second capacitor pair, and a third capacitor pair. The first inductor pair is electrically connected between the common pin pair and a node pair. The second inductor pair is electrically connected to the first inductor pair through the node pair. The first capacitor pair is electrically connected between the node pair and a ground. The second capacitor pair is electrically connected between the common pin pair and the ground. The third capacitor pair is electrically connected between the second inductor pair and the ground. The first inductor pair includes a first inductor and a second inductor. The second inductor pair includes a third inductor and a fourth inductor. The first inductor and the second inductor have a coupling effect. The third inductor and the fourth inductor have a coupling effect.

[0004] The electronic device as described above further includes a high-frequency impedance matching circuit electrically connected between the common pin pair and the bandwidth extension circuit. The high-frequency impedance matching circuit includes a third inductor pair, a fourth capacitor pair, a fifth capacitor pair, a first resistor pair, and a second resistor pair. The third inductor pair is electrically connected between the common pin pair and the first inductor pair. The fourth capacitor pair is electrically connected to one side of the third inductor pair. The fifth capacitor pair is electrically connected to the other side of the third inductor pair. The first resistor pair is electrically connected between the fourth capacitor pair and the ground. The second resistor pair is electrically connected between the fifth capacitor pair and the ground. The third inductor pair includes a fifth inductor and a sixth inductor. The fifth inductor and the sixth inductor have a coupling effect.

[0005] The electronic device as described above further includes a switch pair and a terminal resistor pair. The switch pair is electrically connected to the second inductor pair. The terminal resistor pair is electrically connected between the switch pair and the ground. When the electronic device receives the signal through the common pin pair, the switch pair is turned on. When the electronic device transmits the signal through the common pin pair, the switch pair is not turned on.

[0006] The electronic device as claimed in the preceding paragraph, further comprising a receiving circuit. The receiving circuit is electrically connected to the node pair, and is configured to receive a signal from the common pin pair.

[0007] The electronic device as claimed in the preceding paragraph, further comprising a transmitting circuit. The transmitting circuit is electrically connected to the second inductor pair, and is configured to transmit a signal to the common pin pair.

[0008] The electronic device as claimed in the preceding paragraph, wherein the first inductor generates an equivalent inductance according to a coupling effect, and the equivalent inductance is obtained according to the following equation: L eff = L * (1 + k s ). L eff is the equivalent inductance, L is an inductance value of the first inductor, and k s is a coupling coefficient between the first inductor and the second inductor. The coupling coefficient is greater than zero.

[0009] The electronic device as claimed in the preceding paragraph, wherein the first capacitor pair comprises a parasitic capacitance generated when the receiving circuit is electrically connected to the node pair.

[0010] The electronic device as claimed in the preceding paragraph, wherein the third capacitor pair comprises a parasitic capacitance generated when the transmitting circuit is electrically connected to the second inductor pair.

[0011] The electronic device as claimed in the preceding paragraph, wherein the first capacitor pair comprises a parasitic capacitance generated when an electrostatic discharge (ESD) diode is electrically connected to the node pair, respectively.

[0012] The electronic device as claimed in the preceding paragraph, wherein the common pin pair is a pair of pins of a semiconductor package. The semiconductor package comprises a semiconductor chip.

[0013] The electronic device as claimed in the preceding paragraph, wherein the node pair is a pair of pins of the semiconductor chip. The first inductor pair and the second inductor pair are bonding wires configured to be electrically connected to the common pin pair.

[0014] The electronic device as claimed in the preceding paragraph, wherein the signal comprises a high-frequency component signal and a low-frequency component signal. When the electronic device receives the signal through the common pin pair, the high-frequency component signal is terminated by the first resistor pair, and the low-frequency component signal is terminated by the terminal resistor pair. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present application.

[0016] Figure 2 FIG. 2 is a schematic diagram of a T-coil according to the prior art.

[0017] Figure 3A schematic view of the electronic device 300 according to an embodiment of the present application.

[0018] Figure 4 A schematic view of the electronic device 300 according to an embodiment of the present application. Figure 3 A schematic view of a pair of inductors including an inductor LP and an inductor LN.

[0019] Figure 5A A graph of return loss S11 and transmission loss S21 of the T-shaped coil 200 according to the related art.

[0020] Figure 5B A schematic view of the electronic device 300 according to an embodiment of the present application. Figure 1 The electronic device 100 and Figure 3 A graph of return loss S11 and transmission loss S21 of the electronic device 300 according to an embodiment of the present application.

[0021] SYMBOL DESCRIPTION

[0022] 100, 300: electronic device

[0023] 102p: common pin

[0024] 102n: common pin

[0025] 104, 304: bandwidth extension circuit

[0026] 106, 306: high-frequency impedance matching circuit

[0027] 108, RX: reception circuit

[0028] 110, TX: transmission circuit

[0029] 112p: switch

[0030] 112n: switch

[0031] Sp: positive-phase signal

[0032] Sn: negative-phase signal

[0033] LP1: inductor

[0034] LP2: inductor

[0035] LP: inductor

[0036] LN1: inductor

[0037] LN2: inductor

[0038] LN: inductor

[0039] C ESDP : capacitor

[0040] C ESDN : capacitor

[0041] CP1: Capacitance

[0042] CP2: Capacitance

[0043] CP3: Capacitance

[0044] CP4: Capacitance

[0045] CN1: Capacitance

[0046] CN2: Capacitance

[0047] CN3: Capacitance

[0048] CN4: Capacitance

[0049] RT1: Resistance

[0050] RT2: Resistance

[0051] RT: Resistance

[0052] RT3: Resistance

[0053] RT4: Resistance

[0054] RT5: Resistance

[0055] A, B, C, D, E, F: Node

[0056] 200: T Coil

[0057] I / O: Input / Output

[0058] L1: Inductance

[0059] L2: Inductance

[0060] S11: Return Loss

[0061] S21: Transmission Loss DETAILED DESCRIPTION

[0062] Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0063] The present application will now be described with reference to a number of drawings. In the drawings, which are not necessarily drawn to scale, like reference numbers will be used to refer to like parts throughout the several views. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal sense unless expressly so defined herein.

[0064] The terms "about," "equal," "equivalent," or "substantially" or "approximately" are generally interpreted as being within 20% of a given value or range, or within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0065] The use of ordinal terms such as "first," "second," etc. as used in the specification and claims is to modify an element of the claim itself, and does not imply or represent any order or order of manufacture of the elements, and is used only to distinguish one element from another element having the same name. The same word can not be used in the claims and the specification, whereby the first member in the specification can be the second member in the claims.

[0066] The electrical connection or coupling described in the utility model can be direct connection or indirect connection. In the case of direct connection, the terminals of the elements on the two circuits are directly connected or connected to each other through a conductor segment. In the case of indirect connection, there is a switch, a diode, a capacitor, an inductor, a resistor, other suitable elements, or a combination of the above elements between the terminals of the elements on the two circuits, but not limited thereto.

[0067] It should be understood that the following examples can be replaced, reorganized, mixed to complete other examples without departing from the spirit of the utility model. The features of each embodiment can be arbitrarily mixed and used as long as they do not conflict with the spirit of the invention.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. It will be understood that terms such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present utility model, and should not be interpreted in an idealized or overly formal sense unless expressly so defined in the utility model embodiments.

[0069] In the implementation of integrated circuits (IC), electrostatic discharge (ESD) protection circuits are generally used to prevent static electricity from damaging ICs. However, ESD protection circuits contain parasitic capacitance, which reduces the bandwidth of the output / input port circuit of the IC, thereby affecting the quality of the IC transceiver signal. In the past, T-coil circuits were used to absorb the parasitic capacitance of the ESD protection circuit to extend the bandwidth of the output / input port circuit (I / O port) of the ESD protection circuit.

[0070] Figure 2This is a schematic diagram of a T-coil 200 in the prior art. Figure 2 As shown, the T-type coil 200 includes an input / output terminal (I / O), an inductor L1, an inductor L2, and a capacitor C. ESD A capacitor C PAR A terminating resistor R is connected. Inductor L1 is electrically connected between node C and the input / output (I / O) terminal. Inductor L2 is electrically connected between node C and node D. Capacitor C... ESD The capacitor is electrically connected between node C and ground. PAR A bridging resistor is connected between inductors L1 and L2. The terminating resistor R is electrically connected between node D and ground. The T-coil 200 is a traditional T-coil circuit.

[0071] exist Figure 2 In the middle, capacitor C PAR This is the parasitic capacitance between inductors L1 and L2. Capacitance C ESD This is the parasitic capacitance generated when the electrostatic discharge diode is connected to node C. The electrostatic discharge diode is used to protect against electrostatic pulses from the input / output (I / O) terminals. In traditional T-coil circuit applications, when the T-coil circuit is used for half-duplex transmission, both the receiving and transmitting circuits are electrically connected to node C, thus causing capacitance C to... ESD This includes the parasitic capacitance generated when the receiving and transmitting circuits are electrically connected to node C. Although the T-coil 200 also has the function of amplifying the bandwidth of the entire transmission line, for example, amplifying it to 3 times the original bandwidth, the high-frequency response of the entire transmission line deteriorates due to the parasitic capacitance generated when the transmitting and receiving circuits are simultaneously connected to the T-coil circuit. This reduces the basic bandwidth of the entire transmission line, thereby reducing the bandwidth amplification efficiency of the T-coil circuit.

[0072] Furthermore, in Figure 2In a traditional T-coil circuit 200, point C is the junction for receiving / transmitting signals, while point D is used to terminate the characteristic impedance for impedance matching. However, because the path from the output / input port circuit to point D is an all-pass transfer function containing zeros in the right half-plane, it is unsuitable for serial data transmission (SerDes). Therefore, when both the receiving and transmitting circuits are connected to point C, although only one circuit is conducting at a time, the closed circuit increases the capacitive load at point C, thus reducing the bandwidth. To enable serial data transmission from the output / input port circuit to point D, this invention eliminates the coupling effect between LP1 and LP2. Therefore, the transition from the output / input port circuit to point D is no longer a full-pass transfer function. Thus, point D can be connected to either a receiving circuit or a transmitting circuit. In other words, both points C and D can be connected to either a receiving circuit or a transmitting circuit. Therefore, this invention does not require simultaneously connecting the receiving circuit and / or the transmitting circuit to point C, thereby reducing the capacitive load at point C and improving bandwidth. This is why the electronic device 100 with high-frequency impedance matching circuit 106 and the electronic device 300 with high-frequency impedance matching circuit 306 of this invention were designed. Furthermore, to improve the return loss of the output / input port circuit, an additional high-frequency impedance matching circuit is added, which will be explained below.

[0073] Figure 1 This is a schematic diagram of the electronic device 100 according to an embodiment of the present utility model. Figure 1 As shown, the electronic device 100 includes a common pin 102p, a common pin 102n, a bandwidth extension circuit 104, a high-frequency impedance matching circuit 106, a receiving circuit 108, a transmitting circuit 110, a switch 112p, a switch 112n, a terminating resistor RT, and a terminating resistor RT5. In some embodiments, the electronic device 100 receives or transmits a signal through the common pin 102p and the common pin 102n. Figure 1 In this embodiment, the signal may be, for example, a differential signal. For instance, the signal may include a positive-phase signal Sp and an inverted signal Sn. A common pin 102p is used to receive or transmit the positive-phase signal Sp. A common pin 102n is used to receive or transmit the inverted signal Sn.

[0074] However, this invention does not limit the signal to a differential signal. For example, if the signal is not a differential signal, the electronic device 100 only needs to receive or transmit the signal through one of the common pins 102p and 102n. In some embodiments, the electronic device 100 may be, for example, a semiconductor package. The common pin 102p may be, for example, one pin of the semiconductor package. The common pin 102n may be, for example, another pin of the semiconductor package. In some embodiments, the semiconductor package may utilize any industry-existing packaging technology, such as wafer-level chip-scale package (WLCSP), chip on flex (COF), chip on glass (COG), and chip on plastic (COP).

[0075] exist Figure 1 In this embodiment, the bandwidth extension circuit 104 is electrically coupled to a common pin 102p and a common pin 102n. More specifically, the bandwidth extension circuit 104 is electrically coupled to the common pin 102p and the common pin 102n via a high-frequency impedance matching circuit 106. Figure 1 In this embodiment, the bandwidth extension circuit 104 includes inductor LP1, inductor LP2, and capacitor C. ESDP Capacitors CP1 and CP2. The high-frequency impedance matching circuit 106 includes an inductor LP, capacitors CP3 and CP4, resistors RT1 and RT2. In some embodiments, inductor LP1 is electrically connected between a common pin 102p (or inductor LP) and a node A. Inductor LP2 is electrically connected to inductor LP1 through node A. Capacitor C ESDP The capacitor CP1 is electrically connected between node A and a ground point. The capacitor CP2 is electrically connected between the common pin 102p (or inductor LP) and the ground point.

[0076] In some embodiments, inductor LP1 is different from inductor LP2, and there is no coupling effect between inductors LP1 and LP2. In some embodiments, there is no mutual inductance between inductors LP1 and LP2, or the mutual inductance between them is minimized. In other words, the magnetic field lines generated by inductor LP1 do not intersect with the magnetic field lines generated by inductor LP2. In some embodiments, the angle between inductors LP1 and LP2 may be 90 degrees when viewed from above, but the present invention is not limited thereto. In some embodiments, the semiconductor package includes a semiconductor chip. The semiconductor chip may, for example, include a bandwidth extension circuit 104. Node A is a pin of the semiconductor chip. Inductors LP1 and LP2 are bonding wires for electrically connecting to a common pin 102p.

[0077] In some embodiments, the capacitor C in the bandwidth extension circuit 104 ESDP This includes the parasitic capacitance generated when an electrostatic discharge (ESD) diode is connected to node A. The ESD diode is used to protect against electrostatic pulses from the common pin 102p. Capacitors CP1 and CP2 are parasitic capacitances generated between layers in the semiconductor chip, and / or parasitic capacitances generated by adjacent wires in the circuit layout of the semiconductor chip.

[0078] exist Figure 1 In some embodiments, the high-frequency impedance matching circuit 106 includes an inductor LP, capacitors CP3 and CP4, resistors RT1 and RT2. In some embodiments, inductor LP is electrically connected between a common pin 102p and inductor LP1. Capacitor CP3 is electrically connected to one side of inductor LP. Capacitor CP4 is electrically connected to the other side of inductor LP. Resistor RT1 is electrically connected between capacitor CP3 and ground. Resistor RT2 is electrically connected between capacitor CP4 and ground. In some embodiments, switch 112p is electrically connected to inductor LP2 and capacitor CP2. Termination resistor RT is electrically connected between switch 112p and ground. When the electronic device 100 receives a signal through common pin 102p, switch 112p is turned on. On the other hand, when the electronic device 100 transmits a signal through common pin 102p, switch 112p is not turned on.

[0079] When the signal is a differential signal, the bandwidth extension circuit 104 also includes inductor LN1, inductor LN2, and capacitor C. ESDN The high-frequency impedance matching circuit 106 also includes an inductor LN, capacitors CN1 and CN2, and resistors RT3 and RT4. In some embodiments, inductor LN1 is electrically connected between a common pin 102n (or inductor LN) and a node B. Inductor LN2 is electrically connected to inductor LN1 through node B. Capacitor C ESDN The capacitor CN1 is electrically connected between node B and ground. The capacitor CN2 is electrically connected between the common pin 102n (or inductor LN) and ground.

[0080] In some embodiments, the inductance LN1 is different from the inductance LN2, and there is no coupling effect between the inductance LN1 and the inductance LN2. In some embodiments, there is no mutual inductance between the inductance LN1 and the inductance LN2, or the mutual inductance between them is reduced as much as possible. In other words, the magnetic lines of force generated by the inductance LN1 do not intersect with the magnetic lines of force generated by the inductance LN2. In some embodiments, the included angle between the inductance LN1 and the inductance LN2 can be 90 degrees as viewed from the top, but the present application is not limited thereto. In some embodiments, the node B is a pin of a semiconductor chip. The inductance LN1 and the inductance LN2 are wire bonds for electrically connecting to the common pin 102n.

[0081] In some embodiments, the capacitance C ESDN The parasitic capacitance includes the parasitic capacitance generated when the electrostatic discharge diode is connected to the node B. The electrostatic discharge diode is used to protect against electrostatic pulses from the common pin 102n. The capacitances CN1 and CN2 are parasitic capacitances generated between layers in the semiconductor chip, and / or parasitic capacitances generated by adjacent conductive lines in the circuit layout of the semiconductor chip.

[0082] In the case of a differential signal, the high-frequency impedance matching circuit 106 further includes an inductance LN, a capacitance CN3, a capacitance CN4, a resistance RT3, and a resistance RT4. In some embodiments, the inductance LN is electrically connected between the common pin 102n and the inductance LN1. The capacitance CN3 is electrically connected to one side of the inductance LN. The capacitance CN4 is electrically connected to the other side of the inductance LN. The resistance RT3 is electrically connected between the capacitance CN3 and the ground. The resistance RT4 is electrically connected between the capacitance CN4 and the ground. In some embodiments, the switch 112n is electrically connected between the inductance LN2 and the capacitance CN2. The termination resistance RT5 is electrically connected between the switch 112n and the ground. When the electronic device 100 receives a signal through the common pin 102n, the switch 112n is turned on. On the other hand, when the electronic device 100 transmits a signal through the common pin 102n, the switch 112n is not turned on.

[0083] In the case of a differential signal, the signal can include a positive-phase signal Sp and a negative-phase signal Sn. The common pin 102p is used to receive or transmit the positive-phase signal Sp in the signal. The common pin 102n is used to receive or transmit the negative-phase signal Sn in the signal. In some embodiments, the receiving circuit (RX) 108 is electrically connected between the node A and the node B to receive the signal (e.g., including the positive-phase signal Sp and the negative-phase signal Sn) from the common pin 102p and the common pin 102n. The transmitting circuit (TX) 110 is electrically connected between the inductance LP2 and the inductance LN2 to transmit the signal (e.g., including the positive-phase signal Sp and the negative-phase signal Sn) to the common pin 102p and the common pin 102n.

[0084] In some embodiments, capacitor C ESDP and capacitor C ESDN In addition to the parasitic capacitance generated when the electrostatic discharge diode is connected to nodes A and B, the parasitic capacitance generated when the receiving circuit 108 is electrically connected to nodes A and B is also included. In some embodiments, capacitors CP2 and CN2 include not only the parasitic capacitance generated between layers in the semiconductor chip, and / or the parasitic capacitance generated by adjacent wires in the circuit layout of the semiconductor chip, but also the parasitic capacitance generated when the transmitting circuit 110 is electrically connected to inductors LP2 and LN2.

[0085] When the signals are differential signals, the positive-phase signal Sp and the negative-phase signal Sn respectively include high-frequency and low-frequency components. Figure 1 In practical circuit applications, when electronic device 100 receives the positive-phase signal Sp and the negative-phase signal Sn through common pin 102p and common pin 102n respectively, since the impedance of capacitors CP3 and CN3 is extremely small (equivalent to a short circuit) for high-frequency components, and the impedance of inductors LP and LN is extremely large (equivalent to an open circuit), the high-frequency components of the positive-phase signal Sp and the negative-phase signal Sn will pass through capacitors CP3 and CN3, and thus terminate at resistors RT1 and RT3. Therefore, the high-frequency impedance matching circuit 106 can effectively improve the frequency response of electronic device 100 when transmitting high-frequency components.

[0086] Similarly, when electronic device 100 receives the positive phase signal Sp and the inverted phase signal Sn through common pin 102p and common pin 102n respectively, since for low-frequency components of the signal, capacitors CP3, CN3, CP4, CN4, CP1, CN1, and C... ESDP ,capacitance CESDN The impedances of capacitors CP2 and CN2 are extremely high (equivalent to an open circuit), while the impedances of inductors LP, LN, LP1, LN1, LP2, and LN2 are extremely low (equivalent to a short circuit). The low-frequency components of the positive-phase signal Sp and the negative-phase signal Sn will first pass through inductors LP, LN, LP1, LN1, LP2, and LN2, then through switches 112p and 112n (both are in the ON state), and thus terminate at terminating resistors RT and RT5. Therefore, the frequency response of electronic device 100 when transmitting low-frequency components remains excellent.

[0087] Figure 3 This is a schematic diagram of an electronic device 300 according to an embodiment of the present invention. The biggest difference between electronic device 300 and electronic device 100 is that electronic device 300 uses multiple pairs of inductors that are coupled to each other. For example... Figure 3As shown, the electronic device 300 includes a common pin pair (including common pin pair 102p and common pin 102n), a bandwidth extension circuit 304, a high-frequency impedance matching circuit 306, a receiving circuit 108, a transmitting circuit 110, a switch pair (including switch 112p and switch 112n), and a terminating resistor pair (including terminating resistor RT and terminating resistor RT5). In some embodiments, the electronic device 300 receives or transmits a signal through the common pin pair (including common pin pair 102p and common pin 102n). Figure 3 In this embodiment, the signal is a differential signal. For example, the signal may include a positive-phase signal Sp and an inverted signal Sn. A common pin 102p is used to receive or transmit the positive-phase signal Sp. A common pin 102n is used to receive or transmit the inverted signal Sn. In some embodiments, the electronic device 300 may be, for example, a semiconductor package. The common pin pair (including the common pin pair 102p and the common pin 102n) may be, for example, a pair of pins of a semiconductor package. In some embodiments, the semiconductor package may utilize any industry-existing packaging technology, such as wafer-level chip-scale package (WLCSP), chip-on-film package (COF), glass-on-gold package (COG), and plastic-on-chip package (COP).

[0088] exist Figure 3 In this embodiment, the bandwidth extension circuit 304 is electrically coupled to a common pin pair (including common pin pair 102p and common pin 102n). Specifically, the bandwidth extension circuit 304 is electrically coupled to common pin 102p and common pin 102n via a high-frequency impedance matching circuit 306. Figure 3 In the embodiments, the bandwidth extension circuit 304 includes a first inductor pair (including inductor LP1 and inductor LN1), a second inductor pair (including inductor LP2 and inductor LN2), and a first capacitor pair (including capacitor C). ESDP and C ESDN The second capacitor pair (including capacitor CP1 and capacitor CN1) and the third capacitor pair (including capacitor CP2 and capacitor CN2).

[0089] exist Figure 3 In this embodiment, the first inductor pair (including inductors LP1 and LN1) is electrically connected between a common pin pair (including common pin pair 102p and common pin 102n) and a node pair (including node A and node B). The second inductor pair (including inductors LP2 and LN2) is electrically connected to the first inductor pair via the node pair (including node A and node B). The first capacitor pair (including capacitor C) ESDP and C ESDN) electrically connected between the node pair and a ground. A second capacitor pair (including capacitor CP1 and capacitor CN1) is electrically connected between the common pin pair and the ground. A third capacitor pair (including capacitor CP2 and capacitor CN2) is electrically connected between the second inductor pair and the ground.

[0090] In Figure 3 some embodiments, the inductance LP1 and the inductance LN1 have a coupling effect therebetween. For example, the coupling effect between the inductance LP1 and the inductance LN1 can be represented, for example, by a coupling coefficient k s1 . The inductance LP2 and the inductance LN2 also have a coupling effect therebetween. For example, the coupling effect between the inductance LP2 and the inductance LN2 can be represented, for example, by a coupling coefficient k s2 . In some embodiments, the inductance LP1 generates a first equivalent inductance in accordance with the coupling effect (i.e., the coupling coefficient k s1 ) therebetween, and the first equivalent inductance is obtained by the following equation: L eff1 = L1*(1+k s1 ). L eff1 is the first equivalent inductance, L1 is the inductance value of the inductance LP1, and k s1 is the coupling coefficient between the inductance LP1 and the inductance LN1. The coupling coefficient k s1 is greater than zero. In some embodiments, the inductance LN1 generates a second equivalent inductance in accordance with the coupling effect (i.e., the coupling coefficient k s1 ) therebetween, and the second equivalent inductance is obtained by the following equation: L eff2 = L2*(1+k s1 ). L eff2 is the second equivalent inductance, L2 is the inductance value of the inductance LN1. Since the coupling coefficient k s1 is greater than zero, the actual inductance value of the first equivalent inductance L eff1 corresponding to the inductance LP1 will be greater than the inductance value of the inductance LP1, and the actual inductance value of the second equivalent inductance L eff2 corresponding to the inductance LN1 will be greater than the inductance value of the inductance LN1.

[0091] For example, assume that in the design of the electronic device 100, the inductance values of the inductance LP1 and the inductance LN1 in the bandwidth extension circuit 104 need to be 200 nH. However, in the design of the electronic device 300, since the inductance LP1 and the inductance LN1 have a coupling effect (i.e., the coupling coefficient k s1 ) therebetween, for example, the coupling coefficient k s1 is 0.5 (the coupling coefficient k s1(It can be between 0.1 and 0.5). In order to make the inductance values ​​of the first equivalent inductance of the corresponding inductor LP1 and the second equivalent inductance of the corresponding inductor LN1 200nH, the inductance values ​​of inductor LP1 and inductor LN1 only need to be designed as 200 / (1+0.5)=133.33nH.

[0092] Because the inductance values ​​of inductors LP1 and LN1 in the bandwidth extension circuit 304 are reduced from 200nH to 133.33nH, the layout space for inductors LP1 and LN1 on the circuit board will also decrease. Similarly, due to the coupling effect between inductors LP2 and LN2 (i.e., the coupling coefficient k...), s2 ), and the coupling coefficient k s2 The inductance values ​​can be between 0.1 and 0.5. Compared to the bandwidth expansion circuit 104, the inductance values ​​of inductors LP2 and LN2 in the bandwidth expansion circuit 304 can also be reduced, which makes the layout space of inductors LP2 and LN2 on the circuit board smaller.

[0093] The high-frequency impedance matching circuit 306 includes a third inductor pair (including inductors LP and LN), a fourth capacitor pair (including capacitors CP3 and CN3), a fifth capacitor pair (including capacitors CP4 and CN4), a first resistor pair (including resistors RT1 and RT3), and a second resistor pair (including resistors RT2 and RT4). Figure 3 In this embodiment, the third inductor pair (including inductors LP and LN) is electrically connected between the common pin pair (including common pin pair 102p and common pin 102n) and the first inductor pair (including inductors LP1 and LN1). The fourth capacitor pair (including capacitors CP3 and CN3) is electrically connected to one side of the third inductor pair. The fifth capacitor pair (including capacitors CP4 and CN4) is electrically connected to the other side of the third inductor pair. The first resistor pair (including resistors RT1 and RT3) is electrically connected between the fourth capacitor pair and ground. The second resistor pair (including resistors RT2 and RT4) is electrically connected between the fifth capacitor pair and ground.

[0094] exist Figure 3 In this embodiment, there is a coupling effect between inductor LP and inductor LN. For example, the coupling effect between inductor LP and inductor LN can be expressed by a coupling coefficient k. s This is represented. The inductor LP is based on the coupling effect (i.e., the coupling coefficient k). s A third equivalent inductance is generated, and the third equivalent inductance is obtained by the following formula: L eff3 =L3*(1+k s L eff3 L3 is the third equivalent inductance, where L3 is the inductance value of inductor LP, and k is the value of inductance. s Let k be the coupling coefficient between inductors LP and LN.s Greater than zero. In some embodiments, the inductor LN is determined based on the coupling effect (i.e., the coupling coefficient k). s A fourth equivalent inductance is generated, and the fourth equivalent inductance is obtained by the following formula: L eff4 =L4*(1+k s L eff4 L4 is the fourth equivalent inductance, and L4 is the inductance value of inductor LN. Due to the coupling coefficient k... s The value is greater than zero, making the third equivalent inductance L corresponding to the inductance LP greater than zero. eff3 The actual inductance value will be greater than the inductance value of inductor LP, and the fourth equivalent inductance L corresponding to inductor LN will be greater. eff4 The actual inductance value will be greater than the inductance value of inductor LN.

[0095] For example, suppose that in the design of electronic device 100, the inductance values ​​of inductors LP and LN in the high-frequency impedance matching circuit 106 need to be 120nH. However, in the design of electronic device 300, due to the coupling effect between inductors LP and LN (i.e., the coupling coefficient k...), s For example, the coupling coefficient k s1 The coupling coefficient k is 0.2. s (The inductance can be between 0.1 and 0.5). To ensure that the inductance values ​​of the third equivalent inductance of inductor LP and the fourth equivalent inductance of inductor LN are 120nH, the inductance values ​​of inductors LP and LN only need to be designed as 120 / (1+0.2) = 100nH. Since the inductance values ​​of inductors LP and LN in the high-frequency impedance matching circuit 306 are reduced from 120nH to 100nH, the layout space of inductors LP and LN on the circuit board will also be smaller.

[0096] exist Figure 3 In some embodiments, a switch pair (including switch 112p and switch 112n) is electrically connected to a second inductor pair (including inductor LP2 and inductor LN2). A terminating resistor pair (including terminating resistor RT and terminating resistor RT5) is electrically connected between the switch pair and a ground point. In some embodiments, when the electronic device 300 receives a signal through a common pin pair (including common pin pair 102p and common pin 102n), the switch pair (including switch 112p and switch 112n) is turned on. When the electronic device 300 transmits a signal through the common pin pair, the switch pair is not turned on. Figure 3 In this embodiment, the receiving circuit 108 is electrically connected to a node pair (including node A and node B) to receive signals from a shared pin pair. The transmitting circuit 110 is electrically connected to a second inductor pair (including inductor LP2 and inductor LN2) to transmit signals to the shared pin pair.

[0097] exist Figure 3 In the embodiment, the first capacitor pair (including capacitor C)ESDP and C ESDN The first capacitor pair (including node A and node B) includes the parasitic capacitance generated when the receiving circuit 108 is electrically connected to the node pair (including node A and node B). The third capacitor pair (including capacitor CP2 and capacitor CN2) includes the parasitic capacitance generated when the transmitting circuit 110 is electrically connected to the second inductor pair (including inductor LP2 and inductor LN2). In some embodiments, the first capacitor pair (including capacitor C... ESDP and C ESDN This includes the parasitic capacitance generated when electrostatic discharge (ESD) diodes are electrically connected to a node pair (including node A and node B).

[0098] Figure 4 This is an embodiment of the present utility model. Figure 3 The diagram includes an inductor pair consisting of inductor LP and inductor LN. Figure 4 The inductance pair in the middle can be, for example, Figure 3 The mid-to-high frequency impedance matching circuit 306 includes inductors LP and LN. For example, inductor LP is electrically connected between nodes E and C. Inductor LN is electrically connected between nodes F and D. Figure 4 In the embodiments described, the layout shape of inductors LP and LN can be, for example, an octagonal spiral, but the present invention is not limited thereto. The layout shape of inductors LP and LN can also be designed as a circular spiral, a hexagonal spiral, etc., as long as the design enables a coupling effect between inductors LP and LN.

[0099] Figure 5A This is a graph showing the return loss S11 and transmission loss S21 of the T-type coil 200 in the prior art. Figure 5A As shown, the return loss S11 of the T-type coil 200 increases to 3dB at a frequency of 25GHz. In other words, high-frequency signals above 25GHz will have their energy reflected after being input to the T-type coil 200, resulting in poor impedance matching.

[0100] Figure 5B This is an embodiment of the present utility model. Figure 1 Electronic device 100 and Figure 3 The graphs show the return loss S11 and transmission loss S21 of electronic device 300. (See figure.) Figure 5BAs shown, due to the arrangement of the high-frequency impedance matching circuits 106, 306, the return loss S11 of the electronic device 100 and the electronic device 300 can be maintained at 10 dB between 25 GHz and 50 GHz. In other words, the high-frequency signal above 25 GHz has little energy bounced back after inputting into the electronic device 100 and the electronic device 300. That is, the return loss S11 and T-coil 200 of the electronic device 100 and the electronic device 300 have been significantly improved.

[0101] The high-frequency impedance matching circuit 106 of the electronic device 100 and the high-frequency impedance matching circuit 306 of the electronic device 300 can effectively improve the high-frequency response of the entire transmission line, so that the basic bandwidth of the entire transmission line is increased. In addition, only the receiving circuit 108 is connected in series at the nodes A, B of the bandwidth expansion circuit 104 and the bandwidth expansion circuit 304, and the transmitting circuit 110 is connected in series at the rear stage of the bandwidth expansion circuit 104 and the bandwidth expansion circuit 304, so that the superposition of the parasitic capacitance is reduced. Finally, the bandwidth expansion circuit 104 and the bandwidth expansion circuit 304 multiply the basic bandwidth of the entire transmission line, so that the electronic device 100 and the electronic device 300 have good frequency response whether high frequency or low frequency, that is, the signal received by the electronic device 100 and the electronic device 300 can be almost completely conducted, and the reflected part is very small.

[0102] The electronic device 100 and the electronic device 300 can still effectively increase the signal transmission efficiency and transmission quality between the semiconductor package and the internal semiconductor chip, reduce the delay caused by different frequency component signals during signal transmission, and improve the eye pattern during signal transmission. The electronic device 300 further effectively reduces the circuit layout space by having multiple inductance pairs with coupling effect. The electronic device 100 and the electronic device 300 are suitable for high-speed and wide-band serial data transmission related applications, such as Peripheral Component Interconnect Express (PCI-E), Universal Serial Bus (USB), and Serial Advanced Technology Attachment (SATA), but not limited thereto.

[0103] While the embodiments of the application have been described above in connection with the examples described, we should understand that these described examples are only examples and are not intended to limit the application. Many modifications of the above-described example embodiments can be performed without violating the spirit and scope of the disclosure. Therefore, the scope and range of the application should not be limited by the above-described embodiments. Rather, the scope of the application should be defined by the claims and their equivalents. Although the above disclosure has been illustrated and described by one or more related embodiments, equivalent changes and modifications will be made according to the above specification and drawings and by others skilled in the art. In addition, although a particular feature of the application has been shown by one of the related embodiments, the above feature can be combined with one or more other features, so that there can be a need and help for any known or particular application.

[0104] The professional terms used in the specification are only for the purpose of describing the specific embodiments and are not intended to limit the application. Unless the context clearly indicates otherwise, as used herein, the singular, the and the above include the plural. Furthermore, the words "include", "contain", "have", "provide", or variations thereof are not used as a detailed description or as a claim. Rather, the above words mean to include and are intended to be equivalent to the word "include". Unless otherwise defined, all words used herein (including technical or scientific words) can be generally understood by those skilled in the art. We should understand that the above words, such as the words defined in the commonly used dictionary, should be interpreted in the same way in the context of the relevant art. Unless explicitly defined in this document, the above words will not be interpreted as idealistic or overly formal.

Claims

1. An electronic device, characterized by comprising: The application relates to a semiconductor package, comprising: a common pin pair; wherein the electronic device receives or transmits a signal through the common pin pair; the signal is a differential signal; a bandwidth extension circuit electrically coupled to the common pin pair, comprising: a first inductor pair electrically connected between the common pin pair and a node pair; a second inductor pair electrically connected to the first inductor pair through the node pair; a first capacitor pair electrically connected between the node pair and a ground; a second capacitor pair electrically connected between the common pin pair and the ground; and a third capacitor pair electrically connected between the second inductor pair and the ground; wherein the first inductor pair comprises a first inductor and a second inductor, and the second inductor pair comprises a third inductor and a fourth inductor; wherein the first inductor and the second inductor have a coupling effect, and the third inductor and the fourth inductor have a coupling effect. 2.The electronic device of claim 1, wherein, Further comprising: a high-frequency impedance matching circuit electrically connected between the common pin pair and the bandwidth extension circuit, comprising: a third inductor pair electrically connected between the common pin pair and the first inductor pair; a fourth capacitor pair electrically connected to one side of the third inductor pair; a fifth capacitor pair electrically connected to the other side of the third inductor pair; a first resistor pair electrically connected between the fourth capacitor pair and the ground; and a second resistor pair electrically connected between the fifth capacitor pair and the ground; wherein the third inductor pair comprises a fifth inductor and a sixth inductor, and the fifth inductor and the sixth inductor have a coupling effect. 3.The electronic device of claim 2, wherein, Further comprising: a switch pair electrically connected to the second inductor pair; a terminal resistor pair electrically connected between the switch pair and the ground; wherein when the electronic device receives the signal through the common pin pair, the switch pair is turned on; wherein when the electronic device transmits the signal through the common pin pair, the switch pair is not turned on. 4.The electronic device of claim 1, wherein, Further comprising: a receiving circuit electrically connected to the node pair to receive the signal from the common pin pair. 5.The electronic device of claim 1, wherein, Further comprising: a transmitting circuit electrically connected to the second inductor pair to transmit the signal to the common pin pair. 6.The electronic device of claim 1, wherein, The first inductor generates an equivalent inductance according to the coupling effect, and the equivalent inductance is obtained by the following formula: L eff1 = L1 (1+k s1 ); where L eff1 is the equivalent inductance, Li is the inductance value of the first inductor, and k s1 is the coupling coefficient between the first inductor and the second inductor; the coupling coefficient being greater than zero. 7.The electronic device of claim 4, wherein the processor is further configured to control the display to display the first object and the second object in a manner that the first object is overlapped with the second object. The first capacitor pair comprises a parasitic capacitance generated when the receiving circuit is electrically connected to the node pair. 8.The electronic device of claim 5, wherein, The third capacitor pair comprises a parasitic capacitance generated when the transmitting circuit is electrically connected to the second inductor pair. 9.The electronic device of claim 4, wherein, The first capacitor pair comprises a parasitic capacitance generated when an electrostatic discharge diode is electrically connected to the node pair. 10.The electronic device of claim 1, wherein, The common pin pair is a pair of pins of a semiconductor package; wherein the semiconductor package comprises a semiconductor chip. 11.The electronic device of claim 10, wherein, The node pair is a pair of pins of the semiconductor chip; wherein the first inductor pair and the second inductor pair are wire bonds electrically connected to the common pin pair. 12.The electronic device of claim 3, wherein, The signal comprises a high-frequency component signal and a low-frequency component signal; wherein when the electronic device receives the signal through the common pin pair, the high-frequency component signal is terminated at the first resistor pair, and the low-frequency component signal is terminated at the terminal resistor pair.

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