Low-power-consumption circuit with self-dormancy and self-awakening functions

Abstract

The utility model provides a low-power-consumption circuit with self-dormancy and self-awakening functions, which comprises a switching device M1 of which the first connecting end is connected with a power supply end VCC and the second connecting end is connected with a voltage output end VOUT; the timing power-on module comprises a first current source, a capacitor C1, a first trigger unit, a resistor R4 and a switching device Q1; the timing power-off module comprises a second current source, a capacitor C2, a second trigger unit and a switching device Q3; the power supply end Vin of the product function circuit is connected with the voltage output end VOUT, and the signal end of the product function circuit is PW-HOLD; and the input end of the self-locking power-on module is connected with the signal end of the product function circuit, and the output end of the self-locking power-on module is connected with the control end of the switching device M1. Compared with the prior art, the circuit provided by the utility model is higher in universality, and meets the requirement of low power consumption of the IC circuit without the dormancy function when the function is not enabled.

Description

TECHNICAL FIELD

[0001] The utility model relates to circuit design technical field, especially in a kind of low-power circuit with self hibernation and self wake-up function. BACKGROUND

[0002] To realize low carbon, and the lasting cruising ability of battery, under the condition of meeting product function, the low power consumption of product when function is not enabled will become important index. In the existing design scheme, the hibernation function of integrated IC is usually used, and not all circuits can use integrated IC (integrated circuit) with hibernation function.

[0003] The problems and defects of prior art scheme are: a. integrated IC cost is higher;B. Low versatility cannot be compatible with different scene function application, or to meet high compatibility, MCU (Microcontroller Uni, i.e. micro control unit) function resource waste is more.

[0004] Therefore, it is necessary to propose a new technical scheme to solve the above problems. UTILITY MODEL CONTENT

[0005] One of the purposes of the utility model is to provide a kind of low-power circuit with self hibernation and self wake-up function, which has strong versatility, and solves the low power consumption demand of no hibernation function circuit when function is not enabled.

[0006] According to one aspect of the utility model, the utility model provides a kind of low-power circuit with self hibernation and self wake-up function, it includes: switching device M1, its first connection end is connected with power supply end VCC, its second connection end is connected with voltage output end VOUT, the power supply end VCC is connected with power supply V1;Timing power-on module, it includes first current source, capacitor C1, first trigger unit, resistance R4 and switching device Q1, the input of the first current source is connected with the power supply end VCC, its output is connected with the first end of the capacitor C1, the second end of the capacitor C1 is grounded;The first connection end of the switching device Q1 is connected with the control end of the switching device M1, its second connection end is grounded, and its control end is connected with the output of the first trigger unit;The first trigger unit is used to detect the voltage of the first end of the capacitor C1, and the switching device Q1 is controlled to be turned on or turned off based on the voltage of the first end of the capacitor C1;Timing power-off module, it includes second current source, capacitor C2, second trigger unit and switching device Q3, the input of the second current source is connected with the voltage output end VOUT, its output is connected with the first end of the capacitor C2, the second end of the capacitor C2 is grounded;The first connection end of the switching device Q3 is connected with the first end of the capacitor C1, its second connection end is grounded, and its control end is connected with the output of the second trigger unit;The second trigger unit is used to detect the voltage of the first end of the capacitor C2, and the switching device Q3 is controlled to be turned on or turned off based on the voltage of the first end of the capacitor C2;Product function circuit, the power supply end Vin is connected with the voltage output end VOUT, and its signal end is PW-HOLD;Self-locking power-on module, its input is connected with the signal end of the product function circuit, and its output is connected with the control end of the switching device M1.

[0007] Compared with prior art, the utility model uses common switching device, voltage stabilizing tube, resistance, capacitor to build, only needs when it needs to keep VOUT output, the signal end PW-HOLD of product function circuit is configured to keep signal, therefore, the compatibility of this design is extremely high, low in cost, solve the low-power demand of IC circuit without hibernation function when not enabling function. ACCURACY

[0008] In order to more clearly illustrate the technical scheme of the utility model embodiment, the following will be briefly introduced to the drawing needed to be used in embodiment description, obviously, the drawing in the following description only some embodiments of the utility model, for those skilled in the art, under the premise of not paying the creativity labor intensity, other drawings can also be obtained according to these drawings. Wherein:

[0009] Figure 1This is a circuit diagram of a low-power circuit with self-sleep and self-wake-up functions in one embodiment of the present invention. Detailed Implementation

[0010] To make the above-mentioned objectives, features and advantages of this utility model more apparent and understandable, the utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0011] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. Unless otherwise specified, the terms coupling, connection, linking, and interconnection used herein to indicate electrical connection mean direct or indirect connection. For example, A being connected to B includes both a direct electrical connection between A and B and a connection between A and B via electrical components or circuits.

[0012] In the description of this utility model, it should be understood that the terms "upper", "lower", "front", "back", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0013] Please refer to Figure 1 As shown, it is a circuit diagram of a low-power circuit with self-sleep and self-wake-up functions in one embodiment of the present invention. Figure 1 The low-power circuit shown with self-sleep and self-wake-up functions includes a switching device M1, a timed power-on module (i.e., a timed POWER ON module) 110, a timed power-off module (i.e., a timed POWER OFF module) 120, a product function circuit 130, and a self-locking power-on module (i.e., a self-locking POWER ON module) 140.

[0014] The first connection terminal of the switching device M1 is connected to the power supply terminal VCC, and its second connection terminal is connected to the voltage output terminal VOUT. The power supply terminal VCC is connected to the power supply V1. Specifically, the positive terminal of the power supply V1 is connected to the power supply terminal VCC, and its negative terminal is grounded.

[0015] The timing power-on module 110 comprises a first current source 112, a capacitor C1, a first trigger unit 114, a resistor R4 and a switching device Q1, wherein the input end of the first current source 112 is connected with the power supply end VCC, the output end thereof is connected with the first end of the capacitor C1, and the second end of the capacitor C1 is grounded; the first connection end of the switching device Q1 is connected with the control end of the switching device M1, the second connection end thereof is grounded, and the control end thereof is connected with the output end of the first trigger unit 114; the first trigger unit 114 is used for detecting the voltage of the first end of the capacitor C1 and controlling the switching device Q1 to be turned on or turned off based on the voltage of the first end of the capacitor C1.

[0016] The timing power-off module 120 comprises a second current source 212, a capacitor C2, a second trigger unit 214 and a switching device Q3, wherein the input end of the second current source 212 is connected with the voltage output end VOUT, the output end thereof is connected with the first end of the capacitor C2, and the second end of the capacitor C2 is grounded; the first connection end of the switching device Q3 is connected with the first end of the capacitor C1, the second connection end thereof is grounded, and the control end thereof is connected with the output end of the second trigger unit 214; the second trigger unit 214 is used for detecting the voltage of the first end of the capacitor C2 and controlling the switching device Q3 to be turned on or turned off based on the voltage of the first end of the capacitor C2.

[0017] The power supply end Vin of the product function circuit 130 is connected with the voltage output end VOUT, the signal end thereof is PW-HOLD, and the ground end GND is grounded. When the switching device M1 is turned on, the power supply V1 supplies power to the product function circuit 130 through the switching device M1, so that the product function circuit 130 works; when the switching device M1 is turned off, the power supply V1 stops supplying power to the product function circuit 130, so that the product function circuit 130 does not work.

[0018] The input end of the self-locking power-on module 140 is connected with the signal end PW-HOLD of the product function circuit 130, and the output end thereof is connected with the control end of the switching device M1. When the signal end PW-HOLD of the product function circuit 130 outputs a hold signal, the output end of the self-locking power-on module 140 drives the switching device M1 to keep being turned on; when the signal end PW-HOLD of the product function circuit 130 outputs a non-hold signal, the output end of the self-locking power-on module 140 no longer drives the switching device M1.

[0019] Specifically, when the first trigger unit 114 detects that the voltage of the first end of the capacitor C1 is higher than the first threshold voltage, the driving switch device Q1 is turned on; when the first trigger unit 114 detects that the voltage of the first end of the capacitor C1 is lower than the first threshold voltage, the driving switch device Q1 is turned off. When the second trigger unit 214 detects that the voltage of the first end of the capacitor C2 is higher than the second threshold voltage, the driving switch device Q3 is turned on, thereby discharging the first capacitor C1; when the second trigger unit 214 detects that the voltage of the first end of the capacitor C2 is lower than the second threshold voltage, the driving switch device Q3 is turned off, thereby stopping discharging the first capacitor C1. When the switch device Q1 is turned on or the signal end PW-HOLD of the product function circuit 130 outputs a hold signal, the switch device M1 is turned on; when the switch device Q1 is turned off and the signal end PW-HOLD of the product function circuit 130 outputs a non-hold signal, the switch device M1 is turned off.

[0020] In Figure 1 In the embodiment shown, the first trigger unit 114 includes a voltage stabilizing tube D2 and a resistor R3, the negative electrode of the voltage stabilizing tube D2 is connected with the first end of the capacitor C1, and the positive electrode thereof is connected with a node A; one end of the resistor R3 is connected with the node A, and the other end thereof is grounded; the node A is connected with the control end of the switch device Q1. The second trigger unit 214 includes a voltage stabilizing tube D4 and a resistor R7, the negative electrode of the voltage stabilizing tube D4 is connected with the first end of the capacitor C2, and the positive electrode thereof is connected with a node B; one end of the resistor R7 is connected with the node B, and the other end thereof is grounded; the node B is connected with the control end of the switch device Q2.

[0021] In Figure 1 In the embodiment shown, the first current source 112 includes a voltage stabilizing tube D1, a resistor R1 and a resistor R2, the negative electrode of the voltage stabilizing tube D1 is connected with the power supply end VCC via the resistor R1, and the positive electrode thereof is grounded; one end of the resistor R2 is connected with the negative electrode of the voltage stabilizing tube D1, and the other end thereof is connected with the first end of the capacitor C1. The second current source 212 includes a voltage stabilizing tube D3, a resistor R5 and a resistor R6, the negative electrode of the voltage stabilizing tube D3 is connected with the voltage output end VOUT via the resistor R5, and the positive electrode thereof is grounded; one end of the resistor R6 is connected with the negative electrode of the voltage stabilizing tube D3, and the other end thereof is connected with the first end of the capacitor C2. Among them, the voltage stabilizing value of the voltage stabilizing tube D1 is VR_D1, the voltage stabilizing value of the voltage stabilizing tube D2 is VR_D2, and VR_D1>VR_D2; the voltage stabilizing value of the voltage stabilizing tube D3 is VR_D3, the voltage stabilizing value of the voltage stabilizing tube D4 is VR_D4, and VR_D3>VR_D4.

[0022] In Figure 1In the shown embodiment, the switch device M1 is a PMOS transistor, and the first connection end, the second connection end and the control end of the switch device M1 are the source, the drain and the gate of the PMOS transistor respectively. In another embodiment, the switch device M1 is a PNP transistor, and the first connection end, the second connection end and the control end of the switch device M1 are the emitter, the collector and the base of the PNP transistor respectively.

[0023] In Figure 1 In the shown embodiment, the switch device Q1 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch device Q1 are the collector, the emitter and the base of the NPN transistor respectively. In another embodiment, the switch device Q1 is an NMOS transistor, and the first connection end, the second connection end and the control end of the switch device Q1 are the drain, the source and the gate of the NMOS transistor respectively.

[0024] In Figure 1 In the shown embodiment, the switch device Q3 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch device Q3 are the collector, the emitter and the base of the NPN transistor respectively. In another embodiment, the switch device Q3 is an NMOS transistor, and the first connection end, the second connection end and the control end of the switch device Q3 are the drain, the source and the gate of the NMOS transistor respectively.

[0025] In Figure 1 In the shown embodiment, the self-locking power-on module 140 comprises a switch device Q2, a resistor R8 and a resistor R9, the first connection end of the switch device Q2 is connected with the control end of the switch device M1, the second connection end thereof is grounded, and the control end thereof is connected with the node C through the resistor R8, the node C is grounded through the resistor R9, and the signal end PW-HOLD of the product function circuit 130 is connected with the node C.

[0026] In Figure 1 In the shown embodiment, the switch device Q2 is an NPN transistor, and the first connection end, the second connection end and the control end of the switch device Q2 are the collector, the emitter and the base of the NPN transistor respectively. In another embodiment, the switch device Q2 is an NMOS transistor, and the first connection end, the second connection end and the control end of the switch device Q2 are the drain, the source and the gate of the NMOS transistor respectively.

[0027] In order to facilitate understanding of the utility model, the following specifically introduces Figure 1 The working principle of the low-power consumption circuit with self-sleeping and self-waking functions shown.

[0028] When the power is first turned on, in the timing power-on module 110, the power supply end VCC is stabilized through the series connection of the voltage stabilizing tube D1 and the resistor R1, and the capacitor C1 starts to charge. When the maximum voltage of the capacitor C1 charging reaches VR_D2+Vbe_Q1 (which can be referred to as a first threshold voltage), that is, Vbe_Q1 reaches about 0.7V, the transistor Q1 will enter a saturated state, Vgs_M1 of the MOS tube M1 =-(VCC-Vce_Q1) is less than Vgs(th), the MOS tube M1 is turned on, and the output voltage VOUT≈VCC. By controlling the charging time of the capacitor C1, the MOS tube M1 can be realized to be turned on in a timing manner, so that the voltage output end VOUT opens the output, and VOUT is approximately equal to the voltage of the power supply end VCC.

[0029] After the voltage output end VOUT opens the output, if the product function circuit 130 judges that the power supply needs to be continuous, the configuration signal end PW-HOLD outputs a high level (which can be referred to as a holding signal), the transistor Q2 is configured to be in a saturated state through the current-limiting resistor R8, Vgs_M1 of the MOS tube M1 =-(VCC-Vce_Q2) is less than Vgs(th), and the MOS tube M1 will remain in a conduction state, realizing the self-locking of the power on (i.e., the power-on self-locking), and the voltage output end VOUT continuously outputs; if the product function circuit 130 does not need to be powered, the configuration signal end PW-HOLD outputs a low level (which can be referred to as a non-holding signal), so that the transistor Q2 is in a cut-off state (or an off state), and the MOS tube M1 will no longer be controlled by the transistor Q2.

[0030] At the same time when the voltage output end VOUT opens the output, in the timing power-off module 120, the voltage output end VOUT is stabilized through the series connection of the voltage stabilizing tube D3 and the resistor R5, and the capacitor C2 starts to charge. When the maximum voltage of the capacitor C2 charging reaches VR_D4+Vbe_Q3 (which can be referred to as a second threshold voltage), that is, Vbe_Q3 reaches about 0.7V, the transistor Q3 will enter an amplification state, Ic_Q3 is greater than 0A, the charge on the capacitor C1 is discharged, so that the voltage on the capacitor C1 decreases, and when the voltage on the capacitor C1 decreases to about VR_D2, the transistor Q1 will be cut off due to Vbe_Q1<0.7V, Ic_Q1=0A, Vgs_M1 of the MOS tube M1≈VCC>Vgs(th), the MOS tube M1 is cut off, and the output voltage VOUT will decrease to 0V after the capacitor on the circuit is discharged. By controlling the charging time of the capacitor C2, the MOS tube M1 can be realized to be turned off in a timing manner, so that the voltage output end VOUT closes the output to 0V.

[0031] When the voltage output terminal VOUT is closed to output 0V, the charge on the capacitor C2 is mainly discharged through the resistor R5, the resistor R6, the resistor R7 and Vbe_Q3. When the voltage on the capacitor C2 drops to about VR_D4, the transistor Q3 will be cut off due to Vbe_Q1 < 0.7V, and the discharging action of the charge on the capacitor C1 will stop.

[0032] When the voltage output terminal VOUT is closed to output 0V, and the transistor Q3 is cut off, the capacitor C1 will start to be charged again by the power supply terminal VCC through the resistor R1 and R2. When the charging voltage of the capacitor C1 reaches VR_D2+Vbe_Q1, that is, Vbe_Q1 reaches about 0.7V, the transistor Q1 will enter the saturation state, and Vgs_M1 of the MOS transistor M1 = -(VCC-Vce_Q1) is less than Vgs(th), so that the MOS transistor M1 is turned on again, and the voltage output terminal VOUT is opened to output, and VOUT is about equal to the voltage of the power supply terminal VCC.

[0033] Therefore, if the signal terminal PW-HOLD is in a low state subsequently, the circuit will cycle through the different charging and discharging times of the capacitors C1 and C2, control the turn-on and turn-off of the MOS transistor M1, and switch the voltage output terminal VOUT between VCC voltage and 0V. If the signal terminal PW-HOLD is in a high state during the output of the voltage output terminal VOUT (i.e., during the turn-on of the MOS transistor M1), the output voltage VOUT will continue to be equal to the VCC voltage (i.e., the MOS transistor M1 will continue to be turned on).

[0034] When the voltage output terminal VOUT is closed to output 0V, the entire circuit only consumes power by the power-on module 110, and the current is very small and can be controlled by the resistors R1 and R2. The current is configured to be a maximum of 100uA. When the voltage output terminal VOUT outputs about VCC voltage, the entire circuit mainly consumes the product function circuit 130, and the consumption of the product function circuit 130 is determined by the design of the product function. Assuming that the product function circuit 130 does not enable the function at this time, the entire circuit consumes 2mA. When the turn-off time of the MOS transistor M1 is configured to be 90ms and the turn-on time is 10ms (the detection period of the product function is 100ms, and the detection judgment time is within 10ms, and the specific allocation time can be freely adjusted), the average working current of the entire circuit will be equal to 90%*100uA+10%*2mA=290uA. Compared with the circuit without the low-power circuit with self-sleep and self-wakeup functions, the entire circuit will consume 2mA of current. Therefore, due to the low-power circuit with self-sleep and self-wakeup functions, the circuit can save about 85.5% of power consumption when the function is not enabled.

[0035] It should be noted that the resistors R1 and R5 provide current limiting protection for the voltage stabilizing tubes D1 and D3, the voltage stabilizing tubes D1 and D3 make the charging and discharging time of the capacitors C1 and C2 not be affected by the power supply terminal VCC when different working voltages of the power supply terminal VCC, the resistors R2 and R6 provide current limiting protection for the voltage stabilizing tubes D2 and D4 and configure the charging and discharging time of the capacitors C1 and C2, the voltage stabilizing tubes D2 and D4 improve the charging voltage of the capacitor C1 and provide Ib current limiting protection for the switching devices Q1 and Q3, the resistors R3, R7 and R9 are the lower bias resistors of the triodes Q1-Q3 and make the triodes be in the default off state at the power-on moment, the resistor R8 is the current limiting protection for the triode Q2, the switching device Q1, the switching device Q2 and the resistor R4 drive the MOS tube M1 to be turned off or turned on, and the switching device Q3 makes the charge of the capacitor C1 be discharged after being output at the voltage output terminal VOUT, and the MOS tube M1 is the switching action between VCC and VOUT.

[0036] As can be known from the above, the capacitor C1 starts charging at the power-on moment, the voltage is greater than VR_D2+Vbe_Q1, the triode Q1 is driven to be saturated, the MOS tube M1 is turned on, VOUT is turned on to output, VOUT is approximately equal to the voltage of VCC, and the circuit is in the wake-up state. During the turning on of VOUT, if the product function circuit 130 judges that the continuous power supply is needed, the signal terminal PW-HOLD outputs a high level to make the triode Q2 be saturated, and the MOS tube M1 is continuously turned on to turn on VOUT; if the product function circuit 130 does not need the power supply, the signal terminal PW-HOLD outputs a low level to control the triode Q2 to be turned off, and the MOS tube M1 is not controlled by the triode Q2. During the output of VOUT, the capacitor C2 is charged at the same time, the charging voltage of the capacitor C2 is greater than VR_D4+Vbe_Q3, the triode Q3 is turned on, the charge of the capacitor C1 is discharged, the voltage on the capacitor C1 is lowered, the triode Q1 enters the off state, the MOS tube M1 is turned off, VOUT is turned off to be 0V, the capacitor C2 starts discharging, the voltage on the capacitor C2 is lowered, the triode Q3 is turned off, and the capacitor C1 starts charging. Thus, one cycle is completed, the opening and closing time of VOUT is controlled by controlling the charging time of the capacitors C1 and C2, the self-sleeping and self-wake-up functions of the circuit are realized, and the power consumption of the product is reduced.

[0037] As described above, the low-power-consumption circuit with the self-sleeping and self-wake-up functions has the following beneficial effects:

[0038] 1. The circuit is simple and reliable, basic components are used in the hardware design, the cost is low, and the automatic switching of the sleep mode and the wake-up mode can be realized.

[0039] 2. In the utility model, the main working current during dormancy is only the breakdown current IR of the voltage stabilizing tube D1, D2 and the charging current of the capacitor C1, so the current during dormancy is extremely small. Meanwhile, the charging time of the capacitors C1, C2 can be controlled to flexibly adjust the alternating period and time proportion of the POWER ON / OFF, so as to better reduce the average power consumption when the product is not in use and improve the compatibility of the product.

[0040] It should be noted that any modification made by those skilled in the art to the specific embodiments of the utility model does not deviate from the scope of the claims of the utility model. Accordingly, the scope of the claims of the utility model is not limited to the foregoing specific embodiments.

Claims

1. A low-power circuit with self-sleep and self-wake-up functions, characterized in that, It comprises: a switch device M1, a first connection end of which is connected with a power supply end VCC, and a second connection end of which is connected with a voltage output end VOUT, the power supply end VCC being connected with a power supply V1; a timing power-on module, comprising a first current source, a capacitor C1, a first trigger unit, a resistor R4 and a switch device Q1, an input end of the first current source being connected with the power supply end VCC, an output end of the first current source being connected with a first end of the capacitor C1, a second end of the capacitor C1 being grounded, a first connection end of the switch device Q1 being connected with a control end of the switch device M1, a second connection end of the switch device Q1 being grounded, and a control end of the switch device Q1 being connected with an output end of the first trigger unit, the first trigger unit being used for detecting a voltage of the first end of the capacitor C1, and controlling the switch device Q1 to be turned on or turned off based on the voltage of the first end of the capacitor C1; a timing power-off module, comprising a second current source, a capacitor C2, a second trigger unit and a switch device Q3, an input end of the second current source being connected with the voltage output end VOUT, an output end of the second current source being connected with a first end of the capacitor C2, a second end of the capacitor C2 being grounded, a first connection end of the switch device Q3 being connected with the first end of the capacitor C1, a second connection end of the switch device Q3 being grounded, and a control end of the switch device Q3 being connected with an output end of the second trigger unit, the second trigger unit being used for detecting a voltage of the first end of the capacitor C2, and controlling the switch device Q3 to be turned on or turned off based on the voltage of the first end of the capacitor C2; a product function circuit, a power supply end Vin of which being connected with the voltage output end VOUT, and a signal end of which being PW-HOLD; a self-locking power-on module, an input end of which being connected with the signal end of the product function circuit, and an output end of which being connected with the control end of the switch device M1.

2. The low-power-consumption circuit with self-sleeping and self-waking functions according to claim 1, wherein when the signal end PW-HOLD of the product function circuit outputs a hold signal, the output end of the self-locking power-on module drives the switch device M1 to keep being turned on; when the signal end PW-HOLD of the product function circuit outputs a non-hold signal, the output end of the self-locking power-on module no longer drives the switch device M1.

3. The low-power-consumption circuit with self-sleeping and self-waking functions according to claim 1 or 2, wherein when the first trigger unit detects that the voltage of the first end of the capacitor C1 is higher than a first threshold voltage, the switch device Q1 is driven to be turned on; when the first trigger unit detects that the voltage of the first end of the capacitor C1 is lower than the first threshold voltage, the switch device Q1 is driven to be turned off; when the second trigger unit detects that the voltage of the first end of the capacitor C2 is higher than a second threshold voltage, the switch device Q3 is turned on; when the second trigger unit detects that the voltage of the first end of the capacitor C2 is lower than the second threshold voltage, the switch device Q3 is turned off. When the switch device Q1 is turned on or the signal end PW-HOLD of the product function circuit outputs a hold signal, the switch device M1 is driven to be turned on; when the switch device Q1 is turned off and the signal end PW-HOLD of the product function circuit outputs a non-hold signal, the switch device M1 is driven to be turned off. 4.The low-power-consumption circuit with self-sleep and self-wakeup functions according to claim 3, characterized in that, the first trigger unit comprises a Zener D2 and a resistor R3, a negative electrode of the Zener D2 is connected with a first end of the capacitor C1, and a positive electrode thereof is connected with a node A; one end of the resistor R3 is connected with the node A, and the other end thereof is grounded; the node A is connected with a control end of the switch device Q1, the second trigger unit comprises a Zener D4 and a resistor R7, a negative electrode of the Zener D4 is connected with a first end of the capacitor C2, and a positive electrode thereof is connected with a node B; one end of the resistor R7 is connected with the node B, and the other end thereof is grounded; the node B is connected with a control end of the switch device Q2. 5.The low-power-consumption circuit with self-sleep and self-wakeup functions according to claim 4, characterized in that, the first current source comprises a Zener D1, a resistor R1 and a resistor R2, a negative electrode of the Zener D1 is connected with the power supply end VCC via the resistor R1, and a positive electrode thereof is grounded; one end of the resistor R2 is connected with the negative electrode of the Zener D1, and the other end thereof is connected with a first end of the capacitor C1, the second current source comprises a Zener D3, a resistor R5 and a resistor R6, a negative electrode of the Zener D3 is connected with the voltage output end VOUT via the resistor R5, and a positive electrode thereof is grounded; one end of the resistor R6 is connected with the negative electrode of the Zener D3, and the other end thereof is connected with a first end of the capacitor C2, a voltage stabilization value of the Zener D1 is greater than a voltage stabilization value of the Zener D2; and a voltage stabilization value of the Zener D3 is greater than a voltage stabilization value of the Zener D4. 6.The low-power-consumption circuit with self-sleep and self-wakeup functions according to claim 5, characterized in that, the switch device M1 is a PMOS tube, and a first connection end, a second connection end and a control end of the switch device M1 are a source electrode, a drain electrode and a gate electrode of the PMOS tube respectively; or the switch device M1 is a PNP type triode, and a first connection end, a second connection end and a control end of the switch device M1 are an emitter electrode, a collector electrode and a base electrode of the PNP type triode respectively. 7.The low-power-consumption circuit with self-sleep and self-wakeup functions according to claim 6, characterized in that, the switch device Q1 is a NPN type triode, and a first connection end, a second connection end and a control end of the switch device Q1 are a collector electrode, an emitter electrode and a base electrode of the NPN type triode respectively; or the switch device Q1 is an NMOS tube, and a first connection end, a second connection end and a control end of the switch device Q1 are a drain electrode, a source electrode and a gate electrode of the NMOS tube respectively. The first connection end, the second connection end and the control end of the switch device Q3 are the collector, the emitter and the base of the NPN triode respectively; or the switch device Q3 is an NMOS tube, and the first connection end, the second connection end and the control end of the switch device Q3 are the drain, the source and the gate of the NMOS tube respectively.

8. The low power circuit with self-hibernation and self-wakeup function according to claim 7, characterized in that, The self-locking power-on module comprises a switch device Q2, a resistor R8 and a resistor R9, The first connection end of the switch device Q2 is connected with the control end of the switch device M1, the second connection end thereof is grounded, and the control end thereof is connected with the node C through the resistor R8 once, the node C is grounded through the resistor R9, and the signal end PW-HOLD of the product function circuit is connected with the node C.

9. The low-power-consumption circuit with self-sleeping and self-waking functions according to claim 7, characterized in that, The first connection end, the second connection end and the control end of the switch device Q2 are the collector, the emitter and the base of the NPN triode respectively; or The first connection end, the second connection end and the control end of the switch device Q2 are the collector, the emitter and the base of the NPN triode respectively; or

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