Electronic component

Abstract

The utility model relates to an electronic component. More specifically, an electronic component including an electronic post is provided. An example electronic component, such as an electronic chip, includes a semiconductor substrate having opposing first and second faces and conductive posts intended to be connected to elements external to the electronic component, an insulating layer covering the second surface of the substrate, a first portion of the conductive pillar protrudes from the insulating layer and a second portion of the conductive pillar passes through the insulating layer and extends downward in the semiconductor substrate to a depth that is less than a thickness of the semiconductor substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French patent application number 2400536 entitled “Composantélectronique comprenant des piliers de connexion”, filed on January 19, 2024, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to the field of electronic components having electrical connection posts, and more specifically to the field of electronic chips having electrical connection posts to be connected to a housing or another electronic chip. Background Technology

[0004] To connect an electronic chip to an external component, connecting balls or posts can be provided on the surface of the electronic chip and connected to conductive tracks on the electronic chip. Therefore, it is possible to make contact between the connecting balls or posts and conductive areas or tracks located on an external component (e.g., a housing or another electronic chip).

[0005] The reduction in the size of electronic chips is accompanied by a reduction in the size of these interconnect components. Using pillars is superior to using balls to achieve a high aspect ratio, which is the ratio of the height to the diameter of the connection pad.

[0006] However, the use of connectors, especially when they have a high aspect ratio and / or when they have small dimensions, may have certain disadvantages: the brittleness of connectors, the high duration and cost of connector manufacturing methods, or the risk of connectors tearing from the surface of the electronic chip on which they are formed. Utility Model Content

[0007] At least some aspects of the electronic chip, including the connecting posts, need to be improved.

[0008] This objective is achieved by an electronic component, such as an electronic chip, comprising: a semiconductor substrate having opposing first and second surfaces and conductive pillars intended to connect to elements outside the electronic component; an insulating layer covering the second surface of the substrate, a first portion of the conductive pillars protruding from the insulating layer and a second portion of the conductive pillars penetrating the insulating layer and extending downward in the semiconductor substrate to a depth less than the thickness of the semiconductor substrate.

[0009] According to an embodiment, the second portion of the conductive post is formed by one or more cylindrical elements.

[0010] According to an embodiment, the second part of the conductive pillar is formed by a plurality of coaxially arranged tubular elements.

[0011] According to an embodiment, it comprises an electrically insulating layer arranged between the second portion of the electrically conductive pillar and the semiconductor substrate.

[0012] According to an embodiment, it comprises an interface layer, preferably made of TiCu, in contact with the second portion of the electrically conductive pillar, the interface layer being arranged between the electrically conductive pillar and the electrically insulating layer.

[0013] According to an embodiment, it comprises an active area extending in the semiconductor substrate from the second surface and comprising at least one discrete electronic component, each electrically conductive pillar further comprising a connection track extending over the second surface of the semiconductor substrate and electrically connected to the active area.

[0014] According to an embodiment, the first portion of the electrically conductive pillar has a height greater than 25 pm.

[0015] According to an embodiment, the second portion of the electrically conductive pillar has a height of at least 5 pm.

[0016] This object is also achieved by a method of manufacturing an electronic component, such as an electronic chip, comprising a semiconductor substrate having opposite first and second surfaces and electrically conductive pillars intended to be connected to elements outside the electronic component, the method comprising the steps of:

[0017] - forming an electrically insulating layer on the second surface of the semiconductor substrate,

[0018] - forming an opening through the insulating layer and continuing through a portion of the thickness of the semiconductor substrate,

[0019] - forming a first portion of the electrically conductive pillar by filling the opening with an electrically conductive material,

[0020] - forming a second portion of the electrically conductive pillar from the first portion of the pillar.

[0021] According to an embodiment, the method comprises the step of forming an electrically insulating layer in the opening before filling the opening with the electrically conductive material.

[0022] According to an embodiment, the method comprises the step of depositing an interface layer, preferably made of TiCu, in the opening between the step of forming the electrically insulating layer and the step of filling the opening with the electrically conductive material. BRIEF DESCRIPTION OF DRAWINGS

[0023] The foregoing features and advantages, as well as others, will be described in detail in the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0024] Figure 1 is a partial and simplified cross-sectional view of an example of an electronic chip;

[0025] Figure 2 is a partial and simplified cross-sectional view of an example of an electronic chip;

[0026] Figure 3 are parts of a structure and simplified cross-sectional views according to embodiments of electronic chips;

[0027] Figure 4 , Figure 5 and Figure 6 are simplified top views and cross-sectional views of different pillars positioned in a substrate according to embodiments of electronic chips (dotted lines show the boundary of the electronic chip formed in the substrate);

[0028] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F , Figure 7G and Figure 7H are parts of a structure and simplified cross-sectional views obtained at different steps of embodiments of a method of manufacturing Figure 2 microchips.

[0029] For better readability of the drawings, the various elements in the drawings are not shown to scale. DETAILED DESCRIPTION

[0030] Similar features in the various figures are denoted by similar reference numerals. In particular, structural and / or functional features common among the various embodiments can have the same reference numerals and can have exactly the same structure, dimensions and material properties.

[0031] For the sake of clarity, only the steps and elements necessary for understanding the embodiments are illustrated and described in detail.

[0032] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, while when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements.

[0033] In the following description, when referring to terms defining an absolute position, such as the terms "edge", "back", "top", "bottom", "left", "right", etc., or terms defining a relative position, such as the terms "above", "below", "upper", "lower", etc., or terms defining a direction, such as the terms "horizontal", "vertical", etc., all refer to the orientation of the drawings, unless otherwise indicated.

[0034] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "around" mean within 10%, preferably within 5%. In addition, the terms "insulated" and "conductive" are considered herein to mean "electrically insulated" and "electrically conductive", respectively.

[0035] Figure 1 is a partial and simplified cross-sectional view of an example of an electronic chip 10.

[0036] The electronic chip 10 comprises:

[0037] - a semiconductor substrate 12 comprising a lower surface 14 (first surface) and an upper surface 16

[0038] (second surface);

[0039] - an insulating layer 18 capable of covering the lower surface 14;

[0040] - an active area 20 in the substrate 12, flush with the upper surface 16, one or more electronic components (not shown) being formed inside and / or on top of the active area 20;

[0041] - an interconnection structure 22 covering the upper surface 16 of the substrate, the interconnection structure 22 comprising an upper surface and a lower surface in contact with the substrate 12, the interconnection structure comprising an insulating layer 24 and conductive tracks 26 in the insulating layer 24, some of the conductive tracks 26 being in contact with the active area 20;

[0042] - openings 28 in the insulating layer 24, each opening exposing a portion of one of the conductive tracks 26; and

[0043] - connection posts 30, two connection posts being shown by way of example in Figure 1 , each post being connected to one of the conductive tracks 26.

[0044] Each connection post 30 comprises a shaft 32 extending along an axis A substantially orthogonal to the upper surface 16. The shaft 32 comprises a base 34 on a side closest to the substrate 12, an end surface 36 on a side furthest from the substrate 12 opposite the base 34, and a sidewall 38 coupling the base 34 to the end surface 36. The connection post 30 further comprises an interface layer 40 interposed between the base 34 and the interconnection structure 22. The post 30 further comprises a finish layer 42 covering the end surface 36 and a block 44 of bonding material covering the finish layer 42.

[0045] The use of connection posts 30 such as shown in Figure 1 may have certain drawbacks. When the connection posts 30 have small dimensions or have a high aspect ratio (also known as form factor), the connection posts 30 can be fragile. In addition, each connection post 30 is mechanically coupled to the interconnection structure 22 only through the interface layer 34.

[0046] In addition, during the manufacturing of such a device, the method comprises a step of etching the interface layer 40 deposited over the whole wafer after the formation of the connection pillars 30 thereon. Now, when the material is etched, the etching extends laterally under the conductive material of the connection pillars 30 (phenomenon known as "undercutting"), which causes the interface layer 34 located under the pillars 30 to be etched partially from its peripheral parts. This makes the coupling between the shaft 32 and the interconnection structure 22 brittle. The risk of tearing of the connection pillars 30 from the connection structure 22 can then be observed to increase. The percentage of loss of contact surface area increases with the decrease in the diameter of the pillars.

[0047] Figure 2 is a partial and simplified cross-sectional view of an example of an electronic chip 50. The electronic chip 50 comprises Figure 1 all the elements of the electronic chip 10 of

[0048] Each connection pillar 60 comprises two parts mechanically fixed to each other:

[0049] - a first part (upper part of the pillar) arranged to protrude from the chip 50 to allow an electrical connection with an external element, such as a housing or another electronic chip, the first part extending or protruding from an upper surface of the insulating layer 24 of the interconnection structure 22 covering the second surface 16 of the substrate 12,

[0050] - a second part (lower part of the pillar) which passes completely through the insulating layer 24 of the interconnection structure 22 and a portion of the substrate 12, the height of the second part being lower than the thickness of the substrate 12.

[0051] More particularly, the first part of the pillar comprises a shaft 62 extending along an axis D substantially orthogonal to the upper surface 16 and to the lower surface of the substrate, the shaft protruding from the insulating layer 24 of the interconnection structure 22 positioned on the upper surface 16 of the substrate 12, the shaft 62 having a base 64 arranged at the level of the upper surface of the interconnection structure 24, an end surface 66 arranged outside the substrate 12 and opposite the base 64, and a lateral wall 68 connecting the base 64 to the end surface 66.

[0052] A finishing layer 72 covers the end surface 66 and is in direct physical contact with the end surface 66.

[0053] A block 74 of bonding material covers the finishing layer 72.

[0054] The base 64 of the first part of the pillar is in direct contact with the second part of the pillar.

[0055] The first part is visible, it protrudes from the substrate. The second part is buried inside the component: not visible during normal use of the electronic component 50. Only cutting the component 50 makes it possible to observe it.

[0056] The second portion of the pillar can be formed of one or more elements 61. These elements are in direct contact with the base 64 of the shaft 62 of the first portion 60 of the pillar.

[0057] The elements 61 comprise a base (or lower surface), a lateral wall and an upper surface. The upper surface is in direct contact with the upper portion of the pillar.

[0058] The elements 61 can have different shapes and / or different dimensions. The shapes and / or dimensions can be identical or different within the same pillar or between different pillars.

[0059] According to different embodiments, the second portion of the pillar 60 can comprise a single element 61( Figure 3 , Figure 4 ) or a plurality of elements 61( Figure 2 , Figure 5 and Figure 6 ).

[0060] According to different embodiments, the second portion can be formed of one cylindrical element 61( Figure 3 and Figure 4 ) or a plurality of cylindrical elements 61( Figure 2 , Figure 5 ). The second portion of the pillar 60 can also be formed of one or more tubular elements 61. The tubular elements can be arranged coaxially( Figure 6 ).

[0061] The cross-sectional area of the elements 61 or the sum of the cross-sectional areas of the elements 61 is preferably less than the cross-sectional area of the shaft 62.

[0062] The elements 61 preferably have a height in the range of 5 pm to 50 pm. For example, they have a height of 10 pm. The average diameter of the elements 61 is preferably in the range of 1 pm to 40 pm. The average diameter of the cylindrical elements is for example 5 pm.

[0063] The average diameter means the diameter of the elements 61 having a circular base with the same surface area as the elements 61.

[0064] Thanks to the elements 61 or the plurality of elements 61 of the second portion of the pillar 60, each pillar 60 is anchored in the substrate 12 over a portion of the thickness of the substrate 12. The mechanical stability of the pillars 60 is improved with respect to the mechanical stability of the pillars 30 as shown in Figure 1 for example. The risk of tearing of the connecting pillars 60 is greatly reduced.

[0065] The electronic chip 50 also comprises an interface layer 70 covering the base and the lateral wall of the elements 61 (i.e. it covers the elements 61 completely except for the upper surface in contact with the base 64 of the shaft 62).

[0066] This interface layer 70 plays the role of a seed layer during the formation of the element 61.

[0067] Since the interface layer 70 covers the element(s) 61, its developed surface area is greater than the surface area of the interface layer 40 in contact with the base 34 of the pillar 30 of the component shown in Figure 1

[0068] Thus, even for small dimensioned pillars, typically having an average diameter of the axis 62 smaller than 50 pm, or even smaller than or equal to 25 pm, or even smaller than or equal to 15 pm, the effect of the undercut of the interface layer 70 under the axis 62 of the pillar 60 is significantly reduced.

[0069] As an example, as Figure 1 shown in the example of the component shown in

[0070] As a non-limiting illustration, for a pillar 60 such as the one shown in Figure 2 having an average diameter of 15 pm, and the interface layer 70 having a thickness of 0.3 pm, if the pillar comprises one element 61, two elements 61 and three elements 61, respectively, each element 61 having a diameter of 5 pm and a height of 10 pm, then the percentage of loss of contact surface area between the pillar 60 and the interface layer 70 due to the undercut will be only approximately 8%, 5% and 3%, respectively.

[0071] An insulating layer 78 is arranged between the interface layer 70 and the substrate 12, so as to insulate the substrate 12 from the pillar 60.

[0072] In addition, the component comprises a connection track 76 (or RDL of a “redistribution layer”) on the interconnection structure 22 and connects the axis 62 of the pillar 60 to one of the conductive tracks 26 in one of the openings 28.

[0073] There is also an interface layer 70 between the connection track 76 and the interconnection structure 22.

[0074] This interface layer 70 also plays the role of a seed layer during the formation of the connection track 76.

[0075] A method of manufacturing such an electronic chip 50 shown in Figures 7A to 7H will now be described. Figure 2 The method comprises at least the following steps:

[0076] The method comprises at least the following steps:

[0077] ​- providing a structure comprising a substrate 12 in which an active area 20 has been formed, conductive tracks 26 being positioned in the substrate 12 or on the upper surface of the substrate 12 and connected to the active area 20,

[0078] - covering the upper surface 16 of the substrate 12 with an insulating layer 24,

[0079] - forming an opening 82 through the insulating layer 24 and extending across a partial thickness of the semiconductor substrate 12,

[0080] - forming a first portion of the electrically conductive pillar 60 by filling the opening 82 with an electrically conductive material,

[0081] - forming a second portion of the electrically conductive pillar 60 from a second portion of the pillar.

[0082] More particularly, the method can comprise the following steps:

[0083] a) forming an insulating layer 24 over a structure comprising a substrate 12 in which an active area 20 has been formed, conductive tracks 26 being positioned in the substrate 12 or on the upper surface of the substrate 12 and connected to the active area 20, the insulating layer 24 covering the conductive tracks 26 and the upper surface 16 of the substrate 12, Figure 7A ),

[0084] b) forming one or more openings 82 at the desired location of each element 61 of the connecting pillar 60, the openings passing through the insulating layer 24 and extending in the substrate 12, Figure 7B ),

[0085] c) forming an insulating layer 78 in the openings 82 to insulate the substrate 12 from the second portion of the pillar, Figure 7C ),

[0086] d) forming an opening 28 in the insulating layer 24 to make the conductive tracks 26 accessible,

[0087] e) covering the structure obtained with an interface layer 70, Figure 7D ),

[0088] f) locally depositing a protective film 80 over the structure to define the area on which the conductive material of the shaft 62 of the pillar 60 is to be deposited and to protect the other areas, Figure 7E ),

[0089] g) depositing an electrically conductive material to form the element(s) 61 of the second portion of the pillar 60, then forming the connecting element 76, Figure 7F ),

[0090] h) locally depositing a protective film 81 over the structure obtained at step f) to define the area on which the conductive material of the shaft 62 of the pillar 60 is to be deposited and to protect the other areas,

[0091] i) growing the shafts 62 of the pillars 60 from the elements 61 Figure 7G ),

[0092] j) forming a facing layer 72 and a block 74 of bonding material on the end surface 66 of the shaft 62 of the pillar 60 Figure 7H ),

[0093] k) removing the protective film 81,

[0094] l) etching the interface layer 70 to electrically insulate the pillars 60 from each other.

[0095] During step a), one or more discrete components, not shown, have been formed inside and / or on top of the active area 20. The (one or more) discrete components are for example selected from transistors, diodes, thyristors, triac, filters, etc.

[0096] According to an embodiment, at this stage of the process, the substrate 12 corresponds to a wafer.

[0097] The substrate 12 is made of for example silicon (Si), silicon carbide (SiC), III-V compounds, in particular gallium nitride (GaN), or II-VI compounds. The substrate 12 can have a single layer or a multilayer structure, for example a structure of the SOI (Silicon On Insulator) type. As an example, the substrate 12 can comprise a layer of GaN covering a silicon support. According to an embodiment, the thickness of the substrate 12 is in the range 50 pm to 300 pm.

[0098] A single active area is shown in the figures, but a plurality of microchips active areas 20 can be formed inside and / or on top of the substrate 12, and the active areas 20 can be identical or different.

[0099] In Figure 7A , the interconnection structure 22 comprises two conductive tracks 26 connected to the active area 20 and an insulating layer 24 covering the conductive tracks 26 and the upper surface 16 of the substrate 12 around the conductive tracks 26.

[0100] More than two conductive tracks 26 can be connected to the active area 20.

[0101] The conductive track 26 is for example made of a material selected from copper, copper alloy, titanium, titanium alloy, titanium nitride, platinum, platinum alloy. It can also be aluminum. According to an embodiment, the thickness of each metal track 26 is in the range 0.5 pm to 1.5 pm.

[0102] The insulating layer 24 can be a multilayer formed of a plurality of insulating layers.

[0103] The insulating layer 24 can be made of a dielectric material, such as an oxide or a nitride, preferably silicon oxide (SiO2), silicon nitride (e.g. Si3N4), silicon oxynitride (e.g. SiO x N y ) or hafnium oxide (HfO2). The insulating layer 24 can also be made of a polymeric material.

[0104] According to an embodiment, the thickness of the insulating layer 24 is in the range 0.5 pm to 1.5 pm.

[0105] Figure 7B A structure is shown, obtained after forming an opening 82 at the desired location of each element 61 of the connecting post 60 (step b). The opening 82 goes completely through the interconnection structure 22 and extends from the upper surface 16 to a partial thickness of the substrate 12. The opening is a blind via (in other words, the opening does not go completely through the substrate 12). The depth of the opening 82 can be in the range 5 pm to 50 pm.

[0106] One or more openings 82 are formed for each post, so as to form one or more elements 61, respectively.

[0107] In the figure, the opening 82 has a circular cross-section. However, the opening 82 can have a square cross-section, a rectangular cross-section or a rectangular cross-section with rounded corners.

[0108] The opening 82 can be formed by laser etching.

[0109] Preferably, the opening 82 is formed by a deep reactive ion etching (DRIE) step.

[0110] To form the opening 82, a mask can be used. The layer 24 is etched through its entire thickness through the opening of the mask. Then, the opening 82 continues through a partial thickness of the substrate 12. The mask can be a resin mask. The insulating layer 24 (e.g. made of oxide) can act as a "hard mask" during the formation of the opening 82 in the substrate 12.

[0111] During step c), an insulating layer 78 is formed in each opening. Figure 7C A structure is shown, obtained.

[0112] The insulating layer 78 covers the side walls and the bottom of the opening 82. The insulating layer 78 can be formed by depositing an insulating layer into the opening 82 or by oxidation of the substrate 12. For example, this step can be performed by thermal oxidation, low thermal oxidation, wet oxidation, plasma enhanced chemical vapor deposition (PECVD). Figure 7C An embodiment is shown, in which the insulating layer is obtained by oxidation of the substrate 12. The thickness of the insulating layer is chosen so as not to close the opening 82. For example, in the range 100 nm to 1 pm.

[0113] For each connection pillar 60 to be formed, an opening 28 is made in the insulating layer 24 to expose one of the conductive tracks 26 (step d). These openings 28 can be formed by using a mask.

[0114] During step e), an interface layer 70 is formed. At this stage of the method, the interface layer 70 covers all the walls of the cavities 82, in particular the side walls and the bottom of the cavities 82, the walls of the openings 28 and the exposed portions of the insulating layer 24 connecting the cavities 82 to the corresponding openings 28.

[0115] The thickness of the interface layer 70 is in the range 10 nm to 1 pm. The interface layer 70 plays the role of seed for the formation of the pillars 60 and of the connection tracks 76 of the connection pillars 60. The interface layer 70 can comprise a layer of titanium or chromium (playing the role of a bonding layer) and a layer of copper (playing the role of a seed layer for the subsequent formation of the shafts 62 and of the connection tracks 76). The interface layer 70 is preferably made of TiCu.

[0116] During step f), protection films 80 are deposited on the structure. They play the role of masks during the formation of the pillars 60, which are formed in the openings of the masks.

[0117] During step g), the element(s) 61 forming the second part of the pillars and the tracks 76 Figure 7F ) are formed.

[0118] For each connection pillar 60 to be formed, each cavity 82 is completely filled with a conductive material, thereby forming the element 61 of the connection pillar 60. When the cavities 82 are filled, the connection part 76 of each connection pillar is formed.

[0119] The conductive material forming the element 61 can be deposited on the interface layer 70 by plasma-enhanced chemical vapor deposition (PECVD) or by atomic layer deposition (ALD).

[0120] Preferably, the conductive material of the element 61 is deposited by ALD. The ALD technique is particularly advantageous for filling openings of small dimensions and / or having a high aspect ratio, i.e. when the ratio of the cavity height to the cavity diameter is high. In this case, the deposition of the conductive material is performed starting from the interface layer 70 in a direction substantially perpendicular to the interface layer 70. The deposition of the conductive material is in particular performed starting from the side walls of the cavities 82.

[0121] The conductive material forming the connection tracks 76 can be deposited on the interface layer 70 by electrodeposition. The growth occurs starting from the interface layer 70.

[0122] The thickness of the interface layer is for example in the range 0.3 to 0.9 pm.

[0123] At step h), protection films 81 are locally formed on the structure obtained at step g).

[0124] The protective film 80 deposited at step f) can be removed before step h), or the protective film 81 of step h) can be deposited on top of the film 80 applied at step f) so as to cover them.

[0125] The protective film 80 formed at step f) and / or the protective film 81 formed at step h) is for example a resin. They can be removed by wet etching ("lift-off").

[0126] The protective film 81 comprises an opening in line with the position of the shaft 62 of the deposited pillar 60 at step g).

[0127] The growth of the first part of the pillar 60 is preferably performed by electrodeposition. The conductive material forming the shaft 62 is deposited from the second part of the pillar 60. The growth occurs in a direction substantially perpendicular to the main surfaces 14 and 16 of the substrate 12. Figure 7G ).

[0128] To form the shaft 62, the conductive material can thus be deposited substantially over a thickness equal to half the average diameter of the element 61. Once formed, the shaft 62 protrudes from the upper surface 16 of the substrate 12.

[0129] The shaft 62 can have a substantially cylindrical shape with an axis Δ, the base being circular, square, rectangular, etc. The average diameter D of the shaft 62 of the pillar 60 is in the range 10 μιη to 150 μιη. According to an embodiment, the end surface 66 is substantially perpendicular to the axis Δ.

[0130] The total height H of the shaft 62 from the base 64 to the end surface 66 is for example in the range 75 μιη to 400 μιη. The height of the shaft 62 protruding from the insulating layer 24 is in the range 25 μιη to 100 μιη. The aspect ratio of the shaft 62, which corresponds to the ratio of the total height H of the shaft 62 to the average diameter D of the shaft 62, is in the range 0.5 to 40.

[0131] The shaft 62, the element 61 and the connection track 76 are preferably made of the same material. The shaft 62, the element 61 and the connection track 76 are made of a metal, for example of copper, nickel, silver, gold or an alloy of these metals. Preferably, they are made of copper.

[0132] At step h), for each connection pillar 60, a layer of finish 72 and a block 74 of bonding material are formed on the end surface 66.

[0133] The thickness of the finishing layer 72 is in the range of 10 nm to 5 pm, for example 3 pm. The finishing layer 72 is made of a conductive material, which improves the bonding of the bump 74. The finishing layer 72 is for example made of a metal, in particular gold, silver, platinum, palladium, nickel, titanium, chromium and / or tantalum. Preferably, it is made of nickel. Such a layer can be deposited by physical vapor deposition (PVD). The finishing layer 72 also makes it possible to avoid oxidation of the end surface 66 of the shaft 62 in the case where the assembly method is not performed under a neutral or reducing atmosphere.

[0134] The material forming the bump 74 depends in particular on the assembly method implemented in order to bond the electronic chip 50 to another element. The assembly method can in particular comprise a soldering step or a sintering step.

[0135] The material forming the bump 74 is for example a solder material. It can be one of tin, silver or an alloy thereof, for example SnAgCu, SnAg or SnAgPb. It can also be a gold-based material (such as SnAu or SnAuCu), a palladium-based material (for example, SnPd or SnPdCu), or a platinum-based material (such as SnPt or SnPtCu).

[0136] The height of the bump 74, measured from the finishing layer 72, can be approximately 25 pm.

[0137] After removal of the protective film 80 (step f), the interface layer 70 positioned between the pillars, more particularly between the connection tracks 76, is removed, preferably by etching (step I). The removal can be performed by wet etching. The etching solution can be a hydrofluoric acid (HF) solution or an ammonia solution. The etching solution will be chosen according to the nature of the passivation layer 24 (for example, oxide or polymer).

[0138] The method can also comprise a cutting step to separate the different electronic chips 50 formed in the same substrate 12.

[0139] At the end of the method, the chips are obtained as shown in Figure 2

[0140] Each individualized electronic chip 50 can then be bonded to an external element, for example a package or another electronic chip.

[0141] Such electronic chips find applications in many industrial fields, and in particular in the automotive and telephony fields.

[0142] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined, and that other variants will occur to the person skilled in the art.

[0143] ​The actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art, based on the functional indications given above.

Claims

1. An electronic component, characterized by, Comprising: a semiconductor substrate having opposite first and second surfaces and electrically conductive pillars configured to be connected to elements outside of an electronic component; an insulating layer covering the second surface of the substrate, wherein a first portion of the electrically conductive pillars protrudes from the insulating layer and a second portion of the electrically conductive pillars passes through the insulating layer and extends down in the semiconductor substrate to a depth less than a thickness of the semiconductor substrate.

2. The electronic component of claim 1, wherein, The second portion of the electrically conductive pillars is formed by one or more cylindrical elements.

3. The electronic component of claim 1, wherein, The second portion of the electrically conductive pillars is formed by a plurality of coaxially arranged tubular elements.

4. The electronic component of claim 1, wherein, The electronic component comprises an electrically insulating layer arranged between the second portion of the electrically conductive pillars and the semiconductor substrate.

5. The electronic component of claim 1, wherein, The electronic component comprises an interface layer in contact with the second portion of the electrically conductive pillars, the interface layer being arranged between the electrically conductive pillars and the electrically insulating layer.

6. The electronic component of claim 1, wherein, The electronic component comprises an active area extending in the semiconductor substrate from the second surface and containing at least one discrete electronic component, each electrically conductive pillar further comprising a connection track extending over the second surface of the semiconductor substrate and electrically connected to the active area.

7. The electronic component of claim 1, wherein, The first portion of the electrically conductive pillars has a height greater than 25 pm.

8. The electronic component of claim 1, wherein The second portion of the electrically conductive pillars has a height of at least 5 pm.

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