Gallium arsenide LED epitaxial structure and LED chip
By introducing a composite buffer layer into the LED chip, the growth direction of crystal defects is changed, which solves the crystal quality and stability problems in high-power red LED chips, improves luminous efficiency and reduces cost, and is suitable for high-power and small-size LEDs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2026-03-31
AI Technical Summary
In existing high-power red LED chips, the crystal quality and stability of the epitaxial layer are affected by substrate scratches and defects, resulting in reduced luminous efficiency. Furthermore, low-defect-density substrates are expensive, and the GaAs buffer layer has limited effectiveness.
The LED epitaxial structure adopts gallium arsenide, including a gallium arsenide substrate, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and a composite buffer layer. By setting a first GaAs buffer layer, a defect growth layer and a defect termination layer, the growth direction of crystal defects is changed to terminate their expansion, thereby reducing costs and improving crystal quality.
It effectively avoids epitaxial layer misalignment and stacking defects, improves crystal quality and luminous efficiency, and is particularly suitable for high-power and small-size LEDs, with relatively low cost.
Smart Images
Figure CN224069051U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of light emitting diode especially relates to a gallium arsenide system LED epitaxial structure and LED chip. BACKGROUND
[0002] With the rapid development of LED technology and the gradual improvement of LED light efficiency, the application of LED is more and more extensive, and people pay more and more attention to the development prospect of LED in display screen. LED chip, as the core component of LED lamp, its function is to convert electric energy into light energy, specifically, including epitaxial wafer and N-type electrode and P-type electrode arranged on the epitaxial wafer respectively. The epitaxial wafer includes P-type semiconductor layer, N-type semiconductor layer and active layer between the N-type semiconductor layer and the P-type semiconductor layer, when current passes through the LED chip, the hole in the P-type semiconductor and the electron in the N-type semiconductor will move to the active layer, and recombine in the active layer, so that the LED chip emits light.
[0003] At present, LED semiconductor chip develops towards high power and high brightness, for example, AlGaInP-based red light LED: during mechanical processing of the substrate, such as slicing, polishing and other processes, the machine will inevitably cause scratches on the surface of the epitaxial substrate, and for high-power red light LED, the crystal defects such as epitaxial layer dislocation and stacking defects formed from the scratches and defects on the surface of the substrate during epitaxy will affect the electron and hole recombination efficiency and reduce the overall component light efficiency; in addition, the working temperature of high-power red light chip is also high, and the crystal quality and stability of each epitaxial layer are required to be high, so it is particularly important to accurately control the doping elements and concentration of each epitaxial layer and reduce lattice defects during epitaxial growth.
[0004] At present, the lattice defects are usually reduced by screening low defect density substrates or growing GaAs buffer layer; however, the two ways have the following disadvantages:
[0005] Because the proportion of low defect density substrate is small during the substrate crystal growth process, the technical difficulty is high, therefore, the cost of low defect density substrate is high. At the same time, because the surface of GaAs substrate is easy to oxidize, the dislocation defects are formed along the lattice direction from the inhomogeneous oxidation layer position during the growth process of subsequent epitaxial material, therefore, even if the GaAs buffer layer structure is grown, there is still a certain dislocation effect on the subsequent formed epitaxial layer, which reduces the crystal quality and stability.
[0006] Therefore, the present application has been specially designed, and the gallium arsenide system LED epitaxial structure and LED chip are produced. CONTENT OF THE UTILITY MODEL
[0007] The utility model discloses a gallium arsenide system LED epitaxial structure and LED chip to improve the crystal quality of LED chip.
[0008] In order to realize above-mentioned purpose, the utility model adopts technical scheme as follows:
[0009] A gallium arsenide system LED epitaxial structure, comprising:
[0010] Gallium arsenide substrate;
[0011] N type semiconductor layer, active layer and P type semiconductor layer are located in the substrate one side surface laminated in proper order;
[0012] Wherein, be equipped with the composite type buffer layer between the gallium arsenide substrate and the N type semiconductor layer;The composite type buffer layer includes the first GaAs buffer layer, defect growth layer and defect termination layer that are arranged in proper order on the gallium arsenide substrate surface, the defect growth layer is used to make the crystal defect of the first GaAs buffer layer enlarge, and the defect termination layer terminates the growth of the crystal defect by changing the growth direction of the crystal defect.
[0013] Preferably, the crystal defect of the first GaAs buffer layer is enlarged by the compression strain caused by the defect growth layer with increased lattice constant formed by reducing temperature.
[0014] Preferably, the defect growth layer includes the first defect growth layer and the second defect growth layer arranged in proper order.
[0015] Preferably, the second GaAs buffer layer is further arranged on the side surface of the defect termination layer away from the defect growth layer.
[0016] Preferably, the lattice constant of the first defect growth layer is greater than the lattice constant of the first GaAs buffer layer, and the growth temperature of the first defect growth layer is less than the growth temperature of the first GaAs buffer layer.
[0017] Preferably, the thickness of the first defect growth layer is less than the thickness of the first GaAs buffer layer.
[0018] Preferably, the lattice constant of the second defect growth layer is greater than the lattice constant of the first defect growth layer, and the growth temperature of the second defect growth layer is less than the growth temperature of the first defect growth layer.
[0019] Preferably, the growth temperature of the defect termination layer is greater than the growth temperature of the first GaAs buffer layer.
[0020] Preferably, the current expansion layer is further arranged on the side surface of the P type semiconductor layer away from the active layer.
[0021] Preferably, an etching stop layer and an N-type ohmic contact layer are further arranged between the composite buffer layer and the N-type semiconductor layer.
[0022] Preferably, the first defect growth layer comprises a GaInP layer.
[0023] Preferably, the second defect growth layer comprises an InGaAs layer.
[0024] Preferably, the defect termination layer comprises an AlGaInP layer.
[0025] The utility model further provides a gallium arsenide system LED chip, include:
[0026] The substrate is arranged on the surface of the substrate.
[0027] The epitaxial structure is obtained by removing the etching stop layer and / or composite buffer layer and gallium arsenide substrate from the gallium arsenide system LED epitaxial structure according to any one of the preceding embodiments.
[0028] According to the technical scheme, the gallium arsenide system LED epitaxial structure comprises a gallium arsenide substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked on the surface of the substrate on one side, wherein a composite buffer layer is arranged between the gallium arsenide substrate and the N-type semiconductor layer, the composite buffer layer comprises a first GaAs buffer layer, a defect growth layer and a defect termination layer which are sequentially arranged on the surface of the gallium arsenide substrate, the defect growth layer is used to expand the crystal defects of the first GaAs buffer layer, and the defect termination layer terminates the growth of the crystal defects by changing the growth direction of the crystal defects. Based on the above arrangement, the crystal defects such as epitaxial layer dislocation, stacking defects and even slip formed from the scratches and defects on the surface of the gallium arsenide substrate can be effectively avoided, the quality of the crystal is improved, and the cost is slightly increased. It is especially suitable for high-power LED and small-size (such as Mini, Micro) LED.
[0029] Secondly, the defect growth layer comprises a first defect growth layer and a second defect growth layer which are sequentially arranged, further, the lattice constant of the second defect growth layer is greater than the lattice constant of the first defect growth layer, and the growth temperature of the second defect growth layer is less than the growth temperature of the first defect growth layer. Based on the above arrangement, the crystal defects can be further expanded and released by the second defect growth layer, and the crystal defects received by the subsequent defect termination layer are maximized and terminated.
[0030] Then, a second GaAs buffer layer is arranged on the side surface of the defect termination layer away from the defect growth layer, so that the subsequent epitaxial growth (N-type semiconductor layer, active layer and P-type semiconductor layer) can be protected again through the second GaAs buffer layer.
[0031] The utility model further provides a gallium arsenide system LED chip, the epitaxial structure of LED chip is obtained by removing the corrosion stop layer and / or composite buffer layer and gallium arsenide substrate to the gallium arsenide system LED epitaxial structure of any one described above, realizes the beneficial effect above at the epitaxial end, and further can provide the luminous efficiency of LED chip. BRIEF DESCRIPTION OF DRAWINGS
[0032] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or prior art, the drawings needed to be used in the embodiment or prior art description will be briefly introduced below, and obviously, the drawings in the following description are only the embodiment of the utility model, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative labor.
[0033] Figure 1 The gallium arsenide system LED epitaxial structure provided by the embodiment of the utility model is shown in the structural diagram.
[0034] Explanation of symbols in the drawing:
[0035] 1, gallium arsenide substrate;
[0036] 2, composite buffer layer;
[0037] 2.1, first GaAs buffer layer;
[0038] 2.2, first defect growth layer;
[0039] 2.3, second defect growth layer;
[0040] 2.4, defect termination layer;
[0041] 2.5, second GaAs buffer layer;
[0042] 3, corrosion stop layer;
[0043] 4, N-type ohmic contact layer;
[0044] 5, N-type semiconductor layer;
[0045] 6, active layer;
[0046] 7, P-type semiconductor layer;
[0047] 8, current spreading layer. DETAILED DESCRIPTION
[0048] To make the content of the utility model more clear, the content of the utility model is further explained below in combination with the drawings. The utility model is not limited to the specific embodiment. Based on the embodiment in the utility model, all other embodiments obtained by the person skilled in the art without making creative labor belong to the scope of protection of the utility model.
[0049] A gallium arsenide LED epitaxial structure, comprising:
[0050] A gallium arsenide substrate 1;
[0051] An N-type semiconductor layer 5, an active layer 6 and a P-type semiconductor layer 7 are sequentially stacked on one side surface of the substrate;
[0052] Wherein, a composite buffer layer 2 is arranged between the gallium arsenide substrate 1 and the N-type semiconductor layer 5; the composite buffer layer 2 comprises a first GaAs buffer layer 2.1, a defect growth layer and a defect termination layer 2.4 which are sequentially arranged on the surface of the gallium arsenide substrate 1; the defect growth layer is used for expanding the crystal defects of the first GaAs buffer layer 2.1; and the defect termination layer 2.4 terminates the growth of the crystal defects by changing the growth direction of the crystal defects.
[0053] Based on the above content, in an embodiment of the present application, the crystal defects of the first GaAs buffer layer 2.1 are expanded by the compression strain caused by the defect growth layer with increased lattice constant formed by reducing the temperature.
[0054] Based on the above content, in an embodiment of the present application, the defect growth layer comprises a first defect growth layer and a second defect growth layer 2.3 which are sequentially arranged.
[0055] Based on the above content, in an embodiment of the present application, a second GaAs buffer layer 2.5 is further arranged on the side surface of the defect termination layer 2.4 away from the defect growth layer.
[0056] Based on the above content, in an embodiment of the present application, the lattice constant of the first defect growth layer is greater than the lattice constant of the first GaAs buffer layer 2.1, and the growth temperature of the first defect growth layer is less than the growth temperature of the first GaAs buffer layer 2.1.
[0057] Based on the above content, in an embodiment of the present application, the thickness of the first defect growth layer is less than the thickness of the first GaAs buffer layer 2.1.
[0058] Based on the above, in one embodiment of the present application, the lattice constant of the second defect growth layer 2.3 is greater than that of the first defect growth layer, and the growth temperature of the second defect growth layer 2.3 is less than that of the first defect growth layer.
[0059] Based on the above, in one embodiment of the present application, the growth temperature of the defect termination layer 2.4 is greater than that of the first GaAs buffer layer 2.1.
[0060] Based on the above, in one embodiment of the present application, a current spreading layer 8 is further provided on the side surface of the P-type semiconductor layer 7 away from the active layer 6.
[0061] Based on the above, in one embodiment of the present application, an etching stop layer 3 and an N-type ohmic contact layer 4 are further provided between the composite buffer layer 2 and the N-type semiconductor layer 5.
[0062] Based on the above, in one embodiment of the present application, the first defect growth layer comprises a GaInP layer.
[0063] Based on the above, in one embodiment of the present application, the second defect growth layer 2.3 comprises an InGaAs layer.
[0064] Based on the above, in one embodiment of the present application, the defect termination layer 2.4 comprises an AlGaInP layer.
[0065] Based on the above, in one embodiment of the present application, the etching stop layer 3 comprises an N-type GaInP etching stop layer 3, the N-type ohmic contact layer 4 comprises an N-type GaAs ohmic contact layer, the N-type semiconductor layer 5 comprises an N-type AlInP layer, the active layer 6 is a superlattice multi-quantum well structure, and the P-type semiconductor layer 7 comprises a P-type AlInP layer, but the present application is not limited thereto.
[0066] The utility model further provides a gallium arsenide system LED chip, include:
[0067] The substrate is provided with an epitaxial structure.
[0068] The epitaxial structure comprises the gallium arsenide system LED epitaxial structure of any one of the above.
[0069] The utility model embodiment further provides a gallium arsenide system LED epitaxial structure's production method, the production method comprises:
[0070] S01, provides a gallium arsenide substrate 1;
[0071] S02、InGaAs buffer layer 2 is deposited on the surface of the GaAs substrate 1; the InGaAs buffer layer 2 comprises a first GaAs buffer layer 2.1, a defect growth layer and a defect termination layer 2.4 arranged in sequence on the surface of the GaAs substrate 1, the defect growth layer is used to expand the crystal defects of the first GaAs buffer layer 2.1, and the defect termination layer 2.4 terminates the growth of the crystal defects by changing the growth direction of the crystal defects;
[0072] Further, the crystal defects of the first GaAs buffer layer 2.1 are expanded by the compressive strain caused by the defect growth layer with increased lattice constant formed at a reduced temperature.
[0073] Further, the defect growth layer comprises a first defect growth layer and a second defect growth layer 2.3 arranged in sequence.
[0074] Further, a second GaAs buffer layer 2.5 is arranged on the side surface of the defect termination layer 2.4 away from the defect growth layer.
[0075] Further, the lattice constant of the first defect growth layer is greater than that of the first GaAs buffer layer 2.1, and the growth temperature of the first defect growth layer is lower than that of the first GaAs buffer layer 2.1.
[0076] Further, the thickness of the first defect growth layer is less than that of the first GaAs buffer layer 2.1.
[0077] Further, the lattice constant of the second defect growth layer 2.3 is greater than that of the first defect growth layer, and the growth temperature of the second defect growth layer 2.3 is lower than that of the first defect growth layer.
[0078] Further, the growth temperature of the defect termination layer 2.4 is greater than that of the first GaAs buffer layer 2.1.
[0079] Further, the first defect growth layer comprises a GaInP layer.
[0080] Further, the second defect growth layer 2.3 comprises an InGaAs layer.
[0081] Further, the defect termination layer 2.4 comprises an AlGaInP layer.
[0082] S03, an etching stop layer 3 and an N-type ohmic contact layer 4 are grown;
[0083] S04, an N-type semiconductor layer 5, an active layer 6 and a P-type semiconductor layer 7 are grown in sequence.
[0084] In summary, specifically, the composite buffer layer 2 is formed by the following steps:
[0085] First, the first GaAs buffer layer 2.1 is formed by high-temperature low-speed growth with a growth temperature of 650-750°C, a growth speed of 2-10 A / s, and a growth time of 1-3 min.
[0086] Second, the first defect growth layer is obtained by low-temperature high-speed growth of a GaInP layer with a growth temperature of 550-650°C, a growth speed of 5-15 A / s, and a growth time of 30-90 s. The purpose is to grow a thin GaInP layer (further, a Ga 0.3 In 0.7 P layer) on the first GaAs buffer layer 2.1 at low temperature and high speed. Since the lattice constants of GaAs / Ga 0.3 In 0.7 P are 5.65 A / 5.74 A, respectively, and the lattice constant is not completely matched due to the accelerated growth and the increase of the crystal cell, the defects on the first GaAs buffer layer 2.1 continue to grow and expand.
[0087] Then, the second defect growth layer 2.3 is obtained by low-temperature high-speed growth of an InGaAs layer (further, an In 0.39 Ga 0.61 As layer) with a growth temperature of 500-600°C, a growth speed of 5-15 A / s, and a growth time of 30-60 s. The purpose is to further grow a thin InGaAs layer (further, an In 0.39 Ga 0.61 As layer) on the GaInP layer (the first defect growth layer) at low temperature and high speed. Since the lattice constants of Ga 0.3 In 0.7 P / In 0.39 Ga 0.61 As are 5.74 A / 5.81 A, respectively, and the lattice constant is not completely matched, the defects of the Ga 0.3 In 0.7 P layer (the first defect growth layer) are further expanded.
[0088] Then, the AlGaInP layer is grown at a high temperature and a low speed by setting a growth temperature of 750-850 DEG C, a growth speed of 2-10 A / s, and a growth time of 2-3 min (further, the Al component of the AlGaInP layer is gradually changed from 0.5 to 0.25), so as to obtain the defect termination layer 2.4. The purpose is that, after the defects on the first GaAs buffer layer 2.1 are exposed after being expanded through the growth of the first defect growth layer and the second defect growth layer 2.3, the temperature is increased and the speed is reduced during the growth of the surface termination layer, and the lattice constant is reduced, so as to change the growth direction of the defect termination layer 2.4 through the stress of the defect termination layer 2.4, and terminate the further growth of the defects.
[0089] Finally, the second GaAs buffer layer 2.5 is formed by growing at a high temperature and a low speed by setting a growth temperature of 650-750 DEG C, a growth speed of 2-10 A / s, and a growth time of 1-3 min.
[0090] It can be known from the technical scheme that the gallium arsenide LED epitaxial structure provided by the utility model has the advantages that the epitaxial layer dislocation, the stacking defect and other crystal defects or even slip caused by the scratches and defects on the surface of the gallium arsenide substrate 1 as the starting point can be effectively avoided, the crystal quality is improved, the cost is slightly increased, and the gallium arsenide LED epitaxial structure is especially suitable for high-power LEDs and small-size (such as Mini and Micro) LEDs.
[0091] Secondly, the defect growth layer comprises the first defect growth layer and the second defect growth layer 2.3 arranged in sequence; further, the lattice constant of the second defect growth layer 2.3 is greater than the lattice constant of the first defect growth layer, and the growth temperature of the second defect growth layer 2.3 is less than the growth temperature of the first defect growth layer. Based on the setting, the crystal defects can be further expanded and released by the second defect growth layer 2.3, so as to maximize the crystal defects received by the subsequent defect termination layer 2.4 and terminate the crystal defects.
[0092] Then, a second GaAs buffer layer 2.5 is further arranged on the side surface of the defect termination layer 2.4 away from the defect growth layer, so that the subsequent epitaxial growth (N-type semiconductor layer 5, active layer 6 and P-type semiconductor layer 7) can be protected again through the second GaAs buffer layer 2.5.
[0093] The utility model further provides a gallium arsenide system LED chip, the epitaxial structure of LED chip is obtained by removing the etching stop layer 3 and / or composite buffer layer 2 and gallium arsenide substrate 1 to the gallium arsenide system LED epitaxial structure of any one described above, realizes the beneficial effect of above-mentioned in epitaxial end, and further can provide the luminous efficiency of LED chip.
[0094] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between various embodiments can be referred to each other.
[0095] It should also be noted that in this document, relationship terms such as first and second are used only to distinguish one entity or operation from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the article or device including the above element.
[0096] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A GaAs-based LED epitaxial structure, characterized by, The application relates to a gallium arsenide substrate, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked on one side surface of the substrate, wherein a composite buffer layer is arranged between the gallium arsenide substrate and the N-type semiconductor layer, the composite buffer layer comprises a first GaAs buffer layer, a defect growth layer and a defect termination layer which are sequentially arranged on the surface of the gallium arsenide substrate, the defect growth layer is used for expanding the crystal defects of the first GaAs buffer layer, and the defect termination layer terminates the growth of the crystal defects by changing the growth direction of the crystal defects. The defect growth layer comprises a first defect growth layer and a second defect growth layer which are sequentially arranged, the first defect growth layer comprises a GaInP layer, the second defect growth layer comprises an InGaAs layer, and the defect termination layer comprises an AlGaInP layer. A second GaAs buffer layer is further arranged on the side surface of the defect termination layer which is away from the defect growth layer. The thickness of the first defect growth layer is smaller than the thickness of the first GaAs buffer layer. An etching stop layer and an N-type ohmic contact layer are further arranged between the composite buffer layer and the N-type semiconductor layer.
2. The GaAs-based LED epitaxial structure according to claim 1, wherein The application further relates to a gallium arsenide LED epitaxial structure which is obtained by removing the etching stop layer and the composite buffer layer and the gallium arsenide substrate from the gallium arsenide LED epitaxial structure according to claim 4.
3. The GaAs-based LED epitaxial structure according to claim 1, wherein 4. The GaAs-based LED epitaxial structure of claim 1, wherein, 5. A gallium arsenide-based LED chip, characterized by,