Topological optimization circuit of power electronic conversion circuit based on potential circuit analysis and application chip

Abstract

The utility model provides a topological optimization circuit of a power electronic conversion circuit based on potential circuit analysis and an application chip, which are characterized in that the output end of a power supply circuit is respectively connected with the input end of a main switch parasitic parameter circuit, the first input end of an auxiliary switch parasitic parameter circuit and the first input end of a buffer network circuit; the first output end of the main switch parasitic parameter circuit is connected with the input end of the driving parasitic parameter circuit, the first output end of the driving parasitic parameter circuit is connected with the second input end of the auxiliary switch parasitic parameter circuit, and the first output end of the auxiliary switch parasitic parameter circuit is connected with the second input end of the buffer network circuit. The output end of the buffer network circuit, the second output end of the auxiliary switch parasitic parameter circuit, the second output end of the driving parasitic parameter circuit and the second output end of the main switch parasitic parameter circuit are jointly connected with the input end of the power supply circuit. According to the utility model, the influence of parasitic parameters on the circuit is considered, and the circuit topology structure and the circuit topology screening operation are simplified.

Description

Technical Field

[0001] This utility model relates to the technical field of power electronics, and in particular to a topology optimization circuit and application chip for power electronic conversion circuits based on latent circuit analysis. Background Technology

[0002] Power electronic converters are indispensable key devices in modern power systems, and the construction and optimization of their topologies is a complex and crucial process. However, for a long time, the creation of many new power electronic converter topologies has mainly relied on the inspiration and experience of designers, without rigorous and followable logic and patterns, making it difficult to carry out innovation and optimization of power electronic converter topologies. Therefore, research on topology optimization circuits for power electronic converters is of great significance.

[0003] Based on a comprehensive evaluation and comparison of current power electronic converter circuit technologies, existing publicly available power electronic converter circuits based on latent circuit analysis mainly suffer from the following problems: First, with the increasing frequency of power electronic converter circuits, parasitic parameters have a significant impact on their performance. However, existing power electronic converter circuits are not designed to closely reflect actual conditions and lack a parasitic parameter model to consider the influence of all parasitic parameters. Second, power electronic converter topologies are diverse, each with its own characteristics and applicable scope. Current technologies primarily rely on referencing and adapting existing power electronic circuit topologies, making modifications and adjustments accordingly. This includes combining power electronic converters with the same or different functions... Sub-circuit modules are cascaded and combined to construct novel or optimized topologies to achieve performance optimization. This method can improve the flexibility and scalability of power electronic circuit topology design, and facilitate the implementation of complex functions and system integration. However, the circuit topology is usually complex, functionally redundant, and mainly relies on the designer's experience and inspiration, and is greatly affected by subjective factors. Third, the main methods of existing technology for constructing and optimizing power electronic conversion circuit topologies also include using algorithms such as random topology generation, heuristic topology generation, and knowledge-based topology generation. A large number of potential topologies are automatically generated by computer programs, and then topologies that meet certain conditions and requirements are selected for further analysis and evaluation. However, the number of generated topologies is large, and the process of screening them one by one is complicated, that is, circuit topology screening is cumbersome. Summary of the Invention

[0004] To address the problems of existing technologies that fail to consider the influence of parasitic parameters, have complex circuit topologies, and require cumbersome topology selection, this invention proposes a topology optimization circuit and application chip for power electronic conversion circuits based on latent circuit analysis. This design considers the influence of parasitic parameters on the circuit, simplifying the circuit topology structure and the circuit topology selection process.

[0005] To achieve the above-mentioned technical effects, the technical solution of this utility model is as follows:

[0006] A topology optimization circuit for a power electronic converter circuit based on latent circuit analysis includes: a power supply circuit, a main switch parasitic parameter circuit, a drive parasitic parameter circuit, an auxiliary switch parasitic parameter circuit, and a buffer network circuit.

[0007] The output terminal of the power supply circuit is connected to the input terminal of the main switch parasitic parameter circuit, the first input terminal of the auxiliary switch parasitic parameter circuit, and the first input terminal of the buffer network circuit, respectively. The first output terminal of the main switch parasitic parameter circuit is connected to the input terminal of the driving parasitic parameter circuit. The first output terminal of the driving parasitic parameter circuit is connected to the second input terminal of the auxiliary switch parasitic parameter circuit. The first output terminal of the auxiliary switch parasitic parameter circuit is connected to the second input terminal of the buffer network circuit. The output terminals of the buffer network circuit, the auxiliary switch parasitic parameter circuit, the driving parasitic parameter circuit, and the main switch parasitic parameter circuit are all connected to the input terminal of the power supply circuit.

[0008] Preferably, the main switch parasitic parameter circuit includes a main switch first parasitic inductance circuit, a main switch S1, and a main switch second parasitic inductance circuit. The output terminal of the power supply circuit is connected to the input terminal of the main switch first parasitic inductance circuit, the output terminal of the main switch first parasitic inductance circuit is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input terminal of the driving parasitic parameter circuit, the source of the main switch S1 is connected to the input terminal of the main switch second parasitic inductance circuit, and the output terminal of the main switch second parasitic inductance circuit is connected to the input terminal of the power supply circuit.

[0009] Preferably, the first parasitic inductance circuit of the main switch includes first parasitic inductors connected in series. L d_ex1 Second parasitic inductance L d_in1 The second parasitic inductance circuit of the main switch includes a third parasitic inductor connected in series. L s_in1 and the fourth parasitic inductance L d_ex1 The output terminal of the power supply circuit is connected to the first parasitic inductor. L d_ex1 One end, the first parasitic inductance L d_ex1 The other end is connected to the second parasitic inductor L d_in1 One end, the second parasitic inductance L d_in1The other end is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input of the parasitic parameter driving circuit, and the source of the main switch S1 is connected to the third parasitic inductor. L s_in1 One end, the third parasitic inductor L s_in1 The other end is connected to the fourth parasitic inductor L d_ex1 One end, the fourth parasitic inductor L d_ex1 The other end is connected to the input terminal of the power supply circuit.

[0010] Preferably, the driving parasitic parameter circuit includes a first parasitic resistor. R g1 , drive circuit and second parasitic resistance R g2 The gate of the main switch S1 is connected to the first parasitic resistor. R g1 One end, the first parasitic resistance R g1 The other end is connected to the input terminal of the drive circuit, and the first output terminal of the drive circuit is connected to the second parasitic resistor. R g2 One end, the second parasitic resistance R g2 The other end is connected to the second input terminal of the auxiliary switch parasitic parameter circuit, and the second output terminal of the drive circuit is connected to the input terminal of the power supply circuit.

[0011] Preferably, the auxiliary switch parasitic parameter circuit includes an auxiliary switch first parasitic inductance circuit, an auxiliary switch S2, and an auxiliary switch second parasitic inductance circuit. The output terminal of the driving parasitic parameter circuit is connected to the gate of the auxiliary switch S2, the drain of the auxiliary switch S2 is connected to the first input terminal of the auxiliary switch first parasitic inductance circuit, the second input terminal of the auxiliary switch first parasitic inductance circuit is connected to the output terminal of the power supply circuit, the output terminal of the first parasitic inductance circuit is connected to the input terminal of the buffer network circuit, and the output terminal of the buffer network circuit is connected to the input terminal of the power supply circuit.

[0012] Preferably, the auxiliary switch first parasitic inductance circuit includes a fifth parasitic inductor connected in series. L r Sixth parasitic inductance L d_ex2 and the seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductance circuit includes a ninth parasitic inductor connected in series. L s_in2 and the tenth parasitic inductance L s_ex2The output terminal of the driving parasitic parameter circuit is connected to the gate of the auxiliary switch S2, and the drain of the auxiliary switch S2 is connected to the seventh parasitic inductor. L d_in2 One end, the seventh parasitic inductor L d_in2 The other end is connected to the sixth parasitic inductor L d_ex2 One end, the sixth parasitic inductor L d_ex2 The other end is connected to the input of the buffer network circuit and the fifth parasitic inductor, respectively. L r One end, the fifth parasitic inductor L r The other end is connected to the output terminal of the power supply circuit, and the source of the auxiliary switch S2 is connected to the ninth parasitic inductor. L s_in2 One end, the ninth parasitic inductor L s_in2 The other end is connected to the tenth parasitic inductor L s_ex2 One end, the tenth parasitic inductor L s_ex2 The other end is connected to the input terminal of the power supply circuit.

[0013] Preferably, the buffer network circuit includes a first buffer parameter circuit, a second buffer parameter circuit, and a feedback capacitor. C o and buffer resistor R o The first buffer parameter circuit includes a first buffer capacitor connected in parallel. C D1 and the first diode D 1. The second buffer parameter circuit includes a second buffer capacitor connected in parallel. C D2 Second diode D 2. First buffer capacitor C D1 one end and the first diode D The positive terminals of capacitors 1 and 2 are connected together to the output terminal of the power supply circuit, and the first buffer capacitor is also connected to the output terminal. C D1 The other end is connected to the first diode. D The negative terminal of 1, the second buffer capacitor C D2 One end and the second diode D The positive terminals of 2 are connected together to the fifth parasitic inductor. L r and the sixth parasitic inductor L d_ex2 One end, the second buffer capacitor C D2The other end is connected to the second diode. D The negative terminal of 2, the first diode D The negative terminal of 1 and the second diode D The negative terminals of 2 are connected together to the feedback capacitor. C o and buffer resistor R o One end, feedback capacitor C o and buffer resistor R o The other end is connected to the input terminal of the power supply circuit.

[0014] Preferably, the buffer network circuit includes a first buffer parameter circuit, a second buffer parameter circuit, and a third diode. D 3. Third buffer capacitor C 3. Feedback capacitor C o and buffer resistor R o The first buffer parameter circuit includes a first buffer capacitor connected in parallel. C D1 and the first diode D 1. The second buffer parameter circuit includes a second buffer capacitor connected in parallel. C D2 Second diode D 2. First buffer capacitor C D1 One end, the first diode D The positive terminal of 1 and the third buffer capacitor C One end of 3 is connected to the output terminal of the power supply circuit, and the first buffer capacitor is also connected. C D1 The other end is connected to the first diode. D The negative terminal of 1, the second buffer capacitor C D2 One end, the second diode D The positive terminal of 2 and the third buffer capacitor C The other end of 3 is connected to the third diode. D The negative terminal of 3, the third diode D The positive terminals of 3 are respectively connected to the fifth parasitic inductor. L r and the sixth parasitic inductor L d_ex2 One end, the second buffer capacitor C D2 The other end is connected to the second diode. D The negative terminal of 2, the first diode D The negative terminal of 1 and the second diode D The negative terminals of 2 are connected together to the feedback capacitor.C o and buffer resistor R o One end, feedback capacitor C o and buffer resistor R o The other end is connected to the input terminal of the power supply circuit.

[0015] Preferably, the power supply circuit includes a power supply. U I Resistive elements R L and inductor L The power supply U I Resistive elements R L and inductor L Connected in series.

[0016] This invention also proposes an application chip for a topology optimization circuit of a power electronic conversion circuit based on latent circuit analysis, wherein the application chip is equipped with the topology optimization circuit of the power electronic conversion circuit based on latent circuit analysis as described above.

[0017] Compared with the prior art, the beneficial effects of this utility model's technical solution are:

[0018] This invention proposes a topology optimization circuit and application chip for power electronic converter circuits based on latent circuit analysis. Firstly, by integrating the main switch parasitic parameter circuit, the drive parasitic parameter circuit, the auxiliary switch parasitic parameter circuit, and the buffer network circuit, a topology optimization circuit is formed as a parasitic parameter model for the power electronic converter circuit. This effectively reduces the impact of parasitic parameters on the topology optimization circuit, providing an analytical basis for topology optimization. Secondly, the power supply circuit provides operating power to the topology optimization circuit. The drive parasitic parameter circuit aims to operate by driving the main switch parasitic parameter circuit and the auxiliary switch parasitic parameter circuit. The main switch parasitic parameter circuit is used to simulate the impact of the main switch parasitic parameters on the circuit, and the auxiliary switch... The parasitic parameter circuit receives signals from the driving parasitic parameter circuit and simulates the influence of the parasitic parameters of the auxiliary switch on the signals. Then, the buffer network circuit receives signals from the auxiliary switch parasitic parameter circuit, reducing voltage and current stress during the auxiliary switching process. The output of the buffer network circuit, together with the outputs of the main switch parasitic parameter circuit, the driving parasitic parameter circuit, and the auxiliary switch parasitic parameter circuit, is connected to the power input terminal to form a closed-loop system. This effectively simplifies the complex circuit topology and makes circuit topology selection easier. Furthermore, the topology optimization circuit of this invention performs potential circuit analysis by considering the influence of parasitic parameters, providing a theoretical basis for the research and application of power electronic conversion circuit topologies. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating the topology optimization circuit of a power electronic conversion circuit based on latent circuit analysis proposed in an embodiment of this utility model.

[0020] Figure 2 This is a flowchart illustrating the underlying circuit analysis principle proposed in the embodiments of this utility model.

[0021] Figure 3 This is another structural block diagram of a topology optimization circuit for a power electronic conversion circuit based on latent circuit analysis proposed in an embodiment of this utility model.

[0022] Figure 4 This diagram illustrates the topology optimization circuit connection of a power electronic conversion circuit based on latent circuit analysis, as proposed in this embodiment of the invention.

[0023] Figure 5 The diagram shows the working waveforms of a topology optimization circuit for a power electronic conversion circuit based on latent circuit analysis proposed in this embodiment of the present invention.

[0024] Figure 6 This diagram illustrates the switching process of a topology optimization circuit for a power electronic conversion circuit based on latent circuit analysis, as proposed in an embodiment of this utility model.

[0025] Figure 7 This diagram shows another connection of the topology optimization circuit of a power electronic conversion circuit based on latent circuit analysis proposed in this embodiment of the present invention.

[0026] Figure 8 This illustrates the topology optimization diagram of the topology optimization circuit proposed in this embodiment of the invention.

[0027] Figure 9 This diagram shows another working waveform of a topology optimization circuit for a power electronic conversion circuit based on latent circuit analysis proposed in this embodiment of the present invention.

[0028] Figure 10 This diagram illustrates another switching process of a topology optimization circuit for a power electronic conversion circuit based on latent circuit analysis, as proposed in this embodiment of the invention.

[0029] 1. Power supply circuit; 2. Main switch parasitic parameter circuit; 21. Main switch first parasitic inductance circuit; 22. Main switch second parasitic inductance circuit; 3. Drive parasitic parameter circuit; 4. Auxiliary switch parasitic parameter circuit; 41. Auxiliary switch first parasitic inductance circuit; 42. Auxiliary switch second parasitic inductance circuit; 5. Buffer network circuit; 51. First buffer parameter circuit; 52. Second buffer parameter circuit. Detailed Implementation

[0030] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent.

[0031] It is understandable to those skilled in the art that some well-known details may be omitted from the accompanying drawings;

[0032] The technical solution of this utility model will be further described below with reference to the accompanying drawings and embodiments.

[0033] Example 1

[0034] like Figure 1 As shown, this embodiment proposes a topology optimization circuit for power electronic conversion circuits based on latent circuit analysis, including: power supply circuit 1, main switch parasitic parameter circuit 2, drive parasitic parameter circuit 3, auxiliary switch parasitic parameter circuit 4, and buffer network circuit 5.

[0035] The output terminal of the power supply circuit 1 is connected to the input terminal of the main switch parasitic parameter circuit 2, the first input terminal of the auxiliary switch parasitic parameter circuit 4, and the first input terminal of the buffer network circuit 5, respectively. The first output terminal of the main switch parasitic parameter circuit 2 is connected to the input terminal of the driving parasitic parameter circuit 3. The first output terminal of the driving parasitic parameter circuit 3 is connected to the second input terminal of the auxiliary switch parasitic parameter circuit 4. The first output terminal of the auxiliary switch parasitic parameter circuit 4 is connected to the second input terminal of the buffer network circuit 5. The output terminal of the buffer network circuit 5, the second output terminal of the auxiliary switch parasitic parameter circuit 4, the second output terminal of the driving parasitic parameter circuit 3, and the second output terminal of the main switch parasitic parameter circuit 2 are all connected to the input terminal of the power supply circuit 1.

[0036] This embodiment proposes a topology optimization circuit for power electronic converter circuits based on latent circuit analysis. First, by integrating the main switch parasitic parameter circuit, the drive parasitic parameter circuit, the auxiliary switch parasitic parameter circuit, and the buffer network circuit, a topology optimization circuit is formed as a parasitic parameter model of the power electronic converter circuit. This effectively reduces the impact of parasitic parameters on the topology optimization circuit and provides an analytical basis for topology optimization. Second, the power supply circuit provides operating power to the topology optimization circuit. The purpose of the drive parasitic parameter circuit is to drive the main switch parasitic parameter circuit and the auxiliary switch parasitic parameter circuit. The main switch parasitic parameter circuit simulates the impact of the main switch's parasitic parameters on the circuit, while the auxiliary switch parasitic parameter circuit receives signals from the drive parasitic parameter circuit and simulates the parasitic parameters of the auxiliary switch. The influence of parasitic parameters on the signal is considered, and then the buffer network circuit receives the signal from the auxiliary switch parasitic parameter circuit, reducing the voltage and current stress during the auxiliary switching process. The output of the buffer network circuit, together with the outputs of the main switch parasitic parameter circuit, the drive parasitic parameter circuit, and the auxiliary switch parasitic parameter circuit, is connected to the power input terminal to form a closed-loop system, which effectively simplifies the complex circuit topology and makes circuit topology selection easier. Furthermore, the topology optimization circuit of this invention performs potential circuit analysis by considering the influence of parasitic parameters, providing a theoretical basis for the research and application of power electronic conversion circuit topology. The temperature-compensated RC oscillator circuit of this invention is set on the application chip, which is suitable for various power electronic conversion systems that require high efficiency, low loss, and fast dynamic response.

[0037] See Figure 2 The underlying circuit analysis principle of the topology optimization circuit proposed in this embodiment is as follows:

[0038] First, a topology optimization circuit is established as the parasitic parameter model of the power electronic converter circuit by integrating the main switch parasitic parameter circuit, the drive parasitic parameter circuit, the auxiliary switch parasitic parameter circuit, and the buffer network circuit. Second, modal analysis is performed on the topology optimization circuit as the parasitic parameter model of the power electronic converter circuit to obtain the modal analysis results. The modal analysis results are compared with the normal operating mode threshold in the traditional circuit analysis results to identify modal analysis results that differ from the normal operating mode threshold. These identified modal analysis results are defined as potential operating modes. Then, the output characteristics, switching characteristics, and efficiency of the topology optimization circuit are analyzed. The characteristics are analyzed to obtain the impact of potential operating modes on the topology optimization circuit. Next, the conditions for the occurrence of these potential operating modes are analyzed to determine their excitation conditions. Finally, if the impact of the potential operating modes on the topology optimization circuit is positive, the excitation conditions are enabled through parameter design and topology improvement. If the impact of the potential operating modes on the topology optimization circuit is negative, the satisfaction of the excitation conditions is suppressed through parameter design and topology improvement, resulting in the topology optimization circuit, and the topology optimization ends.

[0039] Example 2

[0040] See Figure 3 and Figure 4 The power supply circuit 1 includes a power supply. U I Resistive elements R L and inductor L The power supply U I Resistive elements R L and inductor L The power supplies are connected in series. U I The output terminal is connected to a resistor element. R L The input terminal, the resistor element R L The output terminal is connected to an inductor. L Input terminal, inductor L The output terminals are respectively connected to the input terminals of the main switch parasitic parameter circuit 2, the first input terminal of the auxiliary switch parasitic parameter circuit 4, and the first input terminal of the buffer network circuit 5. The output terminals of the buffer network circuit 5, the second output terminal of the auxiliary switch parasitic parameter circuit 4, the second output terminal of the drive parasitic parameter circuit 3, and the second output terminal of the main switch parasitic parameter circuit 2 are all connected to the input terminal of the power supply circuit 1. A resistor is used as the input terminal. R L and inductorL For power supply U I The output is preprocessed, which helps to smooth power fluctuations and limit startup current surges. Through interaction with the main switch parasitic parameter circuit, the auxiliary switch parasitic parameter circuit 4, and the buffer network circuit 5, the stability and reliability of the overall circuit are enhanced, providing a more stable and controllable power environment for the entire topology optimization circuit.

[0041] The main switch parasitic parameter circuit 2 includes a main switch first parasitic inductance circuit 21, a main switch S1, and a main switch second parasitic inductance circuit 22. The output terminal of the power supply circuit 1 is connected to the input terminal of the main switch first parasitic inductance circuit 21, the output terminal of the main switch first parasitic inductance circuit 21 is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input terminal of the drive parasitic parameter circuit 3, the source of the main switch S1 is connected to the input terminal of the main switch second parasitic inductance circuit 22, and the output terminal of the main switch second parasitic inductance circuit 22 is connected to the input terminal of the power supply circuit 1.

[0042] The main switch first parasitic inductance circuit 21 includes first parasitic inductors connected in series. L d_ex1 Second parasitic inductance L d_in1 The second parasitic inductance circuit 22 of the main switch includes a third parasitic inductor connected in series. L s_in1 and the fourth parasitic inductance L d_ex1 The output terminal of the power supply circuit 1 is connected to the first parasitic inductor. L d_ex1 One end, the first parasitic inductance L d_ex1 The other end is connected to the second parasitic inductor L d_in1 One end, the second parasitic inductance L d_in1 The other end is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input of the parasitic parameter driving circuit 3, and the source of the main switch S1 is connected to the third parasitic inductor. L s_in1 One end, the third parasitic inductor L s_in1 The other end is connected to the fourth parasitic inductor L d_ex1 One end, the fourth parasitic inductor L d_ex1 The other end is connected to the input terminal of power supply circuit 1. The main switch S1 contains a first inter-pole parasitic capacitance C. ds1 Parasitic capacitance C between the second electrode gd1 Parasitic capacitance C between the third and third electrodes gs1The second inter-electrode parasitic capacitance C gd1 Parasitic capacitance C between the third and third electrodes gs1 After being connected in series, the parasitic capacitance C between the first electrode and the first electrode ds1 Parallel connection; here, the main switch parasitic parameter circuit of the main switch S1 is accurately modeled, including the first parasitic inductance. L d_ex1 Second parasitic inductance L d_in1 Third parasitic inductance L s_in1 and the fourth parasitic inductance L d_ex1 and the first inter-pole parasitic capacitance C inside the main switch S1 ds1 Parasitic capacitance C between the second electrode gd1 Parasitic capacitance C between the third and third electrodes gs1 This approach achieves a comprehensive consideration of the parasitic parameters of the main switch in the power electronic conversion circuit. The establishment of the main switch parasitic parameter circuit not only helps to accurately predict and analyze the voltage and current waveforms and their dynamic behavior in the circuit, but also effectively evaluates the actual impact of the main switch S1 parasitic parameters on the overall circuit performance (such as switching speed, energy loss and stability). By optimizing the above parasitic parameters in the main switch parasitic parameter circuit, the overall efficiency of the main switch S1 circuit can be significantly improved, unnecessary energy loss can be reduced, and the main switch S1 circuit can be ensured to operate stably under various operating conditions, thereby meeting the design requirements of high-performance power electronic conversion systems.

[0043] The driving parasitic parameter circuit 3 includes a first parasitic resistor. R g1 , drive circuit and second parasitic resistance R g2 The gate of the main switch S1 is connected to the first parasitic resistor. R g1 One end, the first parasitic resistance R g1 The other end is connected to the input terminal of the drive circuit, and the first output terminal of the drive circuit is connected to the second parasitic resistor. R g2 One end, the second parasitic resistance R g2The other end is connected to the second input terminal of the auxiliary switch parasitic parameter circuit 4, and the second output terminal of the drive circuit is connected to the input terminal of the power supply circuit 1. Here, the drive parasitic parameter circuit 3 receives the signal from the main switch parasitic parameter circuit 2, amplifies or converts the signal through its internal drive circuit, and then transmits the processed signal to the auxiliary switch parasitic parameter circuit 4 to control the switching state of the auxiliary switch. At the same time, the drive parasitic parameter circuit 3 also forms a loop with the power supply circuit 1 through its second output terminal to ensure the stability of the circuit's drive energy supply and signal transmission. The auxiliary switch S2 is provided with a fourth inter-pole parasitic capacitor C. ds2 Parasitic capacitance C between the fifth electrode gd2 Parasitic capacitance C between the sixth and sixth electrodes gs2 The parasitic capacitance C between the fifth electrodes gd2 Parasitic capacitance C between the sixth and sixth electrodes gs2 Parasitic capacitance C between the series connection and the fourth electrode ds2 in parallel;

[0044] The auxiliary switch parasitic parameter circuit 4 includes an auxiliary switch first parasitic inductance circuit 41, an auxiliary switch S2, and an auxiliary switch second parasitic inductance circuit 42. The output terminal of the driving parasitic parameter circuit 3 is connected to the gate of the auxiliary switch S2. The drain of the auxiliary switch S2 is connected to the first input terminal of the auxiliary switch first parasitic inductance circuit 41. The second input terminal of the auxiliary switch first parasitic inductance circuit 41 is connected to the output terminal of the power supply circuit 1. The output terminal of the first parasitic inductance circuit 41 is connected to the input terminal of the buffer network circuit 9. The output terminal of the buffer network circuit 9 is connected to the input terminal of the power supply circuit 1.

[0045] The auxiliary switch first parasitic inductance circuit 41 includes a fifth parasitic inductor connected in series. L r Sixth parasitic inductance L d_ex2 and the seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductance circuit 42 includes a ninth parasitic inductor connected in series. L s_in2 and the tenth parasitic inductance L s_ex2 The output terminal of the driving parasitic parameter circuit 3 is connected to the gate of the auxiliary switch S2, and the drain of the auxiliary switch S2 is connected to the seventh parasitic inductor. L d_in2 One end, the seventh parasitic inductor L d_in2 The other end is connected to the sixth parasitic inductor L d_ex2 One end, the sixth parasitic inductor L d_ex2 The other end is connected to the input of the buffer network circuit 9 and the fifth parasitic inductor, respectively.L r One end, the fifth parasitic inductor L r The other end is connected to the output terminal of power supply circuit 1, and the source of auxiliary switch S2 is connected to the ninth parasitic inductor. L s_in2 One end, the ninth parasitic inductor L s_in2 The other end is connected to the tenth parasitic inductor L s_ex2 One end, the tenth parasitic inductor L s_ex2 The other end is connected to the input terminal of power supply circuit 1. Here, the auxiliary switch parasitic parameter circuit 4 includes an auxiliary switch first parasitic inductance circuit and an auxiliary switch second parasitic inductance circuit. The auxiliary switch first parasitic inductance circuit is composed of a fifth parasitic inductor. L r Sixth parasitic inductance L d_ex2 and the seventh parasitic inductance L d_in2 The auxiliary switch second parasitic inductor circuit is composed of a series connection and consists of the ninth parasitic inductor. L s_in2 and the tenth parasitic inductance L s_ex2 Composed of series connections, the parasitic inductance in the auxiliary switch parasitic parameter circuit 4 accurately simulates the complex parasitic effects of the auxiliary switch S2 in actual power electronic conversion. This design not only improves the accuracy of the auxiliary switch parasitic parameter circuit 4, but also effectively manages the voltage and current changes during the switching process of the auxiliary switch S2 through the fine configuration of the parasitic inductance, reducing switching losses and electromagnetic interference. Furthermore, by combining the parasitic inductance with the buffer network circuit, the transient response and energy recovery mechanism of the circuit are optimized, thereby significantly improving the efficiency and stability of the entire power electronic conversion circuit.

[0046] The buffer network circuit 5 includes a first buffer parameter circuit 51, a second buffer parameter circuit 52, and a feedback capacitor. C o and buffer resistor R o The first buffer parameter circuit 51 includes a first buffer capacitor connected in parallel. C D1 and the first diode D 1. The second buffer parameter circuit 52 includes a second buffer capacitor connected in parallel. C D2 Second diode D 2. First buffer capacitor C D1 one end and the first diode DThe positive terminal of 1 is connected to the output terminal of power supply circuit 1, and the first buffer capacitor is connected to the output terminal of power supply circuit 1. C D1 The other end is connected to the first diode. D The negative terminal of 1, the second buffer capacitor C D2 One end and the second diode D The positive terminals of 2 are connected together to the fifth parasitic inductor. L r and the sixth parasitic inductor L d_ex2 One end, the second buffer capacitor C D2 The other end is connected to the second diode. D The negative terminal of 2, the first diode D The negative terminal of 1 and the second diode D The negative terminals of 2 are connected together to the feedback capacitor. C o and buffer resistor R o One end, feedback capacitor C o and buffer resistor R o The other end is connected to the input terminal of power supply circuit 1.

[0047] Among them, the main switch S 1 and auxiliary switch S Both use MOSFET transistors for the main switch. S 1 and auxiliary switch S 2. Inter-electrode parasitic capacitance was considered ( C ds , C gs , C gd Parasitic inductance ( L d , L s ), driving parasitic resistance ( R g Parasitic parameters such as ) and anti-parallel diodes, among which, the main switch S The parasitic parameters of 1 are all prefixed with 1, auxiliary switch S The parasitic parameters of 2 are all prefixed with 2; first buffer capacitor C D1 Second buffer capacitor C D2 respectively with D 1 and D 2. Parallel connection. D 1 and D The parasitic inductance of 2 can be concentrated in the stray inductance at the drain terminal of the MOSFET.L d1 and L d2 Middle. Second parasitic resistance R g2 The auxiliary switch includes the first parasitic inductance circuit 41, the second buffer parameter circuit 52, and the first inter-electrode parasitic capacitance C. ds1 It forms a low-loss buffer to provide a soft-switching environment for the main switch S1.

[0048] right Figure 4 Modal analysis of the topology optimization circuit shown reveals that it has 10 operating modes within one cycle, as follows: Figure 5 As shown, modes 4, 6 and 9 are working modes that differ from normal working modes, i.e., potential working modes. Figure 6 for Figure 5 The switching process in the circuit. It can be seen that the inductor current... i Lr exist t 5- t During period 8, it flows through D2 and C D2 This results in severe waveform distortion, increased circulating current loss, and reduced converter efficiency. Although the main switch S1 implements a soft-switching process, the auxiliary switch S2 conducts under high voltage conditions and turns off under high current conditions, still incurring significant switching losses. This severely impacts the system's performance.

[0049] Example 3

[0050] This embodiment proposes further optimization of the buffer network circuit 5 proposed in the above embodiment, with the aim of improving the inductor current. i Lr Waveform distortion and auxiliary switches S To improve the overall performance of the circuit by optimizing the switching environment (2), the specific steps are as follows: Figure 4 During the operation of the topology optimization circuit shown, existing potential operating modes 4 and 5 are introduced. Simultaneously, the buffer network circuit 5 of the topology optimization circuit is improved as follows: Figure 7 That is, in D 1 and D The positive terminals of 2 are connected. C 3; D 2 Anode and L r A third diode is connected in series between them. D 3, D 3 represents a fast recovery diode.

[0051] More specifically, the buffer network circuit 5 includes a first buffer parameter circuit 51, a second buffer parameter circuit 52, and a third diode. D3. Third buffer capacitor C 3. Feedback capacitor C o and buffer resistor R o The first buffer parameter circuit 51 includes a first buffer capacitor connected in parallel. C D1 and the first diode D 1. The second buffer parameter circuit 52 includes a second buffer capacitor connected in parallel. C D2 Second diode D 2. First buffer capacitor C D1 One end, the first diode D The positive terminal of 1 and the third buffer capacitor C One end of 3 is connected to the output terminal of power supply circuit 1, and the first buffer capacitor C D1 The other end is connected to the first diode. D The negative terminal of 1, the second buffer capacitor C D2 One end, the second diode D The positive terminal of 2 and the third buffer capacitor C The other end of 3 is connected to the third diode. D The negative terminal of 3, the third diode D The positive terminals of 3 are respectively connected to the fifth parasitic inductor. L r and the sixth parasitic inductor L d_ex2 One end, the second buffer capacitor C D2 The other end is connected to the second diode. D The negative terminal of 2, the first diode D The negative terminal of 1 and the second diode D The negative terminals of 2 are connected together to the feedback capacitor. C o and buffer resistor R o One end, feedback capacitor C o and buffer resistor R o The other end is connected to the input terminal of power supply circuit 1.

[0052] The optimized topology is analyzed as follows: Let... C 3>> C D2 , C 3>> C D3 , C D3 forD The junction capacitance is 3. The operation process and switching states of each mode of the improved topology optimization circuit are shown in Table 1.

[0053] Table 1. Operating modes and switching states of the improved topology optimization circuit.

[0054]

[0055] See Figure 8 In auxiliary switch S 2. At the moment of shutdown u Cds2 Start charging, C 1, C D2 , C D3 The buffer capacitor network and auxiliary switch are composed of S 2's own parasitic capacitance C e2 Under the action of auxiliary switch S 2. Achieve zero-voltage shutdown. t Before time 4, the voltage at node A was insufficient to make D 2 is on, during this period, L r Energy through D 3 branch roads C 3. Transfer. Settings L r The inductance value is large enough that when the auxiliary switch S2 is turned off, L r Energy storage can enable C voltage on 3 u C3 The output voltage is reached. u C3 After reaching the output voltage, L r The remaining energy is passed through D 2. The current is transferred to the output terminal until it is fully released, and remains zero until the auxiliary switch S2 is turned on in the next cycle. At this time, the original mode 6 is similar to the structure of the switching stage of a normal Boost circuit, and its duration depends on the switching transistor. S 1. Switch control. In t 7-hour shutdown S 1. Then proceed to the next stage: under the influence of input, C ds1 Being charged, C 1. Discharge. In this mode, all switches and diodes are in the off state. The simulation waveform of the improved topology optimization circuit is as follows: Figure 9 and Figure 10 As shown. Inductor current.i Lr Waveform distortion has been improved, and the auxiliary switch... S The switching environment of component 2 has been improved.

[0056] Obviously, the above embodiments of this utility model are merely examples for clearly illustrating this utility model, and are not intended to limit the implementation of this utility model. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the protection scope of the claims of this utility model.

Claims

1. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis, characterized by, The application relates to a power electronic conversion circuit based on potential circuit analysis and a topology optimization circuit thereof. The output end of the power supply circuit (1) is connected with the input end of the main switch parasitic parameter circuit (2), the first input end of the auxiliary switch parasitic parameter circuit (4) and the first input end of the buffer network circuit (5), the first output end of the main switch parasitic parameter circuit (2) is connected with the input end of the driving parasitic parameter circuit (3), the first output end of the driving parasitic parameter circuit (3) is connected with the second input end of the auxiliary switch parasitic parameter circuit (4), the first output end of the auxiliary switch parasitic parameter circuit (4) is connected with the second input end of the buffer network circuit (5), and the output end of the buffer network circuit (5), the second output end of the auxiliary switch parasitic parameter circuit (4), the second output end of the driving parasitic parameter circuit (3) and the second output end of the main switch parasitic parameter circuit (2) are jointly connected with the input end of the power supply circuit (1). The main switch parasitic parameter circuit (2) comprises a main switch first parasitic inductance circuit (21), a main switch S1 and a main switch second parasitic inductance circuit (22), the output end of the power supply circuit (1) is connected with the input end of the main switch first parasitic inductance circuit (21), the output end of the main switch first parasitic inductance circuit (21) is connected with the drain electrode of the main switch S1, the gate electrode of the main switch S1 is connected with the input end of the driving parasitic parameter circuit (3), the source electrode of the main switch S1 is connected with the input end of the main switch second parasitic inductance circuit (22), and the output end of the main switch second parasitic inductance circuit (22) is connected with the input end of the power supply circuit (1).

2. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis according to claim 1, characterized in that, The auxiliary switch parasitic parameter circuit (4) comprises an auxiliary switch first parasitic inductance circuit (41), an auxiliary switch S2 and an auxiliary switch second parasitic inductance circuit (42), the output end of the driving parasitic parameter circuit (3) is connected with the gate electrode of the auxiliary switch S2, the drain electrode of the auxiliary switch S2 is connected with the first input end of the auxiliary switch first parasitic inductance circuit (41), the second input end of the auxiliary switch first parasitic inductance circuit (41) is connected with the output end of the power supply circuit (1), the output end of the first parasitic inductance circuit (41) is connected with the input end of the buffer network circuit (5), and the output end of the buffer network circuit (5) is connected with the input end of the power supply circuit (1).

3. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis according to claim 2, characterized in that, The first parasitic inductance circuit (21) of the main switch comprises first parasitic inductance L d_ex1 and second parasitic inductance L d_in1 The second parasitic inductance circuit (22) of the main switch comprises third parasitic inductance L s_in1 and fourth parasitic inductance L d_ex1 One end of the first parasitic inductance L d_ex1 of the power supply circuit (1) is connected to the output end, the other end of the first parasitic inductance L d_ex1 is connected to one end of the second parasitic inductance L d_in1 , the other end of the second parasitic inductance L d_in1 is connected to the drain of the main switch S1, the gate of the main switch S1 is connected to the input end of the driving parasitic parameter circuit (3), one end of the third parasitic inductance L s_in1 is connected to the source of the main switch S1, the other end of the third parasitic inductance L s_in1 is connected to one end of the fourth parasitic inductance L d_ex1 , the other end of the fourth parasitic inductance L d_ex1 is connected to the input end of the power supply circuit (1).

4. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis according to claim 3, characterized in that, The driving parasitic parameter circuit (3) comprises a first parasitic resistance R g1 , a driving circuit and a second parasitic resistance R g2 , one end of the first parasitic resistance R g1 is connected to the gate of the main switch S1, the other end of the first parasitic resistance R g1 is connected to the input end of the driving circuit, the first output end of the driving circuit is connected to one end of the second parasitic resistance R g2 , the other end of the second parasitic resistance R g2 is connected to the second input end of the auxiliary switch parasitic parameter circuit (4), and the second output end of the driving circuit is connected to the input end of the power supply circuit (1).

5. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis according to claim 4, characterized in that, The application chip is provided with the topology optimization circuit of the power electronic conversion circuit based on potential circuit analysis.

6. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis according to claim 5, characterized in that, The auxiliary switch first parasitic inductor circuit (41) comprises a fifth parasitic inductor L r , a sixth parasitic inductor L d_ex2 and a seventh parasitic inductor L d_in2 in series, the auxiliary switch second parasitic inductor circuit (42) comprises a ninth parasitic inductor L s_in2 and a tenth parasitic inductor L s_ex2 in series, the output terminal of the driving parasitic parameter circuit (3) is connected to the gate of the auxiliary switch S2, one end of the seventh parasitic inductor L d_in2 is connected to the drain of the auxiliary switch S2, the other end of the seventh parasitic inductor L d_in2 is connected to one end of the sixth parasitic inductor L d_ex2 , the other end of the sixth parasitic inductor L d_ex2 is connected to the input terminal of the buffer network circuit (5) and one end of the fifth parasitic inductor L r respectively, the other end of the fifth parasitic inductor L r is connected to the output terminal of the power supply circuit (1), one end of the ninth parasitic inductor L s_in2 is connected to the source of the auxiliary switch S2, the other end of the ninth parasitic inductor L s_in2 is connected to one end of the tenth parasitic inductor L s_ex2 , the other end of the tenth parasitic inductor L s_ex2 is connected to the input terminal of the power supply circuit (1).

7. A topology optimization circuit for power electronic conversion circuits based on latent circuit analysis according to claim 6, characterized in that, The buffer network circuit (5) includes a first buffer parameter circuit (51), a second buffer parameter circuit (52), and a feedback capacitor. C o and buffer resistor R o The first buffer parameter circuit (51) includes a first buffer capacitor connected in parallel. C D1 and the first diode D 1. The second buffer parameter circuit (52) includes a second buffer capacitor connected in parallel. C D2 Second diode D 2. First buffer capacitor C D1 one end and the first diode D The positive terminals of 1 are connected together to the output terminal of the power supply circuit (1), and the first buffer capacitor C D1 The other end is connected to the first diode. D The negative terminal of 1, the second buffer capacitor C D2 One end and the second diode D The positive terminals of 2 are connected together to the fifth parasitic inductor. L r and the sixth parasitic inductor L d_ex2 One end, the second buffer capacitor C D2 The other end is connected to the second diode. D The negative terminal of 2, the first diode D The negative terminal of 1 and the second diode D The negative terminals of 2 are connected together to the feedback capacitor. C o and buffer resistor R o One end, feedback capacitor C o and buffer resistor R o The other end is connected to the input terminal of the power supply circuit (1).

8. The topology optimization circuit for power electronic conversion circuits based on latent circuit analysis as claimed in claim 6, wherein, The buffer network circuit (5) comprises a first buffer parameter circuit (51), a second buffer parameter circuit (52), a third diode D 3, a third buffer capacitor C 3, a feedback capacitor C o and a buffer resistor R o The first buffer parameter circuit (51) comprises a first buffer capacitor C D1 and a first diode D 1 connected in parallel C D2 The second buffer parameter circuit (52) comprises a second buffer capacitor D 2 and a second diode C 2 connected in parallel D 1, a third buffer capacitor C 3, a fifth parasitic inductor C D1 and a sixth parasitic inductor D D2 The one end of the first buffer capacitor C r , the positive pole of the first diode D 2 and the other end of the third buffer capacitor C 3 are jointly connected to the negative pole of the third diode D 3, and the positive pole of the third diode D 3 is respectively connected to the one end of the fifth parasitic inductor L d_ex2 and the one end of the sixth parasitic inductor L D2 The other end of the second buffer capacitor C o is connected to the negative pole of the second diode D 2, and the negative pole of the first diode D 1 and the negative pole of the second diode D 2 are jointly connected to the feedback capacitor C o and the buffer resistor R o The one end of the feedback capacitor C I and the buffer resistor R L is jointly connected to the input end of the power supply circuit (1).

9. The topology optimization circuit for power electronic conversion circuits based on latent circuit analysis as claimed in claim 1, wherein, The power supply circuit (1) includes a power supply U I , a resistance element R L and an inductance element L , which are connected in series. U I , a resistance element R L and an inductance element L in this order.

10. An application chip for topology optimization of power electronic conversion circuits based on latent circuit analysis, characterized in that ​

Images