Scan chain circuit and control circuit for loading repetitive sequence to flip-flop

Abstract

The embodiment of the utility model relates to a scan chain circuit and a control circuit for loading a repetitive sequence to a trigger. The scan chain circuit is used for inputting a repetitive bit sequence to a trigger sequence comprising a multi-bit trigger and a unit trigger. One example includes a control circuit including a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits.

Description

Technical Field

[0001] This utility model relates to a scanning chain circuit and a control circuit for loading a repeating sequence into a flip-flop. Background Technology

[0002] Integrated circuits typically comprise thousands of components with complex interrelationships. These circuits are usually designed using a highly automated process known as electronic design automation (EDA). EDA begins with functional specifications provided in a hardware description language (HDL) and continues to the specifications of the circuit design, including the specifications of the basic circuit elements called cells, the physical arrangement of the cells, and the wiring of the interconnecting cells. Cells implement logic or other electronic functions using specific integrated circuit technologies.

[0003] Electronic design automation (EDA) allows for the implementation of many different circuit designs using various combinations of units. Commonly used units include flip-flops. A flip-flop is a circuit with two stable states that can be used to store state information. A flip-flop has one or more outputs and its state can be changed by signals applied to one or more control inputs. The stored state information can then be used to store data in a memory cell.

[0004] Flip-flops in a circuit can be connected in a chain-like structure to form a scan chain. Scan chains allow for easier testing of sequences of flip-flops and are an example of design fortestability (DFT) techniques used to improve the testability of designed circuits. Furthermore, scan chains can include multi-bit flip-flops and unit flip-flops. External automated test equipment can pass test pattern data to the sequence, and the observed outputs indicate the correct performance of the flip-flops. For example, some outputs of a scan chain may indicate a stuck bit fault or a hold-time violation. Utility Model Content

[0005] This invention discloses a control circuit for loading a repeating sequence onto multiple flip-flops. The control circuit includes a bit counter, a multiplexer, a first set of control circuits, and a second set of control circuits. The bit counter is configured to receive a first control signal, a second control signal, and a scan clock signal as inputs, and is further configured to output the first and second bits according to the first control signal, the second control signal, and the scan clock signal. The multiplexer is configured to receive the first and second bits as inputs and output the bit sequence. The first set of control circuits is configured to receive the bit sequence as input and output a first set of control signals. The second set of control circuits is configured to receive the bit sequence as input and output a second set of control signals.

[0006] This utility model discloses a scan chain circuit comprising multiple flip-flops, a first control signal, a second control signal, a scan clock signal, and a control circuit. The multiple flip-flops include unit flip-flops and multi-bit flip-flops, arranged in a predetermined output-to-input order. The control circuit includes a bit counter, one or more multiplexers, one or more first-group control circuits, and one or more second-group control circuits. The bit counter is configured to receive the first control signal, the second control signal, and the scan clock signal as inputs, and is further configured to output the first and second bits. The one or more multiplexers are configured to receive the first and second bits as inputs and output a bit sequence. The one or more first-group control circuits are configured to receive the bit sequence as input and output a first-group control signal to one or more corresponding multi-bit flip-flops. The one or more second-group control circuits are configured to receive the bit sequence as input and output a second-group control signal to one or more corresponding multi-bit flip-flops.

[0007] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a block diagram of an example circuit with a scan chain for testing a sequence of triggers, as shown in some embodiments.

[0009] Figure 2 As shown in some embodiments Figure 1 The block diagram of the example control circuit is shown.

[0010] Figure 3A As shown in some embodiments Figure 2 The example logic diagram for the counter is shown.

[0011] Figure 3B This is an example logic diagram of an input multiplexer for each offset of the desired input sequence, as shown in some embodiments.

[0012] Figure 4 According to some embodiments Figure 2 Example logic diagram of a medium-mode control circuit.

[0013] Figure 5 According to some embodiments, such as Figure 1 The example logic diagram of the input circuit of the flip-flop is shown.

[0014] Figure 6 This is an example table for classifying multiple trigger sequences according to some embodiments.

[0015] Figure 7This is an example table shown in some embodiments for selecting normal or inverted inputs for a trigger sequence.

[0016] Figure 8 As shown in some embodiments Figure 1 Alternative embodiments of the control circuit used in the example.

[0017] Figure 9 This is an example process for classifying a sequence of multiple triggers according to some embodiments.

[0018] Figure 10 It is a combination of some embodiments Figure 1 Example method flowchart of the control circuit.

[0019] Figure 11 Based on the use of some embodiments Figure 1 A flowchart illustrating an example method for diagnosing scan chain diagnostics using a control circuit to determine the trigger sequence.

[0020] Figure 12 This is an example method flowchart for providing a scan chain according to some embodiments.

[0021] Explanation of reference numerals in the attached figures

[0022] 100: Circuit

[0023] 110, 110A, MB2, MB4, MB6, MB12, SDF: Triggers

[0024] 112: Combinational Logic

[0025] 114, 114A: Input circuit

[0026] 116: Control Circuit

[0027] 118: Scan Clock

[0028] 120: Control signal

[0029] 122: Unit trigger

[0030] 210: 2-bit counter

[0031] 212, 212A, 212B, 212C, 212D: Group input circuits

[0032] 214, 214A, 820: Group control circuit

[0033] 216, 216A, 820: Normal and inverted signals

[0034] 218: Group

[0035] 310, 312: Output signals

[0036] 318, 410, 414, 416, 422, 428, 430: XOR gates

[0037] 320: OR Gate

[0038] 322: Latch

[0039] 326: Inverse XOR gate

[0040] 328, 334: D-type triggers

[0041] 330, 336, Q0, Q1: Counter bits

[0042] 332, 424: NOT gates

[0043] 340A, 340B, 340C, 340D, 412, 426: Multitasking Units

[0044] 342A, 342B, 342C, 342D, 514, 518: Input signals

[0045] 344A, 344B, 344C, 344D, 418, 432: Output signals

[0046] 346A, 346B, 346C, 346D: Select pins

[0047] 408A: First group of control circuits

[0048] 408B: Second group of control circuits

[0049] 420, 434: Inverting output signals

[0050] 510: OR Gate

[0051] 512: With the door

[0052] 516: Output of the previous trigger

[0053] 600: Sequence

[0054] 610: Rule Logic Table

[0055] 612: Classification Rules for Multi-bit Flip-Flops

[0056] 614: Classification Rules for Unit Triggers

[0057] 700: Connection Type Rule

[0058] 710: Sequence

[0059] 800: Control Circuit

[0060] 814: M-bit counter

[0061] 816: N sequential circuits

[0062] 822: Group N

[0063] 900: Process

[0064] 910: Netlist

[0065] 912: Control Kit

[0066] 914: Classification Rules

[0067] 916: Scan Chain Report

[0068] 918: Multiple groups

[0069] 1000, 1100, 1200: Method

[0070] 1010~1018, 1110~1120, 1210~1220: Operation

[0071] CD, D, SI: Input

[0072] CP, SE, Q: Output

[0073] mode0, mode1, mode1_A, mode1_B, mode1_C, mode1_D, mode1A_control, mode1B_control, mode1C_control, mode1D_control, mode0A_control, mode0B_control, mode0C_control, mode0D_control, mode1_x_ctrl, mode0_x_ctrl, mode1_x_ctrl_inverted, mode0_x_ctrl_inverted: signal

[0074] Q, QN: Unit

[0075] si: Input

[0076] so: Output Detailed Implementation

[0077] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the utility model description. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0078] Furthermore, for ease of description, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature and another element(s) as illustrated in the diagrams. In addition to the orientations depicted in the diagrams, spatially relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0079] As mentioned above, scan chains help detect certain errors in a sequence of flip-flops. For example, loading a repeating 011 / 1100 throughout the scan chain can be used to identify errors such as a fault stuck at a specific position or a hold-time violation. In many product designs that include scan chains, the flip-flop sequence consists of single and multi-bit flip-flops, with flip-flops of the same bit length not adjacent to each other. Because different multi-bit flip-flops require different numbers of clock cycles to correctly load the repeating bit sequence, the repeating bit sequence must therefore be loaded in segments.

[0080] This utility model relates to a scan chain system and method for efficiently loading repeating bit sequences into a sequence of flip-flops, including multi-bit flip-flops and unit flip-flops. The scan chain system includes control circuitry that connects and provides specific inputs to the flip-flop sequence based on the number of clock pulses, depending on the maximum scan length of all flip-flops in the scan chain, to address these issues. With the added control circuitry, users can efficiently diagnose the scan chain with repeating bit sequences, such as 1100 / 0011. Furthermore, each flip-flop is categorized into one of several groups. Each flip-flop group corresponds to an input to the control circuitry, which provides the desired sequence to each group based on the number of clock pulses. Moreover, the added control circuitry results in low area loss for circuit layout. By generating control input signals for each multi-bit flip-flop using the control circuitry, scan chain diagnostics can be determined, potentially indicating stuck bit faults or hold-time violations if errors are present in the flip-flop sequence. The information forming the control circuitry is obtained from netlists, control kits (ctl kits), and scan chain reports.

[0081] Figure 1 This is a block diagram of an example circuit with a scan chain for testing a sequence of flip-flops. In the illustrated embodiment, circuit 100 includes a sequence of flip-flops 110 connected to combinational logic 112 during normal operation. Furthermore, when the scan chain is used for testing purposes, input circuitry 114 is connected to the Q output and D input of each flip-flop 110. The flip-flops 110 also include unit flip-flops 122. Circuit 100 includes control circuitry 116 for providing a correct sequence based on the flip-flop group and the number of clock pulses. Control circuitry 116 receives inputs from a scan clock 118 and a control signal 120.

[0082] As shown in the figure, in this embodiment, the sequence of flip-flops 110 forms a scan chain, which includes D inputs for normal operation and Q outputs connected to combinational logic 112 and one of the input circuits 114 corresponding to the next flip-flop in the scan chain. In this embodiment, each flip-flop 110 is a D-type flip-flop; however, other types of flip-flops may also be used for scan chain testing, such as SR flip-flops, JK flip-flops, or T flip-flops. The sequence of flip-flops 110 includes flip-flops with different ratings regarding the number of bits. Multi-bit flip-flops may include, for example, 2-bit, 4-bit, or 12-bit. Although not shown, each multi-bit flip-flop may include additional D inputs and Q outputs. For scan chain purposes, in some embodiments not shown herein, multi-bit flip-flops may also include multiple si inputs. Furthermore, the sequence of flip-flops 110 includes unit flip-flops 122. Although only one unit flip-flop 122 is shown, more may be included. During normal operation, combinational logic 112 outputs from other connected portions of the circuit to the D inputs of each flip-flop and receives outputs from the Q outputs of each flip-flop 110. Input circuit 114, control circuit 116, scan clock 118, and control signal 120 are not used for normal operation. Combinational logic may include other elements to form memory cells or other registers to store data.

[0083] Circuit designers or other users may wish to use a scan chain to test components of the circuit. Input circuitry 114 is connected to a designated input si for each corresponding flip-flop 110. Multi-bit input circuitry of input circuitry 114 receives input from control circuitry 116, while the input circuitry of the unit flip-flop 122 receives control signal 120 directly, not from control circuitry 116. In this embodiment, control signal 120 includes mode0 and mode1 signals. Control circuitry 116 transmits a bit sequence to each input circuitry according to the classification group of the corresponding flip-flop. Furthermore, this bit sequence is the maximum length within the scan chain (the flip-flop with the highest rated number of bits) and requires the same number of clock pulses. For example, if the length of the maximum bit flip-flop is 6 bits, then the specified number of bits and the number of clock pulses in the sequence will also be 6. The control circuitry uses inputs from scan clock 118 and control signal 120 to generate these sequences. Although only five flip-flops are shown, the control circuitry can be connected to more flip-flops. Furthermore, each flip-flop may have more inputs and outputs, depending on its rated length. The increased control circuitry 116 and input circuitry 114 also result in lower area loss. For example, in some embodiments, adding input circuitry 114 and control circuitry 116 results in an increase of 2.2525% in the total area of ​​circuitry 100. Although a certain number and sequence of flip-flops are shown in circuitry 100, many different configurations of flip-flops and control circuitry can be used similarly to the described system and function.

[0084] Figure 2 yes Figure 1 The block diagram of the example control circuit is shown. In this embodiment, control circuit 116 is designed for the repeating sequence 1100 / 0011, but other bit sequences are also within the scope of this invention. As shown, control circuit 116 includes a counter circuit, which in the illustrated embodiment is a 2-bit counter 210 that receives inputs from scan clock 118 and control signal 120. The 2-bit counter 210 outputs a category signal to each group input circuit in group input circuit 212, including group input circuit 212A, group input circuit 212B, group input circuit 212C, and group input circuit 212D. Each input circuit of group input circuit 212 then outputs a corresponding signal to the corresponding group control circuit of group control circuit 214. Each control circuit then outputs a normal and an inverted output signal 216, mode1x_control, and mode0x_control to group 218, which includes the corresponding group of triggers.

[0085] Control circuit 116 receives inputs from scan clock 118 and control signal 120 to 2-bit counter 210. 2-bit counter 210 comprises 2 bits and can generate up to 4 sets of sufficient sequences. Although shown as a 2-bit counter, it can be an M-bit counter, capable of generating repeating bit sequences up to... Figure 8 The number of classification groups is N = 2M. The 2-bit output of the 2-bit counter 210 is connected to group input circuits 212, which include group input circuits 212A, 212B, 212C, and 212D. As indicated, each includes a bit of a repeating sequence, such as 1100. Furthermore, each repeating sequence is an offset from the other repeating sequences. For example, the repeating sequence 1100 of group input circuit 212A is shifted left by 1 bit to produce a repeating sequence 1001 for group input circuit 212B.

[0086] The repeating sequence shown is transmitted from group input circuit 212 to group control circuit 214. Similar to mode0 and mode1 serving as inputs to the scan chain without control circuitry, each group has a corresponding group control signal for mode0 and mode1, generated by its respective group control circuit in group control circuit 214. For example, the mode1A_control circuit generates the corresponding mode1A_ctrl signal. These respective group control signals for mode0 and mode1 are then connected to the normal connection type and the inverted connection type, and then to the corresponding group 218.

[0087] Figure 3A Show Figure 2The example logic diagram of the counter is shown. In the illustrated embodiment, mode0 310 and mode1 312 are output signals from control signal 120. Both mode0 310 and mode1 312 are connected to an XOR gate 318, which is then connected to an OR gate 320. The OR gate 320 also receives input from node signal 316. These signals are then fed to latch 322 along with an inverted scan clock 118. Latch 322 and scan clock 118 are received by an AND gate 324. These signals are then provided to D-type flip-flops 328 and 334, which provide counter bits Q1 330 and Q0 336, which are selection bits. Furthermore, mode0 310 and mode1 312 are also connected to an inverted XOR gate 326, which is connected to D-type flip-flops 328 and 334. D-type flip-flop 328 is connected to D-type flip-flop 334 via NOT gate 332.

[0088] In this embodiment, the 2-bit counter is a Gray code counter to avoid glitch during state transitions. For example, the counter transitions through states 0 (00), 1 (01), 3 (11), and 2 (10) before returning to state 0. However, in other embodiments, other types of counters, such as ring counters, decimal counters, modulo-N counters, ripple counters, or other binary code counters, may be used. Furthermore, the component may include additional logic elements not shown.

[0089] Figure 3B An example logic diagram of the input multiplexer for each offset of the required input sequence is shown. Here, counter bits Q0 and Q1 are used as inputs to all four group input circuits 212A-D. Each group input circuit includes a corresponding multiplexer 340A, 340B, 340C, or 340D, and selection signals 342A-D. Each selection signal 342 is connected to the selection pin 346 of the multiplexer 340. When each corresponding multiplexer receives the shown input signals 342A, 342B, 342C, and 342D, as well as counter bits Q0 and Q1, the multiplexers 340A-D output group output signals 344A, 344B, 344C, and 344D, which include the bit sequence and offset specified according to the group.

[0090] In the illustrated embodiment, each group input circuit in group input circuit 212 is controlled by the output of a 2-bit counter 210. Each multiplexer 340A-340D generates a corresponding repeating bit sequence as the counter enters different states or counts. A selection signal 342 indicates the input bit that causes the corresponding multiplexer to output the correct repeating bit sequence. For example, when a first clock pulse causes the 2-bit counter 210 to output Q1=0 and Q0=1 (state 1), and a second clock pulse causes the 2-bit counter 210 to output Q1=1 and Q0=1 (state 3), multiplexer 340A will first output the select pin (0) of select pin 346A, and then the select pin (3) of select pin 346A. This pattern continues for each multiplexer 340A-D to produce each corresponding repeating pattern: 1100 for group input circuit 212A, 1001 for group input circuit 212B, 0011 for group input circuit 212C, and 0110 for group input circuit 212D. Although shown with specific sequences and inputs, other embodiments may include different inputs and outputs for each group to achieve the same desired functionality.

[0091] Figure 4 yes Figure 2 An example logic diagram of the mode control circuit. In the illustrated embodiment, multiplexer 340A outputs group output signal 344A to group control circuit 214A, which includes a first group control circuit 408A and a second group control circuit 408B. Output signal mode1_A 344A is connected to XOR gates 410 and 422. The XOR gates also receive mode0 310. XOR gates 410 and 422 then output to multiplexers 412 and 426, respectively. Multiplexer 412 receives mode1 312 as input, while multiplexer 426 receives mode0, inverted by NOT gate 424 (i.e., inverter), as input. Both multiplexers receive activation signals from XOR gates 414 and 428, respectively. Mode0 310 and mode1 312 serve as inputs to XOR gates 414 and 428. The output of multiplexer 412 is mode1_A_ctrl 418, and the output signal is also inverted by XOR gate 416 to become mode1_A_ctrl_inverted 420. A similar process occurs to generate mode0_A_ctrl 432 and mode0_A_ctrl_inverted 434. XOR gate 430 receives input from XOR gate 428 and multiplexer 426, and then outputs mode0_A_ctrl_inverted 434.

[0092] Here, group control circuit 214A is shown, but the remaining group control circuits 214B-D include the same or similar components and output their respective mode0 and mode1 control signals. mode0_A_ctrl 432 and mode1_A_ctrl 418 are both generated by this circuit and are based on... Figure 6 One or more rules discussed in the relevant discussion include a repeating bit sequence. As previously mentioned, this repeating sequence will be the bit length of the largest rated flip-flop in the scan chain. Although group control circuits 214B-D include the same or similar components as group control circuit 214A, these circuits produce the corresponding repeating pattern. Furthermore, mode1_A_ctrl_inverted and mode0_A_ctrl_inverted are generated along with the normal version of the signal. Neither is connected to the unit flip-flop in the group, but rather based on... Figure 7 Choose one or more rules from the relevant discussion.

[0093] Figure 5 Is it like this? Figure 1 The example logic diagram of the input circuit of the flip-flop is shown. As shown, the input circuit 114A includes an OR gate 510 and an AND gate 512. The OR gate 510 receives input 514, which can be mode1_A_ctrl 418 or mode1_A_ctrl_inverted 420, and the output 516 of the previous flip-flop. The OR gate 510 then outputs a signal to the AND gate 512, which also receives input 518, which can be mode0_A_ctrl 432 or mode0_A_ctrl_inverted 434. The AND gate 512 then outputs to the si input of the D-type flip-flop 110A.

[0094] As shown in the figure, input circuit 114A receives three inputs: input 514, input 516, and input 518. Depending on the selected connection, input 514 will be either the mode1_A_ctrl or mode1_A_ctrl_inverted signal. If the connected flip-flop 110A is a unit flip-flop, then input 514 is mode1. Input 516 is... Figure 1 The connection shown is the Q output of the previous flip-flop. If flip-flop 110A is a unit flip-flop, mode0 is also directly connected to input 518.

[0095] Figure 6 An example table is shown for classifying multiple flip-flop sequences. In this embodiment, rule logic table 610 shows the steps for classifying the corresponding bits in the above sequence 600 using classification rule 612 for multi-bit flip-flops and classification rule 614 for single-bit flip-flops.

[0096] Sequence 600 comprises multiple multi-bit and unit flip-flops, forming a scan chain. As shown in the figure, 4N+X above each flip-flop represents the preceding sequence accumulated at output so, excluding the current unit. For example, no bits are accumulated at unit 1, therefore, the accumulated bits are 0, which is a multiple of 4N or 4*0, with no remainder. Based on this judgment, unit 1 is classified as 1A. Unit 1 has a length of 4 bits, therefore, the detected output is 0011 (the inverse of input 1100). The category of each flip-flop is classified by position in this way, as shown in rule logic table 610.

[0097] The maximum scan length is the largest multi-bit flip-flop in the sequence because the clock needs to pulse multiple times to load the pattern; in the illustrated embodiment, its length is 6. This maximum length is obtained from the control suite of the circuit. Therefore, smaller multi-bit flip-flops will receive additional pulses. Smaller multi-bit flip-flops use rollback counting to handle these additional pulses. The system then reclassifies the units based on the new accumulated bits of the additional clock pulses, as shown in rule logic table 610. For example, unit 1 now accumulates two bits 00 to handle the additional clock pulses. According to the classification rule 612 for multi-bit flip-flops, these additional accumulated bits result in a 4N+2 classification, thus resulting in a final 1C classification. Therefore, when performing scan chain diagnostics, unit 1 will receive mode0_C_ctrl and mode1_C_ctrl from the control circuit at its input circuit.

[0098] For unit flip-flops, additional pulses are not applicable because they are directly connected to control signals 120, mode0, and mode1, and are fixed. Therefore, their classification does not change from their original position. According to these rules, flip-flops in each final category share the same type of control sequence and category, and share the same clock. According to rule logic table 610, classification rule 612 for multi-bit flip-flops, and classification rule 614 for unit flip-flops, the result of connecting the previously described circuit is a repeating sequence of 1100 / 0011.

[0099] Figure 7 An example table is shown for selecting normal or inverted inputs for a sequence of flip-flops. In the illustrated embodiment, connection type rule 700 is used to determine the connection type, i.e., normal or inverted, for each cell / flip-flop in sequence 710.

[0100] Connection type rule 700 provides rules for classifying flip-flops in sequence 710 as either normally connected or inverted connected. In this embodiment, QN cells are cells that only have inverted outputs associated with the D / si pin. These QN flip-flops in the scan chain act as inverters during the shift phase. The applied rules include determining the number of QN cells from the current cell to the scan chain output (so), including the current cell. If the number of QN flip-flops is odd, the input circuitry of that flip-flop receives the mode1_x_ctrl_inverted and mode0_x_ctrl_inverted signals instead of the normal versions of mode1_x_ctrl and mode0_x_ctrl. For example, the number of QN cells starting from cell 2 (including the current cell) is even, so its input circuitry receives a normal connection. Furthermore, in this embodiment, a single bit is directly connected to the mode0 and mode1 control signals 120 and is not inverted.

[0101] Figure 8 It shows Figure 1 An alternative embodiment of the control circuitry used is described. Instead of a 2-bit counter that generates 4 bits and 4 groups of sequences, the control circuitry 800 can also be used to classify up to N groups. An M-bit counter 814 receives input signals from a scan clock 118 and a control signal 120. The M-bit counter 814 then outputs N output signals to N sequence circuits 816. The group control circuit 818 then receives the corresponding sequence and outputs the corresponding signal 820 to the flip-flops of the N groups 822.

[0102] In this embodiment, the bit counter is not limited to 2, but is designated to generate N groups of 822. As mentioned earlier, the number of N groups that an M-bit counter can support can be obtained by the formula N=2M.

[0103] Figure 9 An example step for classifying trigger sequences is shown. Here, step 900 includes classification rules 914 for receiving control suite 912, netlist 910, and scan chain report 916 to classify the trigger sequences into multiple groups 918.

[0104] Classification rule 914 is one or more rules previously described for classifying multi-bit flip-flops. Control kit 912 provides scan length information for the multi-bit cells, scan chain information from the scan chain report, and the number of flip-flops from the netlist. Using this information, the previously described circuitry can be generated. For example, a sequence of flip-flops can be synthesized. A netlist is formed from this sequence. Then, design-for-test (DFT) insertion of other components (such as input circuitry) produces a testable scan chain. The scan chain report, control kit, and netlist become known. Control circuitry is added and appropriately grouped with the corresponding flip-flops. For example, once all specified flip-flops in netlist 910 have been classified using the rules for classifying flip-flop cells, each flip-flop is classified into multiple groups 918. As previously mentioned, these one or more rules may be the rules previously described.

[0105] Figure 10 It is a combination Figure 1 An example method for controlling the circuit. In the illustrated embodiment, method 1000 includes operations 1010 to 1018, the result of which is to connect the control circuit to facilitate a scan chain with a repeating sequence.

[0106] Operation 1010 includes providing control circuitry and control signal input ports to the circuitry. This control circuitry may be control circuitry 116, and the mode0 and mode1 input ports may be control signals 120.

[0107] In operation 1012, one or more triggers are classified into multiple groups. These one or more triggers may include multi-bit triggers and unit triggers, arranged in a sequence to form a scan chain. Furthermore, triggers may be classified using one or more rules previously discussed.

[0108] In operation 1014, for each category of flip-flops, select either a normal connection type or an inverted connection type with the control circuit. The choice between normal and inverted connection may depend on the number of inverted output flip-flops between the current cell and the SO output.

[0109] In operation 1016, the output of the control circuit is connected to the corresponding input unit of each class of multi-bit flip-flops. The control circuit includes inverting and normal connection types, which are connected according to the previous selection. The input unit can also be one of the input circuits 114.

[0110] In operation 1018, the input unit of each unit flip-flop is directly connected to the mode0 and mode1 ports, regardless of its group. This unit flip-flop can be unit flip-flop 122. The method shown may also include using the provided control circuitry and flip-flops to determine scan chain diagnostics.

[0111] Figure 11 Is using Figure 1 An example method for determining scan chain diagnostics of a trigger sequence using control circuitry. In the illustrated embodiment, operations 1110-1120 of method 1100 use the control circuitry described above to determine scan chain diagnostics, including possible hold-time violations or stuck-in-position faults.

[0112] Operation 1110 includes receiving one or more input signals and a scan clock signal by a control circuit. The one or more input signals may be a control signal 120, and the scan clock signal may be a scan clock 118. In some embodiments, the control circuit may be a control circuit 116.

[0113] In operation 1112, the control circuit generates multiple input bits, wherein the multiple input bits include a repeating bit sequence and an offset of the repeating bit sequence. The repeating sequence can be as follows: Figures 2 to 7 The repeating sequence is 1100 / 0011. Furthermore, the control circuit can use a 2-bit counter 210 to generate the selected sequence and its respective offset, and provide this to the group input circuits 212A-D to generate the plurality of input bits. The group control circuit 214 can then receive the repeating sequence to generate the classified mode0 and mode1 signals for each group, for example, generating a plurality of group control signals based on the plurality of input bits described in operation 1114.

[0114] Proceeding to operation 1116, the control circuit provides each set of control signals to a corresponding group among a plurality of groups, each group comprising one or more categorized flip-flops, wherein the one or more categorized flip-flops form a scan chain. The flip-flops can be categorized into four groups A, B, C, and D of group 918. Using the received inputs, the flip-flops may then have their respective outputs. In operation 1118, the outputs are detected from one or more categorized flip-flops. Then, in operation 1120, scan chain diagnostics are determined based on the detected outputs.

[0115] Figure 12 This is a flowchart illustrating an example method for providing a scan chain. In this embodiment, method 1200 provides a plurality of sequentially connected triggers. The triggers are then connected to the provided control circuitry according to a classification. Scan chain diagnostics can then be performed.

[0116] In operation 1210, multiple flip-flops are provided. These multiple flip-flops include unit flip-flops and multi-bit flip-flops. These multiple flip-flops form a scan chain. These multiple flip-flops can be flip-flop 110. In operation 1212, the cumulative number of bits from each flip-flop to the scan chain output is determined. As described in connection type rule 700, the cumulative bit includes the current unit / flip-flop.

[0117] Proceed to operation 1214, where each trigger is categorized into multiple groups based on one or more rules, the first of which is based on the accumulated bit count. These accumulated bits then determine the trigger's category. Additionally, this operation may include determining the maximum scan length for the multiple triggers. A rollback count is then added to each of the multiple multi-bit triggers based on the maximum scan length. Each trigger can then be reclassified into its final category.

[0118] In operation 1216, a control circuit is provided, comprising multiple outputs corresponding to multiple groups, wherein the control circuit includes a first input signal port and a second input signal port. This control circuit may be control circuit 116, as previously discussed, connected to control signal 120 and including mode0 and mode1. In operation 1218, a predetermined repeating bit sequence is input to multiple flip-flops. This step can use the control circuit to provide an appropriate repeating sequence according to the category of each flip-flop. Then, in operation 1220, scan chain diagnostics are determined based on the outputs from the multiple flip-flops.

[0119] This method may further include determining the number of flip-flops with inverted outputs between each flip-flop in the flip-flop sequence and the scan chain output, and selecting an inverted connection type if the determined number is odd. Then, a normal connection type is selected if the determined number is even. These connection types are selected using connection type rule 700. Additionally, scan chain diagnostics may include stuck bit faults or hold-time violations.

[0120] According to some embodiments, a control circuit for loading a repeating sequence into a trigger sequence includes: a bit counter configured to receive a first control signal, a second control signal, and a scan clock signal as inputs, the bit counter further configured to output a first bit and a second bit according to the first control signal, the second control signal, and the scan clock signal. The control circuit also includes a multiplexer configured to receive the first and second bits as inputs and output a bit sequence; a first set of control circuitry configured to receive the bit sequence as inputs and output a first set of control signals; and a second set of control circuitry configured to receive the bit sequence as inputs and output a second set of control signals.

[0121] According to other examples, the scan chain circuit includes multiple flip-flops, including unit flip-flops and multi-bit flip-flops, arranged in a predetermined output-to-input order. The scan chain circuit also includes a first control signal, a second control signal, and a scan clock signal; and control circuitry including: a bit counter configured to receive the first control signal, the second control signal, and the scan clock signal as inputs, the bit counter also configured to output the first and second bits; and one or more multiplexers configured to receive the first and second bits as inputs and output a bit sequence. The control circuitry also includes one or more first-group control circuitry configured to receive the bit sequence as input and output a first-group control signal to one or more corresponding multi-bit flip-flops; and one or more second-group control circuitry configured to receive the bit sequence as input and output a second-group control signal to one or more corresponding multi-bit flip-flops.

[0122] According to a further embodiment, a method for testing multiple flip-flops includes: providing a plurality of flip-flops, wherein the plurality of flip-flops includes one or more unit flip-flops and one or more multi-bit flip-flops, the one or more unit flip-flops and the one or more multi-bit flip-flops being arranged in a predetermined output-to-input order. The method further includes: determining the cumulative number of bits from each flip-flop to a scan chain output; classifying each of the plurality of flip-flops into multiple groups according to one or more rules, wherein a first rule of the one or more rules is based on the cumulative number of bits. The method further includes: providing control circuitry including a plurality of outputs corresponding to the plurality of groups, wherein the control circuitry includes a first input signal port and a second input signal port. The method further includes: outputting a predetermined repeating bit sequence from the control circuitry to the plurality of flip-flops; and determining scan chain diagnostics based on the outputs from the plurality of flip-flops.

[0123] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand various aspects of the present invention. Those skilled in the art will understand that the present invention can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or obtaining the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A control circuit for loading a repeating sequence to a plurality of flip-flops, characterized by, The control circuit includes: a bit counter configured to receive as inputs a first control signal, a second control signal, and a scan clock signal, the bit counter further configured to output a first bit and a second bit based on the first control signal, the second control signal, and the scan clock signal; a multiplexer configured to receive as inputs the first bit and the second bit and output a bit sequence; a first set of control circuits configured to receive as inputs the bit sequence and output a first set of control signals; and a second set of control circuits configured to receive as inputs the bit sequence and output a second set of control signals.

2. The control circuit of claim 1, wherein: the first set of control circuits is further configured to output an inverted first set of control signals; and the second set of control circuits is further configured to output an inverted second set of control signals.

3. The control circuit of claim 2, wherein: the first set of control circuits connects the first set of control signals to a test input of one or more corresponding flip-flops, the one or more corresponding flip-flops including an even number of invert output flip-flops between the test input and a scan chain output of the one or more corresponding flip-flops; the first set of control circuits connects the inverted first set of control signals to a test chain input of the one or more corresponding flip-flops, the one or more corresponding flip-flops including an odd number of invert output flip-flops between the test input and the scan chain output of the one or more corresponding flip-flops; the second set of control circuits connects the second set of control signals to the test input of the one or more corresponding flip-flops, the one or more corresponding flip-flops including the even number of invert output flip-flops between the test input and the scan chain output of the one or more corresponding flip-flops; and the second set of control circuits connects the inverted second set of control signals to the test input of the one or more corresponding flip-flops, the one or more corresponding flip-flops including the odd number of invert output flip-flops between the test input and the scan chain output of the one or more corresponding flip-flops.

4. The control circuit of claim 1, wherein the bit counter includes: a first flip-flop counter configured to output the first bit; an inverter configured to receive the first bit and output an inverted first bit; and a second flip-flop counter configured to receive the inverted first bit and output the second bit.

5. The control circuit of claim 1, wherein the first set of control circuits includes: a first control multiplexer receiving as inputs a mutually exclusive or output signal, the bit sequence, and a mutually exclusive or select signal, the first control multiplexer outputting a first set of input signals. The scan chain circuit includes:

6. A scan chain circuit, characterized by a plurality of flip-flops, the plurality of flip-flops including single-bit flip-flops and multi-bit flip-flops and arranged in a predetermined output-to-input sequence; a first control signal, a second control signal, and a scan clock signal; and a control circuit including: ​ a bit counter configured to receive the first control signal, the second control signal, and the scan clock signal as inputs, the bit counter further configured to output a first bit and a second bit; one or more multi-taskers configured to receive the first bit and the second bit as inputs and output a bit sequence; one or more first sets of control circuitry configured to receive the bit sequence as inputs and output a first set of control signals to one or more corresponding multi-bit flip-flops; and one or more second sets of control circuitry configured to receive the bit sequence as inputs and output a second set of control signals to the one or more corresponding multi-bit flip-flops.

7. The scan chain circuit of claim 6, wherein a unit flip-flop of the plurality of flip-flops is configured to directly receive the first control signal and the second control signal as inputs.

8. The scan chain circuit of claim 6, wherein each flip-flop of the plurality of flip-flops comprises: an OR gate configured to receive the first set of control signals and an output from a previous flip-flop; and an AND gate configured to receive an inverted signal of the second set of control signals and an output of the OR gate as inputs, the AND gate outputting a signal to the flip-flop.

9. The scan chain circuit of claim 6, wherein: the one or more first sets of control circuitry are further configured to output an inverted first set of control signals; and the one or more second sets of control circuitry are further configured to output an inverted second set of control signals.

10. The scan chain circuit of claim 6, wherein the bit counter comprises: a first flip-flop counter configured to output the second bit; an inverter configured to receive the first bit and output an inverted first bit; and a second flip-flop counter configured to receive the inverted first bit and output the second bit.

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