Dynamic comparator built-in circuit and multi-gear voltage comparison circuit
By incorporating a dynamic comparator circuit with a built-in reference voltage, and utilizing resistor ratio configuration and latching circuitry, the problem of poor reference voltage range flexibility is solved, multi-range comparison is simplified, and the complexity and area overhead of the preceding circuit are reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-05
- Publication Date
- 2026-04-14
AI Technical Summary
Existing dynamic comparators have poor flexibility in the range of reference voltage, and the implementation of multi-range comparison is highly complex, which increases the area overhead and layout requirements of the front-end circuit.
The dynamic comparator circuit with built-in reference voltage is used. The reference voltage offset is achieved by using the built-in resistor ratio configuration through the pre-amplifier circuit and latch circuit. The comparison result is output through the latch circuit, which simplifies the design requirements of the front-end circuit.
It improves the flexibility of the reference voltage range, reduces the dependence on the front-end circuit, reduces the chip area and layout complexity, and simplifies the implementation of multi-range comparison.
Smart Images
Figure CN224124117U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of integrated circuits, specifically to a dynamic comparator built-in circuit and a multi-level voltage comparison circuit. Background Technology
[0002] Dynamic comparators are commonly used circuit modules in on-chip integrated systems. Their main function is to compare a reference voltage and a voltage to be compared and then provide the result information for other modules to use. This requires the preceding circuitry to provide a reference voltage.
[0003] Current dynamic comparators mainly suffer from the following problems: Poor flexibility in reference voltage range. For example, in the technical solution disclosed in patent CN115395931A, the reference voltage value can only be determined by the preceding stage circuit, and the voltage range cannot be flexibly adjusted according to actual needs. High complexity in implementing multi-range comparison. For example, in the technical solution disclosed in patent CN115865081A, when n-range voltage comparison is required, n filtered reference voltages must be provided by the preceding stage circuit. This not only increases the area overhead of the preceding stage circuit but also places higher demands on the layout of voltage traces on the circuit board. Utility Model Content
[0004] The purpose of this invention is to solve the problem in the prior art that it completely relies on the front-end circuit to provide the reference voltage.
[0005] In a first aspect, this utility model provides a built-in circuit for a dynamic comparator with an internal reference, including a preamplifier circuit and a latch circuit, wherein the preamplifier circuit and the latch circuit are connected in sequence.
[0006] The preamplifier circuit uses a built-in resistor ratio configuration to offset the reference voltage and amplifies the difference between the input voltage and the offset reference voltage; the latch circuit latches the amplified difference and outputs the comparison result.
[0007] Furthermore, the preamplifier circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor;
[0008] The gate of the first NMOS transistor receives a reference voltage; the gate of the second NMOS transistor receives a voltage to be compared; the gate of the third NMOS transistor receives a bias voltage, its source is grounded, and its drain is connected to the source of the first NMOS transistor and the source of the second NMOS transistor.
[0009] Furthermore, the preamplifier circuit also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor;
[0010] The first resistor is connected between the source of the first NMOS transistor and the drain of the third NMOS transistor; the second resistor is connected between the source of the second NMOS transistor and the drain of the third NMOS transistor; one end of the third resistor is connected to the drain of the first NMOS transistor and the other end is connected to the power supply; one end of the fourth resistor is connected to the drain of the second NMOS transistor and the other end is connected to the power supply.
[0011] The first capacitor is connected in parallel across the third resistor, and the second capacitor is connected in parallel across the fourth resistor.
[0012] Furthermore, the latching circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
[0013] The drain of the fourth NMOS transistor is connected to the source of the fifth and sixth NMOS transistors, and its gate receives a clock signal; the gate of the fifth NMOS transistor is connected to the drain of the first NMOS transistor; and the gate of the sixth NMOS transistor is connected to the drain of the second NMOS transistor.
[0014] Furthermore, the latching circuit also includes a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
[0015] The sources of the seventh NMOS transistor and the eighth NMOS transistor are respectively connected to the drains of the fifth NMOS transistor and the sixth NMOS transistor, and the gates and drains of the seventh NMOS transistor and the eighth NMOS transistor are cross-connected to form a cross-coupling structure.
[0016] The gates and drains of the first PMOS transistor and the second PMOS transistor are cross-coupled, forming a cross-coupled structure. The drain of the first PMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the eighth NMOS transistor. The source is connected to the power supply.
[0017] Furthermore, the latching circuit also includes a third PMOS transistor, a fourth PMOS transistor, a first NOR gate, a second NOR gate, a third NOR gate, and an inverter;
[0018] The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the power supply, and their gates receive the clock signal; the drain of the third PMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the eighth NMOS transistor.
[0019] Furthermore, the latch circuit also includes a first NOR gate, a second NOR gate, a third NOR gate, a NAND gate, and an inverter;
[0020] The two inputs of the first NOR gate are connected to the reset signal and the drain of the eighth NMOS transistor, respectively; the two inputs of the second NOR gate are connected to the output of the first NOR gate and the output of the third NOR gate, respectively; the two inputs of the third NOR gate are connected to the output of the second NOR gate and the output of the NAND gate, respectively; the two inputs of the NAND gate are connected to the drain of the seventh NMOS transistor and the output of the inverter, respectively; and the input of the inverter is connected to the reset signal.
[0021] Furthermore, the NMOS transistor in the preamplifier circuit can be replaced with a PMOS transistor.
[0022] A second aspect of this utility model is to provide a multi-level voltage comparison circuit, including multiple built-in dynamic comparator circuits as described in any of the preceding claims.
[0023] Multiple dynamic comparator built-in circuits share the same input terminal and reference voltage, and the second resistor in each dynamic comparator built-in circuit has a different resistance value.
[0024] Compared with the prior art, this utility model has at least the following beneficial effects: by using a built-in resistor ratio configuration in the preamplifier circuit to achieve the reference voltage offset, the dependence on the preamplifier circuit is reduced, and the preamplifier circuit no longer needs to directly provide a specific reference voltage value, simplifying the design requirements of the preamplifier circuit; by changing the resistance ratio of the built-in resistors, the offset of the reference voltage can be flexibly adjusted, thereby improving the flexibility of voltage level setting; since the offset of the reference voltage is achieved inside the comparator, an additional reference voltage generation circuit is eliminated, effectively reducing the chip area. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0026] Figure 1 This is a circuit diagram of a dynamic comparator with a built-in reference voltage in one embodiment of the present invention;
[0027] Figure 2 This is a circuit diagram of a dynamic comparator with a built-in reference voltage used for multi-level quantization in one embodiment of the present invention. Detailed Implementation
[0028] The present invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the present invention. It should be understood that those skilled in the art can modify the present invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being broadly known to those skilled in the art and is not intended to limit the present invention.
[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0030] The present invention will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0031] Example 1
[0032] Please refer to Figure 1 This embodiment provides a built-in circuit for a dynamic comparator with an internal reference, including a preamplifier circuit and a latch circuit, wherein the preamplifier circuit and the latch circuit are connected in sequence.
[0033] The preamplifier circuit uses a built-in resistor ratio configuration to offset the reference voltage and amplifies the difference between the input voltage and the offset reference voltage; the latch circuit latches the amplified difference and outputs the comparison result.
[0034] Specifically, the preamplifier circuit uses a built-in resistor ratio configuration to offset the reference voltage and amplifies the difference between the input voltage and the offset reference voltage. The latch circuit latches the amplified difference and outputs the comparison result. The latch circuit can include multiple NMOS and PMOS transistors, forming a cross-coupled structure. The latch circuit can also include multiple NOR gates and inverters for logic operations and signal inversion. Through the combination of the preamplifier circuit and the latch circuit, the difference between the input voltage and the reference voltage is amplified and latched, and the comparison result is output.
[0035] The preamplifier circuit uses a built-in resistor ratio configuration to achieve reference voltage offset, allowing the reference voltage range to be flexibly adjusted according to actual needs, thus solving the problem of poor reference voltage range flexibility. At the same time, the latch circuit design simplifies the implementation of multi-range comparisons, reducing the area overhead and layout complexity of the preamplifier circuit.
[0036] Furthermore, the preamplifier circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor;
[0037] The gate of the first NMOS transistor receives a reference voltage; the gate of the second NMOS transistor receives a voltage to be compared; the gate of the third NMOS transistor receives a bias voltage, its source is grounded, and its drain is connected to the source of the first NMOS transistor and the source of the second NMOS transistor.
[0038] Specifically, the first and second NMOS transistors are used to receive the reference voltage and the voltage to be compared, respectively, while the third NMOS transistor provides the bias voltage. By connecting the first and second resistors, a voltage difference is created between the sources of the first and second NMOS transistors, thereby amplifying the difference between the input voltage and the reference voltage. The third and fourth resistors are connected to the power supply to provide a stable operating voltage. The first and second capacitors are used to filter out high-frequency noise, ensuring circuit stability.
[0039] By introducing multiple resistors and capacitors into the preamplifier circuit, the difference between the input voltage and the reference voltage can be effectively amplified. Furthermore, the filtering effect of the capacitors further improves the circuit's anti-interference capability and stability. This simplifies the circuit structure and also enhances its performance and reliability.
[0040] Furthermore, the preamplifier circuit also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor;
[0041] The first resistor is connected between the source of the first NMOS transistor and the drain of the third NMOS transistor; the second resistor is connected between the source of the second NMOS transistor and the drain of the third NMOS transistor; one end of the third resistor is connected to the drain of the first NMOS transistor and the other end is connected to the power supply; one end of the fourth resistor is connected to the drain of the second NMOS transistor and the other end is connected to the power supply.
[0042] The first capacitor is connected in parallel across the third resistor, and the second capacitor is connected in parallel across the fourth resistor.
[0043] Specifically, the first and second resistors are used to adjust the gain of the preamplifier circuit; changing the resistance values adjusts the circuit's amplification factor. The third and fourth resistors provide power supply voltage to the drains of the first and second NMOS transistors, ensuring normal circuit operation. The first and second capacitors filter out high-frequency noise, improving circuit stability and anti-interference capabilities.
[0044] In a preferred embodiment, the first and second resistors can be variable resistors to dynamically adjust the circuit gain according to actual needs. The third and fourth resistors are fixed resistors to ensure a stable power supply voltage.
[0045] By introducing resistors and capacitors into the preamplifier circuit, precise control of circuit gain and effective noise suppression are achieved. Adjusting the resistor value allows for flexible changes in the circuit's amplification factor to suit different application scenarios; introducing capacitors effectively filters out high-frequency noise, improving the circuit's anti-interference capability.
[0046] Furthermore, the latching circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
[0047] The drain of the fourth NMOS transistor is connected to the source of the fifth and sixth NMOS transistors, and its gate receives a clock signal; the gate of the fifth NMOS transistor is connected to the drain of the first NMOS transistor; and the gate of the sixth NMOS transistor is connected to the drain of the second NMOS transistor.
[0048] Specifically, the latch circuit, through its cross-coupling structure, effectively latches the amplified difference signal output from the preamplifier circuit and achieves a stable output of the comparison result through a combination of NOR and NAND gates. The cross-coupling structure gives the latch circuit high anti-interference capability, enabling it to maintain stable operation in complex circuit environments. Furthermore, by introducing clock and reset signals, the latch circuit can achieve synchronous operation and reset functions, further improving the circuit's reliability and flexibility.
[0049] Furthermore, the latching circuit also includes a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, and a second PMOS transistor;
[0050] The sources of the seventh NMOS transistor and the eighth NMOS transistor are respectively connected to the drains of the fifth NMOS transistor and the sixth NMOS transistor, and the gates and drains of the seventh NMOS transistor and the eighth NMOS transistor are cross-connected to form a cross-coupling structure.
[0051] The gates and drains of the first PMOS transistor and the second PMOS transistor are cross-coupled, forming a cross-coupled structure. The drain of the first PMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the eighth NMOS transistor. The source is connected to the power supply.
[0052] Specifically, the cross-coupling structure of the seventh and eighth NMOS transistors enhances the stability and response speed of the latch circuit. The cross-coupling structure of the first and second PMOS transistors further improves the circuit's anti-interference capability and signal transmission efficiency. For example, the cross-connection of the gates and drains of the seventh and eighth NMOS transistors effectively reduces signal delay and improves the circuit's response speed. The cross-connection of the gates and drains of the first and second PMOS transistors effectively suppresses noise interference and improves signal transmission quality.
[0053] In a preferred embodiment, the sources of the seventh and eighth NMOS transistors are connected to the drains of the fifth and sixth NMOS transistors, respectively, which can effectively reduce circuit power consumption and improve circuit efficiency. The sources of the first and second PMOS transistors are connected to the power supply, which can effectively improve the stability and reliability of the circuit.
[0054] By introducing the seventh NMOS transistor, the eighth NMOS transistor, the first PMOS transistor, and the second PMOS transistor, and adopting a cross-coupling structure, the stability, response speed, and anti-interference capability of the latch circuit are significantly improved.
[0055] Furthermore, the latching circuit also includes a third PMOS transistor, a fourth PMOS transistor, a first NOR gate, a second NOR gate, a third NOR gate, and an inverter;
[0056] The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the power supply, and their gates receive the clock signal; the drain of the third PMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the eighth NMOS transistor.
[0057] Specifically, the introduction of the third and fourth PMOS transistors enables the latch circuit to perform voltage comparison and result latching more effectively under the control of the clock signal. The combination of the first, second, and third NOR gates further enhances the circuit's logic processing capability, ensuring that the circuit can quickly return to its initial state under the action of a reset signal. The use of an inverter provides precise control over the reset signal, avoiding signal delay or distortion.
[0058] By introducing a third PMOS transistor, a fourth PMOS transistor, a first NOR gate, a second NOR gate, a third NOR gate, and an inverter, the performance and reliability of the latch circuit are significantly improved. This not only simplifies the circuit structure and reduces implementation complexity but also improves the accuracy and response speed of voltage comparison.
[0059] Furthermore, the latch circuit also includes a first NOR gate, a second NOR gate, a third NOR gate, a NAND gate, and an inverter;
[0060] The two inputs of the first NOR gate are connected to the reset signal and the drain of the eighth NMOS transistor, respectively; the two inputs of the second NOR gate are connected to the output of the first NOR gate and the output of the third NOR gate, respectively; the two inputs of the third NOR gate are connected to the output of the second NOR gate and the output of the NAND gate, respectively; the two inputs of the NAND gate are connected to the drain of the seventh NMOS transistor and the output of the inverter, respectively; and the input of the inverter is connected to the reset signal.
[0061] Specifically, the first NOR gate receives the reset signal and the drain signal of the eighth NMOS transistor, and generates an output signal based on these two signals. The second NOR gate receives the output signals of the first and third NOR gates, and further generates a new output signal. The third NOR gate receives the output signals of the second NOR gate and the NAND gate, and generates the final output signal. The NAND gate receives the drain signal of the seventh NMOS transistor and the output signal of the inverter, and generates an intermediate signal. The inverter is used to invert the reset signal before outputting it.
[0062] In a preferred embodiment, the first NOR gate, second NOR gate, third NOR gate, NAND gate, and inverter can be implemented using standard CMOS logic gate circuits. For example, the first NOR gate can be composed of two PMOS transistors and two NMOS transistors, wherein the sources of the two PMOS transistors are connected to the power supply, the sources of the two NMOS transistors are grounded, the drains of the two PMOS transistors and the drains of the two NMOS transistors are connected together as the output terminal, and the gates of the two PMOS transistors and the gates of the two NMOS transistors are respectively connected to the reset signal and the drain signal of the eighth NMOS transistor.
[0063] By introducing first NOR gates, second NOR gates, third NOR gates, NAND gates, and inverters, the latch circuit was further optimized. Specifically, the introduction of these logic gates enabled the latch circuit to process reset signals and comparison result signals more effectively, thereby improving the reliability and stability of the circuit.
[0064] Furthermore, the NMOS transistor in the preamplifier circuit can be replaced with a PMOS transistor.
[0065] Specifically, the NMOS transistor in the preamplifier circuit can achieve the same function by replacing it with a PMOS transistor. This replacement can be achieved by adjusting the bias voltage and connection method in the circuit. For example, when an NMOS transistor is replaced with a PMOS transistor, the polarity of the bias voltage needs to be adjusted accordingly to ensure that the PMOS transistor can function properly. In addition, the source and drain connections of the PMOS transistor also need to be reversed compared to the NMOS transistor to maintain the logic function of the circuit.
[0066] In another possible embodiment of this invention, all NMOS transistors in the preamplifier circuit can be replaced with PMOS transistors. The size and parameters of the replaced PMOS transistors can be adjusted according to specific application requirements to optimize circuit performance.
[0067] Replacing the NMOS transistors in the preamplifier circuit with PMOS transistors provides a flexible design option, allowing circuit designers to select the most suitable device type based on specific application scenarios and process conditions. This replacement not only maintains the original functionality of the circuit but can also improve circuit performance in certain situations, such as reducing power consumption or increasing speed.
[0068] The following describes the built-in circuitry in this embodiment, in conjunction with... Figure 1 For a detailed analysis, let the transconductance of MN0 in the preamplifier circuit be gm0, the transconductance of MN1 be gm1, the resistance of R0 be r0, the resistance of R1 be r1, the resistances of R2 and R3 be equal and r2, the current flowing through MN2 under the control of the bias voltage Vb be I, the gate voltage of MN0 be VREF, the gate voltage of MN1 be VI, and the drain voltage of MN2 be V0.
[0069] Ignoring channel modulation and volume effects, both MN0 and MN1 are in the saturation region. When in equilibrium, the current flowing through MN0 and MN1 is equal, both being I / 2.
[0070] Current flowing through MN0
[0071] Current flowing through MN1
[0072] In other words, when in equilibrium, In fact, the reference voltage of the new built-in comparator at this time is... set up r is the resistance value of the resistor unit, and k is a natural number greater than or equal to 1.
[0073] Therefore, the reference voltage of the built-in comparator can be expressed as: By adjusting the value of k, the built-in reference voltage of the comparator can be set.
[0074] Example 2
[0075] Please refer to Figure 2 This embodiment provides a multi-level voltage comparison circuit, including multiple built-in dynamic comparator circuits as described in Embodiment 1.
[0076] Multiple dynamic comparator built-in circuits share the same input terminal and reference voltage, and the second resistor in each dynamic comparator built-in circuit has a different resistance value.
[0077] The multi-level voltage comparator circuit achieves flexible adjustment of the reference voltage level through the combination of multiple dynamic comparator built-in circuits. Each dynamic comparator's built-in circuit has a different second resistor value, allowing the reference voltage offset to be adjusted according to actual needs, thus solving the problem of poor reference voltage level flexibility in existing technologies. Furthermore, by sharing the same input terminal and reference voltage, the complexity and area overhead of the preceding circuitry are reduced, simplifying the layout requirements for voltage traces on the circuit board.
[0078] In this embodiment, please refer to Figure 2 The comparator COM instance in Example 1 is used as COM1, COM2, COM3, ..., COMn in Example 2.
[0079] Let the resistance of R0 be r, and the resistance of R1 be respectively... r, r, r, ... r. Therefore, the built-in reference voltages VREF1, VREF2, VREF3, ..., VREFn are respectively: ...
[0080] These built-in reference voltages can quantize the input voltage VIN in n levels, with the step between each two adjacent levels being... Where m = 2, 3, 4, ..., n. The error of the built-in reference voltage range design is mainly determined by the comparator itself and is independent of the preceding reference voltage VREF, and can be simulated and optimized.
[0081] The above-described specific examples are for illustrative purposes only and are not intended to limit the scope of this invention. Those skilled in the art to which this invention pertains can make various simple deductions, modifications, or substitutions based on the concept of this invention.
Claims
1. A dynamic comparator built-in circuit, characterized in that, It includes a preamplifier circuit and a latch circuit, wherein the preamplifier circuit and the latch circuit are connected in sequence; The preamplifier circuit uses a built-in resistor ratio configuration to offset the reference voltage and amplifies the difference between the input voltage and the offset reference voltage; the latch circuit latches the amplified difference and outputs the comparison result.
2. The dynamic comparator built-in circuit as described in claim 1, characterized in that, The preamplifier circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; The gate of the first NMOS transistor receives a reference voltage; the gate of the second NMOS transistor receives a voltage to be compared; the gate of the third NMOS transistor receives a bias voltage, its source is grounded, and its drain is connected to the source of the first NMOS transistor and the source of the second NMOS transistor.
3. The dynamic comparator built-in circuit as described in claim 2, characterized in that, The preamplifier circuit also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, and a second capacitor. The first resistor is connected between the source of the first NMOS transistor and the drain of the third NMOS transistor; the second resistor is connected between the source of the second NMOS transistor and the drain of the third NMOS transistor; one end of the third resistor is connected to the drain of the first NMOS transistor and the other end is connected to the power supply; one end of the fourth resistor is connected to the drain of the second NMOS transistor and the other end is connected to the power supply. The first capacitor is connected in parallel across the third resistor, and the second capacitor is connected in parallel across the fourth resistor.
4. The built-in dynamic comparator circuit as described in claim 3, characterized in that, The latching circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The drain of the fourth NMOS transistor is connected to the source of the fifth and sixth NMOS transistors, and its gate receives a clock signal; the gate of the fifth NMOS transistor is connected to the drain of the first NMOS transistor; and the gate of the sixth NMOS transistor is connected to the drain of the second NMOS transistor.
5. The dynamic comparator built-in circuit as described in claim 4, characterized in that, The latching circuit also includes a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor, and a second PMOS transistor; The sources of the seventh NMOS transistor and the eighth NMOS transistor are respectively connected to the drains of the fifth NMOS transistor and the sixth NMOS transistor, and the gates and drains of the seventh NMOS transistor and the eighth NMOS transistor are cross-connected to form a cross-coupling structure. The gates and drains of the first PMOS transistor and the second PMOS transistor are cross-coupled, forming a cross-coupled structure. The drain of the first PMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the eighth NMOS transistor. The source is connected to the power supply.
6. The dynamic comparator built-in circuit as described in claim 5, characterized in that, The latching circuit also includes a third PMOS transistor, a fourth PMOS transistor, a first NOR gate, a second NOR gate, a third NOR gate, and an inverter; The sources of the third PMOS transistor and the fourth PMOS transistor are connected to the power supply, and their gates receive the clock signal; the drain of the third PMOS transistor is connected to the drain of the seventh NMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the eighth NMOS transistor.
7. The dynamic comparator built-in circuit as described in claim 6, characterized in that, The latching circuit further includes a first NOR gate, a second NOR gate, a third NOR gate, a NAND gate, and an inverter; The two inputs of the first NOR gate are connected to the reset signal and the drain of the eighth NMOS transistor, respectively; the two inputs of the second NOR gate are connected to the output of the first NOR gate and the output of the third NOR gate, respectively; the two inputs of the third NOR gate are connected to the output of the second NOR gate and the output of the NAND gate, respectively; the two inputs of the NAND gate are connected to the drain of the seventh NMOS transistor and the output of the inverter, respectively; and the input of the inverter is connected to the reset signal.
8. The built-in dynamic comparator circuit as described in claim 3, characterized in that, The NMOS transistor in the preamplifier circuit can be replaced with a PMOS transistor.
9. A multi-level voltage comparator circuit, characterized in that, Includes multiple built-in dynamic comparator circuits as described in any one of claims 3-8; Multiple dynamic comparator built-in circuits share the same input terminal and reference voltage, and the second resistor in each dynamic comparator built-in circuit has a different resistance value.