RTP annealing furnace wafer transfer dynamic simulation optimization system

Abstract

The utility model provides an RTP annealing furnace wafer transfer dynamic simulation optimization system, which relates to the technical field of annealing furnace wafer transfer dynamic simulation, selects a wafer transfer path in a high level signal mode through a path selection module, adjusts the wafer transfer speed through a speed adjustment module, and improves the wafer transfer efficiency. The communication interface module is used for sending a chip transmission path and a chip transmission speed to the chip transmission module, and the chip transmission module is used for carrying out chip transmission simulation according to the chip transmission path sent by the path selection module and the chip transmission speed sent by the speed regulation module; the precision detection module is installed around the wafer carrier and used for detecting whether the accuracy of the wafer placement position accuracy meets the simulation requirement when the wafer conveying module conveys wafers, the precision selection module is used for adjusting the accuracy of the wafer placement position accuracy and sending the accuracy to the precision detection module, and the speed detection module is used for detecting the time of the wafer conveying process of the wafer conveying module. And the simulation display module is used for displaying the accuracy of the wafer placement position and the wafer transfer time.

Description

Technical Field

[0001] This utility model relates to the field of dynamic simulation technology for wafer transfer in annealing furnaces, specifically to an RTP annealing furnace wafer transfer dynamic simulation optimization system. Background Technology

[0002] In the semiconductor manufacturing industry, the wafer transfer process in RTP annealing furnaces has stringent requirements for process precision and efficiency. Traditional wafer transfer systems often rely on software algorithms for control logic, resulting in poor real-time performance and weak resistance to electromagnetic interference. This is particularly problematic in high-temperature, high-dust industrial environments, where it can easily lead to signal delays or misjudgments. Existing hardware control systems often employ fixed paths and single-speed modes, lacking dynamic parameter adjustment capabilities, making it difficult to coordinate and optimize wafer transfer efficiency and wafer positioning accuracy. Furthermore, in the simulation and debugging phase, the separate design of precision detection and speed monitoring modules, lacking an integrated feedback mechanism, leads to long process parameter optimization cycles and high costs, making it difficult to meet the stringent requirements of advanced processes for wafer transfer consistency. Utility Model Content

[0003] The purpose of this invention is to provide a dynamic simulation optimization system for wafer transfer in an RTP annealing furnace, in order to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, this utility model provides the following technical solution:

[0005] A dynamic simulation and optimization system for wafer transfer in an RTP annealing furnace includes:

[0006] The path selection module operational amplifier is electrically connected to the communication interface module operational amplifier. It is used to generate a high-level signal to control the wafer transfer path during wafer transfer and to send the wafer transfer path to the wafer transfer module operational amplifier through the communication interface module operational amplifier.

[0007] The speed adjustment module operational amplifier is electrically connected to the communication interface module operational amplifier and is used to generate an analog voltage signal to control the chip transfer speed, which is then sent to the chip transfer module operational amplifier through the communication interface module operational amplifier.

[0008] The communication interface module operational amplifier is electrically connected to the chip transfer module operational amplifier and is used to transmit analog voltage signals and high-level signals between the path selection module operational amplifier, the speed adjustment module operational amplifier and the chip transfer module operational amplifier.

[0009] The operational amplifier of the transfer module is used to set the transfer parameters according to the high-level signal sent by the operational amplifier of the path selection module to select the transfer path and the analog voltage signal sent by the operational amplifier of the speed adjustment module to control the transfer speed.

[0010] The precision detection module operational amplifier is installed around the wafer carrier and electrically connected to the simulation display module operational amplifier. It is used to detect the precision of the wafer placement position when the wafer transfer module operational amplifier transfers the wafer, and generate precision data. After comparing the precision data with the precision threshold, the data exceeding the precision threshold is sent to the simulation display module operational amplifier.

[0011] An operational amplifier for precision selection module, which is electrically connected to an operational amplifier for precision detection module, is used to adjust the precision threshold for accurate wafer placement and send the precision threshold to the operational amplifier for precision detection module.

[0012] A speed detection module operational amplifier, which is electrically connected to the simulation display module operational amplifier, is used to detect the time of the chip transfer process of the chip transfer module operational amplifier and send it to the simulation display module operational amplifier.

[0013] The simulation display module operational amplifier is used to display the accuracy of wafer placement and wafer transfer time.

[0014] Furthermore, the path selection module includes a DIP switch group SW1-SW8, a 74H148 priority encoder, and a 74HC595 first register. One end of the DIP switch group SW1-SW8 is connected in parallel and electrically connected to the power supply terminal VCC. The other end is connected to the IN0-IN7 terminals of the priority encoder. The priority encoder includes the IN0-IN7 terminals and the A0 terminal. The first register includes the SER terminal and the Q7S terminal. The A0 terminal of the priority encoder is electrically connected to the SER terminal of the first register.

[0015] Furthermore, the speed adjustment module includes an adjustment resistor R1, an LM358 operational amplifier, an ADC0804 digital-to-analog converter module, and a 74HC595 second register. One end of the adjustment resistor R1 is electrically connected to the power supply terminal VCC, the other end is electrically connected to the ground terminal GND, and the middle end is electrically connected to the IN+ terminal of the operational amplifier. The operational amplifier includes an IN+ terminal, an IN- terminal, and an OUT terminal. The IN- terminal and the OUT terminal are electrically connected. The OUT terminal is electrically connected to the IN terminal of the digital-to-analog converter module. The digital-to-analog converter module includes an IN terminal and an OUT terminal. The second register includes a SER terminal and a Q7S terminal. The OUT terminal of the digital-to-analog converter module and the SER terminal of the second register are electrically connected. The communication interface module is a MAX485 communication interface. The OUT terminals of the first register and the second register are connected in parallel and then electrically connected to the DI terminal of the communication interface.

[0016] Furthermore, the accuracy detection module includes detectors 1-5, the accuracy selection module includes a CD4520 counter, a 74HC85 numerical comparator, and a DIP switch group SW9-SW12, the simulation display module includes indicator lights D1-D3 and a digital tube, the counter includes terminals Q1A-Q5A and Q1-Q4, the numerical comparator includes terminals A0-A3, B0-B3, and Q1-Q3, detectors 1-5 are electrically connected to terminals Q1A-Q5A of the counter, terminals Q1-Q4 of the counter are electrically connected to terminals B0-B3 of the numerical comparator 74HC85, terminals Q1-Q3 of the numerical comparator are electrically connected to one end of indicator lights D1-D3, and the other ends of indicator lights D1-D3 are connected in parallel and electrically connected to the ground terminal GND.

[0017] Compared with the prior art, the beneficial effects of this utility model are:

[0018] This invention uses a path selection module to select the wafer transfer path with a high-level signal, a speed adjustment module to adjust the wafer transfer speed, and a communication interface module to send the wafer transfer path and speed to the wafer transfer module. The wafer transfer module performs wafer transfer simulation based on the wafer transfer path sent by the path selection module and the wafer transfer speed sent by the speed adjustment module. An accuracy detection module is installed around the wafer carrier to detect whether the accuracy of the wafer placement position during wafer transfer meets the simulation requirements. The accuracy selection module is used to adjust the accuracy of the wafer placement position and send the result to the accuracy detection module. The speed detection module is used to detect the wafer transfer process time. The simulation display module is used to display the accuracy of the wafer placement position and the wafer transfer time.

[0019] This solution significantly improves the real-time performance and reliability of wafer transfer control by constructing a dynamic simulation optimization system entirely in hardware. The path selection and speed adjustment modules are directly controlled by level signals, avoiding the latency issues of software protocol parsing and reducing the wafer transfer command response time to the microsecond level. The hardware-level parallel processing mechanism of the accuracy detection and speed detection modules enables synchronous monitoring of wafer position offset and wafer transfer time. Combined with the integrated feedback of the simulation display module, this effectively improves debugging efficiency. The hardware comparison circuit design for accuracy thresholds achieves small positioning tolerance judgments without software intervention, effectively solving the false alarm problem caused by electromagnetic interference in traditional systems. This provides a highly robust wafer transfer control solution for semiconductor manufacturing equipment. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the overall system structure of this utility model;

[0022] Figure 2 This is a schematic diagram of the path selection module and speed adjustment module in this utility model;

[0023] Figure 3 This is a schematic diagram of the precision detection module and precision selection module in this utility model.

[0024] The diagram shows: Path selection module 10, speed adjustment module 20, communication interface module 30, chip transfer module 40, accuracy detection module 50, accuracy selection module 60, speed detection module 70, and simulation display module 80. Detailed Implementation

[0025] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0026] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0028] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0029] Example:

[0030] Please see Figures 1-3 This utility model provides a technical solution:

[0031] A dynamic simulation optimization system for wafer transfer in an RTP annealing furnace includes a path selection module 10, a speed adjustment module 20, a communication interface module 30, a wafer transfer module 40, a precision detection module 50, a precision selection module 60, a speed detection module 70, and a simulation display module 80, wherein:

[0032] The operational amplifier 10 of the path selection module is electrically connected to the operational amplifier 30 of the communication interface module. It is used to generate a high-level signal to control the wafer transfer path during wafer transfer and to send the wafer transfer path to the wafer transfer module through the operational amplifier 30 of the communication interface module.

[0033] Furthermore, the path selection module 10 includes a DIP switch group SW1-SW8, a 74H148 priority encoder, and a 74HC5951 first register. One end of the DIP switch group SW1-SW8 is connected in parallel and electrically connected to the power supply terminal VCC. The other end is connected to the IN0-IN7 terminals of the priority encoder. The priority encoder includes the IN0-IN7 terminals and the A0 terminal. The first register includes the SER terminal and the Q7S terminal. The A0 terminal of the priority encoder is electrically connected to the SER terminal of the first register.

[0034] The DIP switch group SW1-SW8 is an 8-bit independent switch used to manually select the chip transmission path. The 74HC148 priority encoder is used to convert the switch signal into binary code. The 74HC595 first register is an 8-bit serial shift register that converts the encoding result into a serial data stream.

[0035] The path selection module 10 selects the physical chip transfer path through DIP switch group SW1-SW8. When a DIP switch is closed, the corresponding pin is grounded, forming a high-level signal input to the IN0-IN7 terminals of the 74HC148 priority encoder. This priority encoder automatically converts the 8-channel switch signals into 3-bit binary codes based on hardware priority, with IN7 having the highest priority and IN0 the lowest, effectively resolving multi-path false triggering conflicts. The generated binary code is serially input to the SER terminal of the first register of the 74HC595 through the A0 terminal, and is sequentially shifted to the Q7S terminal to output the serial path code. At the same time, the chip's built-in latch function ensures stable data transmission. The entire path selection process is implemented entirely through hardware logic for signal conversion. The priority encoder eliminates signal conflicts, the shift register completes the parallel-to-serial conversion, and finally, the high-level path instruction is transmitted to the chip transfer module 40 via the RS485 differential signal of the communication interface module 30, avoiding software parsing delays.

[0036] The speed adjustment module 20 is electrically connected to the communication interface module 30 and is used to generate an analog voltage signal to control the chip transfer speed, which is then sent to the chip transfer module 40 through the communication interface module 30.

[0037] Furthermore, the speed adjustment module 20 includes an adjustment resistor R1, an LM358 operational amplifier, an ADC0804 digital-to-analog converter module, and a 74HC5952 second register. One end of the adjustment resistor R1 is electrically connected to the power supply terminal VCC, the other end is electrically connected to the ground terminal GND, and the middle end is electrically connected to the IN+ terminal of the operational amplifier. The operational amplifier includes an IN+ terminal, an IN- terminal, and an OUT terminal. The IN- terminal and the OUT terminal are electrically connected. The OUT terminal is electrically connected to the IN terminal of the digital-to-analog converter module. The digital-to-analog converter module includes an IN terminal and an OUT terminal. The second register includes a SER terminal and a Q7S terminal. The OUT terminal of the digital-to-analog converter module and the SER terminal of the second register are electrically connected. The communication interface module 30 is a MAX485 communication interface. The OUT terminals of the first register and the second register are connected in parallel and electrically connected to the DI terminal of the communication interface.

[0038] The adjustable resistor R1 provides an intuitive linear speed adjustment interface, the LM358 voltage follower eliminates the influence of load effects on voltage divider accuracy, the ADC0804 achieves quantization accuracy in hardware trigger mode, and the 74HC5952 second register is an 8-bit serial shift register that converts the encoded result into a serial data stream.

[0039] The speed adjustment module 20 changes the position of the center tap by rotating the adjustment resistor R1, buffering the 0-5V analog voltage through a voltage follower composed of an LM358 operational amplifier, and outputting a stable level to the IN terminal of the ADC0804 analog-to-digital converter module. The ADC0804 quantizes the analog voltage into a digital signal with 8-bit resolution. Its parallel output OUT terminal is connected to the parallel input IN terminal of the second register of the 74HC5952, and then shifts bit by bit through the SER terminal to the Q7S terminal to generate a serial speed code. At the same time, the first register synchronously transmits path selection data. The two signals are combined into a differential signal output through the DI terminal of the MAX485 communication interface.

[0040] The communication interface module 30 uses an MX90SM 485 communication connector, which is electrically connected to the operational amplifier 40 of the chip transfer module. It is used to transmit analog voltage signals and high-level signals between the operational amplifiers 10, 20, and 40 of the path selection module, the speed adjustment module, and the chip transfer module.

[0041] The wafer transfer module 40 uses a YASAKAWA wafer transfer robot, which is used to set the wafer transfer parameters according to the high-level signal sent by the operational amplifier 10 of the path selection module to select the wafer transfer path and the analog voltage signal sent by the operational amplifier 20 of the speed adjustment module to control the wafer transfer speed.

[0042] The accuracy detection module 50 is installed around the wafer carrier and is electrically connected to the operational amplifier of the simulation display module 80. It is used to detect the accuracy of the wafer placement position when the operational amplifier of the wafer transfer module 40 transfers the wafer, and generate accuracy data. After comparing the accuracy data with the accuracy threshold, the data exceeding the accuracy threshold is sent to the simulation display module 80.

[0043] The operational amplifier 60 of the precision selection module is electrically connected to the operational amplifier 50 of the precision detection module. It is used to adjust the precision threshold for accurate wafer placement and send the precision threshold to the operational amplifier 50 of the precision detection module.

[0044] Furthermore, the accuracy detection module 50 includes detectors 1-5, the accuracy selection module 60 includes a CD4520 counter, a 74HC85 numerical comparator, and a DIP switch group SW9-SW12, and the simulation display module 80 includes indicator lights D1-D3 and a digital tube. The counter includes terminals Q1A-Q5A and Q1-Q4, and the numerical comparator includes terminals A0-A3, B0-B3, and Q1-Q3. Detectors 1-5 are electrically connected to terminals Q1A-Q5A of the counter, terminals Q1-Q4 of the counter are electrically connected to terminals B0-B3 of the numerical comparator 74HC85, terminals Q1-Q3 of the numerical comparator are electrically connected to one end of indicator lights D1-D3, and the other ends of indicator lights D1-D3 are connected in parallel and electrically connected to the ground terminal GND.

[0045] The precision detection module 50 monitors the position offset detector in real time through detectors 1-5 distributed around the wafer carrier. It uses an EE-SX670 photoelectric sensor for non-contact position capture. When the wafer placement deviation fails to block the optical path of any detector, the corresponding detector outputs a high-level signal to trigger the enable pin of the CD4520 counter. The counter counts the number of valid high-level signals and outputs a 4-bit binary count value to the A0-A3 pins of the 74HC85 numerical comparator. The preset threshold codes of the DIP switches SW9-SW12 are connected to the B0-B3 pins of the comparator. The 74HC85 compares the actual offset with the set threshold using hardware logic. When the count value exceeds the threshold, Q1 outputs a high level to illuminate indicator D1; when it equals the threshold, Q2 triggers indicator D2; and when it is below the threshold, Q3 triggers indicator D3.

[0046] The speed detection module 70 uses a 555 counter, which is electrically connected to the operational amplifier 80 of the simulation display module. It is used to detect the time of the chip transfer process of the operational amplifier 40 of the chip transfer module and send it to the operational amplifier 80 of the simulation display module.

[0047] The simulation display module 80 uses an indicator light of model F3F5LED and a code tube display module of model TM1637 to display the accuracy of the wafer placement position and the wafer transfer time.

[0048] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A system for dynamic simulation and optimization of wafer handling in an RTP annealing furnace, comprising: a wafer handling system; a wafer handling controller; a wafer handling simulation system; and a wafer handling optimization system. include: The path selection module (10) is electrically connected to the communication interface module (30) and is used to generate a high-level signal to control the wafer transfer path during wafer transfer and send the wafer transfer path to the wafer transfer module (40) through the communication interface module (30). Speed ​​adjustment module (20), which is electrically connected to communication interface module (30), is used to generate an analog voltage signal to control the chip transfer speed and send it to chip transfer module (40) through communication interface module (30); The communication interface module (30) is electrically connected to the chip transfer module (40) and is used to transmit analog voltage signals and high-level signals between the path selection module (10), the speed adjustment module (20) and the chip transfer module (40). The chip transfer module (40) is used to set chip transfer parameters according to the high-level signal sent by the path selection module (10) to select the chip transfer path and the analog voltage signal sent by the speed adjustment module (20) to control the chip transfer speed. The precision detection module (50) is installed around the wafer carrier and electrically connected to the simulation display module (80). It is used to detect the precision of the wafer placement position when the wafer transfer module (40) transfers the wafer, and generate precision data. After comparing the precision data with the precision threshold, the data exceeding the precision threshold is sent to the simulation display module (80). A precision selection module (60) is electrically connected to a precision detection module (50) for adjusting the precision threshold for accurate wafer placement and sending the precision threshold to the precision detection module (50). Speed ​​detection module (70), which is electrically connected to simulation display module (80), is used to detect the time of the chip transfer process of chip transfer module (40) and send it to simulation display module (80); The simulation display module (80) is used to display the accuracy of the wafer placement position and the wafer transfer time.

2. The RTP anneal furnace wafer transfer dynamic simulation optimization system of claim 1, wherein: The path selection module (10) includes a DIP switch group SW1-SW8, a 74H148 priority encoder, and a 74HC595 first register. One end of the DIP switch group SW1-SW8 is connected in parallel and electrically connected to the power supply terminal VCC. The other end is connected to the IN0-IN7 terminals of the priority encoder. The priority encoder includes the IN0-IN7 terminals and the A0 terminal. The first register includes the SER terminal and the Q7S terminal. The A0 terminal of the priority encoder is electrically connected to the SER terminal of the first register.

3. The RTP anneal furnace wafer transfer dynamic simulation optimization system of claim 1, wherein: The speed adjustment module (20) includes an adjustment resistor R1, an LM358 operational amplifier, an ADC0804 digital-to-analog converter module, and a 74HC595 second register. One end of the adjustment resistor R1 is electrically connected to the power supply terminal VCC, the other end is electrically connected to the ground terminal GND, and the middle end is electrically connected to the IN+ terminal of the operational amplifier. The operational amplifier includes an IN+ terminal, an IN- terminal, and an OUT terminal. The IN- terminal and the OUT terminal are electrically connected. The OUT terminal is electrically connected to the IN terminal of the digital-to-analog converter module. The digital-to-analog converter module includes an IN terminal and an OUT terminal. The second register includes a SER terminal and a Q7S terminal. The OUT terminal of the digital-to-analog converter module and the SER terminal of the second register are electrically connected. The communication interface module (30) is a MAX485 communication interface. The OUT terminal of the first register and the OUT terminal of the second register are connected in parallel and electrically connected to the DI terminal of the communication interface.

4. The RTP anneal wafer transfer dynamic simulation optimization system of claim 1, wherein: The accuracy detection module (50) includes detectors 1-5. The accuracy selection module (60) includes a CD4520 counter, a 74HC85 numerical comparator, and a DIP switch group SW9-SW12. The simulation display module (80) includes indicator lights D1-D3 and a digital tube. The counter includes terminals Q1A-Q5A and Q1-Q4. The numerical comparator includes terminals A0-A3, B0-B3, and Q1-Q3. Detectors 1-5 are electrically connected to terminals Q1A-Q5A of the counter. Terminals Q1-Q4 of the counter are electrically connected to terminals B0-B3 of the numerical comparator 74HC85. Terminals Q1-Q3 of the numerical comparator are electrically connected to one end of indicator lights D1-D3. The other ends of indicator lights D1-D3 are connected in parallel and electrically connected to ground terminal GND.

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