STS8200-based wafer test circuit
By designing a wafer test circuit based on STS8200 and combining multiple test units with the STS8200 tester, simultaneous testing of four chips was achieved, solving the problem of low chip testing efficiency in existing technologies and improving work efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HEXIN SEMICON TECH (SUZHOU) CO LTD
- Filing Date
- 2025-04-27
- Publication Date
- 2026-04-21
AI Technical Summary
In existing technologies, the testing efficiency of integrated circuit chips is low, and it is impossible to test multiple chips simultaneously.
Design an STS8200-based wafer test circuit, which connects multiple chips under test through a tester and a circuit board. It performs multiple tests using a mixed-signal unit, an O/S open/short circuit test unit, a high-voltage power supply test unit, a voltage test unit, and an ACM/QUMe mixed test unit, and achieves synchronous testing of multiple chips by combining with the STS8200 tester.
It enables simultaneous testing of four chips under test, significantly improving testing efficiency.
Smart Images
Figure CN224152609U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to a wafer testing circuit based on STS8200, and more particularly to a wafer testing circuit based on STS8200 quad-side positioning. Background Technology
[0002] Integrated circuits (ICs) are small in size and powerful in function, making them an indispensable electronic component in information equipment. To ensure proper functioning, chips must undergo rigorous testing before leaving the factory. A common testing method involves inputting known test signals into the chip's circuitry and then obtaining the feedback signal to determine if the chip is functioning correctly. However, typical chip testing only allows for single-chip testing, resulting in relatively low efficiency.
[0003] In view of the above-mentioned shortcomings, the designer actively researched and innovated in order to create a new type of STS8200 wafer test circuit with greater industrial application value. Utility Model Content
[0004] To solve the above-mentioned technical problems, the purpose of this utility model is to provide a wafer test circuit based on STS8200.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] An STS8200-based wafer testing circuit includes a tester and a circuit board. A chip under test (DUT) is connected to the circuit board, as is a power supply unit. The output of the power supply unit is connected to the input of the DUT. The mixed-signal (MS / DS) terminal of the DUT is connected to the input of the MS / DS unit. The open / short circuit (O / S) test terminal of the DUT is connected to the input of the O / S test unit. The high-voltage power supply terminal of the DUT is connected to the input of the high-voltage power supply test unit. The voltage terminal of the DUT is connected to the input of the voltage test unit. The ground plane terminal of the DUT is connected to the input of the tester. The ACM / QUMe terminal of the DUT is connected to the input of the ACM / QUMe mixed-signal test unit. The outputs of the MS / DS unit, the O / S test unit, the high-voltage power supply test unit, the voltage test unit, and the ACM / QUMe mixed-signal test unit are connected to the input of the tester.
[0007] Preferably, in the STS8200 wafer testing circuit, the testing machine is an STS8200 testing machine.
[0008] Preferably, in the STS8200-based wafer testing circuit, a pin card is connected to the circuit board, and the chip under test is plugged into the pin card.
[0009] Preferably, in the STS8200-based wafer testing circuit, there are four pin cards, which are independently connected to the circuit board.
[0010] By means of the above solution, this utility model has at least the following advantages:
[0011] This invention enables simultaneous testing of four chips under test, effectively improving work efficiency.
[0012] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0013] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0014] Figure 1 This is a schematic diagram of the principle of this utility model;
[0015] Figure 2 This is a circuit diagram of the mixed-signal unit of this utility model;
[0016] Figure 3 This is the circuit diagram of the O / S open / short circuit test unit of this utility model;
[0017] Figure 4 This is a circuit diagram of the high-voltage power supply test unit of this utility model;
[0018] Figure 5 This is a circuit diagram of the voltage testing unit of this utility model;
[0019] Figure 6 This is the circuit diagram of the ACM / QUMe hybrid test unit of this utility model. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0022] Example
[0023] like Figures 1 to 6 As shown, an STS8200-based wafer testing circuit includes a tester 1 and a circuit board 2. A chip under test (DUT) 3 is connected to the circuit board 2. A power supply unit 4 is also connected to the circuit board 2. The output of the power supply unit 4 is connected to the input of the DUT 3. The mixed analog-to-digital (MADC) terminal of the DUT 3 is connected to the input of a mixed analog-to-digital (MADC) unit 5. The open / short circuit (O / S) test terminal of the DUT 3 is connected to the input of an O / S O / S O / S test unit 6. The high-voltage power supply terminal of the DUT 3 is connected to the input of a high-voltage power supply test unit 7. The voltage terminal of the DUT 3 is connected to the input of a voltage test unit 8. The ground plane terminal of the DUT 3 is connected to the input of the tester 1. The ACM / QUMe terminal of the DUT 3 is connected to the input of an ACM / QUMe mixed-signal test unit 9. The outputs of the mixed-signal unit 5, the O / S O / S O / S test unit 6, the high-voltage power supply test unit 7, the voltage test unit 8, and the ACM / QUMe mixed-signal test unit 9 are connected to the input of the tester 1.
[0024] The testing machine 1 described in this utility model is an STS8200 testing machine.
[0025] In this invention, a pin clip is connected to the circuit board 2, and the chip under test 3 is inserted into the pin clip. There are four pin clips, each independently connected to the circuit board 2. These four pin clips allow for simultaneous testing of four chips under test, effectively improving work efficiency.
[0026] The working principle of this utility model is as follows:
[0027] In practice, the chip under test (model HE1106_CP) is tested according to the required test units, namely the mixed analog-to-digital unit 5, O / S open / short circuit test unit 6, high voltage power supply test unit 7, voltage test unit 8, and ACM / QUMe mixed test unit 9. After the chip under test is inserted into the pin card, it is connected to the STS8200 tester through different test units on the circuit board. Then, the STS8200 tester performs functional tests on the different test units of the chip under test. The chip under test that passes the test is displayed by the tester.
[0028] The STS8200 testing machine in this utility model is a conventional testing device known to those skilled in the art, and will not be described in any further detail.
[0029] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0030] In the description of this application, it should be noted that the terms "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0031] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or vertical, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.
[0032] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0033] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. A STS8200 wafer test circuit based on, comprising a tester (1) and a circuit board (2), the circuit board (2) is connected with a chip (3) to be tested, characterized in that: A power supply unit (4) is connected to the circuit board (2). The output terminal of the power supply unit (4) is connected to the input terminal of the chip under test (3). The analog-to-digital (ADC) terminal of the chip under test (3) is connected to the input terminal of the ADC unit (5). The O / S open / short circuit test terminal of the chip under test (3) is connected to the input terminal of the O / S open / short circuit test unit (6). The high voltage power supply terminal of the chip under test (3) is connected to the input terminal of the high voltage power supply test unit (7). The voltage terminal of the chip under test (3) is connected to the power supply unit (7). The input terminal of the voltage test unit (8) is connected, the ground plane terminal of the chip under test (3) is connected to the input terminal of the test machine (1), the ACM / QUMe terminal of the chip under test (3) is connected to the input terminal of the ACM / QUMe hybrid test unit (9), and the output terminals of the analog-digital hybrid unit (5), O / S open-circuit and short-circuit test unit (6), high voltage power supply test unit (7), voltage test unit (8) and ACM / QUMe hybrid test unit (9) are connected to the input terminal of the test machine (1). 2. The STS8200 wafer test circuit according to claim 1, wherein: The test machine (1) is an STS8200 test machine.
3. The STS8200 wafer test circuit according to claim 1, wherein: A pin card is connected to the circuit board (2), and the chip to be tested (3) is plugged into the pin card.
4. The STS8200 wafer test circuit according to claim 3, wherein: The pin card has four pins, which are independently connected to the circuit board (2).