Sectional driving framework for detecting and adjusting slew rate of BOOST power tube

Abstract

The utility model relates to a sectional driving framework for detecting and adjusting the slew rate of a BOOST power tube, which comprises a logic and dead zone module for receiving a PWM (Pulse Width Modulation) signal, and a level shift module, a high-side driving circuit and a high-side power tube which are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module, the low-side driving circuit and the low-side power tube are sequentially connected with the logic and dead zone module, the slope detection and dynamic adjustment module is connected with a source electrode of the high-side power tube and a drain electrode of the low-side power tube, and the logic and dead zone module processes the PWM signal and then generates a switch control signal. The slope detection and dynamic adjustment module receives the switch control signal, detects the slew rate of the low-side power tube when the low-side power tube is turned off, and controls the parallel number of driving tubes in the low-side driving circuit according to a detection result, and the low-side driving circuit outputs a low-side driving signal according to the parallel number of the driving tubes; and the low-side driving signal controls the on and off of the low-side power tube.

Description

Technical Field

[0001] This utility model relates to the field of gate drive technology for BOOST power transistors, and particularly to the detection and regulation of the voltage change rate of a power transistor driven by a gate driver. More specifically, it relates to a segmented drive architecture for detecting and regulating the slew rate of a BOOST power transistor. Background Technology

[0002] Thanks to the superior conductivity of metal-oxide-semiconductor field-effect transistors (MOSFETs), the switching frequency (F) of BOOST power converters is... SW It can surge to several megahertz or even tens of megahertz, while significantly improving BOOST power efficiency.

[0003] However, during the switching process of a MOSFET power transistor, due to the distributed capacitance (C) between the input and output... GS Under the influence of inverting amplification, the equivalent input capacitance is amplified, creating a "Miller plateau" that slows down the switching process. Simultaneously, the Miller plateau reduces the drain-source voltage Vd of the power transistor. DS and leakage current I D There is significant overlap between them, leading to energy loss, increased power consumption, and decreased system stability.

[0004] As the switching speed increases, the gate drive current I of the power transistor can be increased. G To increase dI / dt (i.e., leakage current I) D The slope) and dV / dt (i.e., drain-source voltage V) DS The slope of dI / dt and dV / dt can be used to accelerate switching on or off, reduce the effect of the Miller plateau, and minimize energy loss. However, excessively large dI / dt and dV / dt can result in a very steep V. DS Voltage transients and I D Current transients can lead to reliability issues such as EMI noise and gate oscillation. More seriously, due to the parasitic inductance at the chip's pin terminals, during switching (especially during the turn-off of the low-side power transistor on the BOOST side), excessively rapid inductor current commutation (excessively large dI / dt) can cause a voltage drop across the parasitic inductor, increasing the drain-source voltage V on the power transistor. DS This can cause a large overshoot, increasing the risk of the power transistor being damaged.

[0005] To slow down the commutation speed of inductor current during switching and reduce the overshoot voltage drop on the power transistor, there are currently two active gate control techniques: 1) Digital open-loop method, which can achieve segmented updates during switching transients, but the complex digital algorithm and the performance of the gate drive process limit its application in the drive circuit, and the control sequence in this method cannot adapt to changes in load and input voltage; 2) Adding a gate resistor to the gate of the power transistor. This technique can reduce the gate charging and discharging current, thereby reducing dI / dt and dV / dt, but this method sacrifices the switching speed of the MOSFET and greatly increases the conduction delay and switching losses. Summary of the Invention

[0006] To address the problems in the prior art, this invention provides a segmented drive architecture for BOOST power transistor slew rate detection and adjustment. Without affecting switching speed and switching losses, it reduces voltage overshoot caused by excessively rapid current commutation on parasitic inductors during switching, thereby improving system stability.

[0007] This utility model provides a segmented drive architecture for BOOST power transistor slew rate detection and adjustment, including a logic and dead-time module for receiving PWM signals, a level shift module, a high-side drive circuit, and a high-side power transistor connected sequentially to the logic and dead-time module, and a slope detection and dynamic adjustment module, a low-side drive circuit, and a low-side power transistor connected sequentially to the logic and dead-time module. The slope detection and dynamic adjustment module is connected to the source of the high-side power transistor and the drain of the low-side power transistor, respectively. The logic and dead-time module processes the PWM signal to generate a switch control signal. The slope detection and dynamic adjustment module receives the switch control signal and, when the low-side power transistor is turned off, detects the slew rate of the low-side power transistor and controls the number of parallel drive transistors in the low-side drive circuit according to the detection result. The low-side drive circuit outputs a low-side drive signal according to the number of parallel drive transistors, and the low-side drive signal controls the on and off of the low-side power transistor.

[0008] Furthermore, the two output terminals of the logic and dead-time module are respectively connected to the input terminal of the level shift module and the first input terminal of the slope detection and dynamic adjustment module. The output terminal of the level shift module is connected to the input terminal of the high-side drive circuit, and the output terminal of the high-side drive circuit is connected to the gate of the high-side power transistor.

[0009] Furthermore, the output terminal of the slope detection and dynamic adjustment module is connected to the input terminal of the low-side driving circuit, the output terminal of the low-side driving circuit is connected to the gate of the low-side power transistor, and the drain of the low-side power transistor is connected to the source of the high-side power transistor and the second input terminal of the slope detection and dynamic adjustment module, respectively.

[0010] Furthermore, the drain of the low-side power transistor is connected to an external inductor, and the drain of the high-side power transistor is connected to an external load.

[0011] Furthermore, the slope detection and dynamic adjustment module includes a slope detector, a VI converter, and a current comparator connected in sequence. The slope detector detects the rate of change of the drain-source voltage of the low-side power transistor and converts the rate of change of the drain-source voltage into a changing voltage signal. The VI converter converts the changing voltage signal into a changing current signal. The changing current signal is compared with a preset current threshold in the current comparator to detect whether the rate of change of the drain-source voltage of the low-side power transistor reaches a preset value, so as to output a drive control signal to control the low-side drive circuit.

[0012] Furthermore, the output terminal of the slope detector is connected to the input terminal of the VI converter, the output terminal of the VI converter is connected to the input terminal of the current comparator, and the output terminal of the current comparator outputs the drive control signal.

[0013] Furthermore, both the high-side driving circuit and the low-side driving circuit include n PMOS driving transistors and n NMOS driving transistors, where n is a positive integer.

[0014] Furthermore, the sources of the first PMOS transistor, the second PMOS transistor, ..., and the nth PMOS transistor are connected together and connected to the input power supply; the drains of the first PMOS transistor, the second PMOS transistor, ..., and the nth PMOS transistor, the drains of the first NMOS transistor, the second NMOS transistor, ..., and the nth NMOS transistor are connected together; the sources of the first NMOS transistor, the second NMOS transistor, ..., and the nth NMOS transistor are all grounded; the gates of the first PMOS transistor, the second PMOS transistor, ..., and the nth PMOS transistor, the first NMOS transistor, the second NMOS transistor, ..., and the nth NMOS transistor are all connected to the output of the driving circuit.

[0015] This invention, while ensuring a large dV / dt and without affecting switching speed and switching losses, allows the slope detection and dynamic adjustment module to adjust the number of driving transistors in the inductor current commutation stage according to the power transistor's withstand voltage and actual needs. This adjusts the current magnitude and the inductor current commutation speed dI / dt, reducing the voltage drop across the parasitic inductor and the overshoot voltage on the power transistor, thereby improving the system's stability and reliability. This invention has a simple structure, low operating cost, and is safe and reliable. Attached Figure Description

[0016] Figure 1This is a basic block diagram of the segmented drive architecture for BOOST power transistor slew rate detection and adjustment according to this utility model.

[0017] Figure 2 This is a schematic diagram of the segmented drive architecture for BOOST power transistor slew rate detection and adjustment according to this utility model.

[0018] Figure 3 yes Figure 1 A schematic diagram of the slope detection and dynamic adjustment module.

[0019] Figure 4 yes Figure 1 Schematic diagram of the driving circuit structure.

[0020] Figure 5 This is a schematic diagram of the segmented drive architecture for BOOST power transistor slew rate detection and adjustment according to this utility model.

[0021] Figure 6 This is a waveform diagram of the segmented drive architecture for BOOST power transistor slew rate detection and adjustment according to this utility model. Detailed Implementation

[0022] To make the objectives, solutions, and advantages of this utility model clearer, the specific structure and working principle of this utility model will be described in more detail below with reference to the accompanying drawings. The embodiments described are only for explaining this utility model and are not limited to these embodiments, nor are they intended to limit the scope of application of this utility model.

[0023] The purpose of the following content is to provide the public with a clearer understanding of this utility model. However, those skilled in the art can clearly understand this utility model even without the following detailed description.

[0024] like Figure 1As shown, the present invention provides a segmented drive architecture for BOOST power transistor slew rate detection and adjustment, including a logic and dead-time module 10 for receiving PWM signals, a level shift module 21, a high-side drive circuit 22 and a high-side power transistor 23 connected in sequence to the logic and dead-time module 10, and a slope detection and dynamic adjustment module 31, a low-side drive circuit 32 and a low-side power transistor 33 connected in sequence to the logic and dead-time module 10. The slope detection and dynamic adjustment module 31 is connected to the source of the high-side power transistor 23 and the drain of the low-side power transistor 33, respectively. The logic and dead-time module 10 is also connected to the low-side drive circuit 32. The logic and dead-time module 10 performs a series of processing on the PWM signal, such as delay and inversion, to generate a first switch control signal and a second switch control signal. The first switch control signal is converted into a high-side drive signal after passing through the level shift module 21 and the high-side drive circuit 22. The high-side drive signal controls the on and off of the high-side power transistor 23. The slope detection and dynamic adjustment module 31 receives the second switch control signal and simultaneously detects the slew rate of the low-side power transistor 33. Based on the detection result, it controls the number of parallel drive transistors in the low-side drive circuit 32. The low-side drive circuit 32 outputs a low-side drive signal based on the number of parallel drive transistors and the received second switch control signal. The low-side drive signal controls the on and off of the low-side power transistor 33.

[0025] More specifically, the two outputs of the logic and dead-time module 10 are connected to the input of the level shift module 21 and the first input of the slope detection and dynamic adjustment module 31, respectively. The output of the level shift module 21 is connected to the input of the high-side drive circuit 22. The level shift module 21 is used to shift the low-voltage rail controlled switch signal into a high-voltage rail controlled switch control signal. The output of the high-side drive circuit 22 is connected to the gate of the high-side power transistor 23. The output of the slope detection and dynamic adjustment module 31 is connected to the input of the low-side drive circuit 32. The output of the low-side drive circuit 32 is connected to the gate of the low-side power transistor 33. The drain of the low-side power transistor 33 is connected to the source of the high-side power transistor 23 and the second input of the slope detection and dynamic adjustment module 31, respectively. The drain of the low-side power transistor 33 is connected to an external inductor, and the drain of the high-side power transistor 23 is connected to an external load.

[0026] like Figure 2The diagram shows a detailed structural schematic of the segmented drive architecture for BOOST power transistor slew rate detection and adjustment of this utility model. It includes a logic and dead-time module 10, a level shift module 21, a high-side drive circuit 22, and a high-side power transistor 23 connected in sequence to the logic and dead-time module 10, and a slope detection and dynamic adjustment module 31, a low-side drive circuit 32, and a low-side power transistor 33 connected in sequence to the logic and dead-time module 10. The slope detection and dynamic adjustment module 31 is connected to the source of the high-side power transistor 23 and the drain of the low-side power transistor 33, respectively. The logic and dead-time module 10 is also connected to the low-side drive circuit 32. The level shifting module 21 consists of two level shifting circuits with high and low potential voltage differences of VH1 and VH2, respectively. The logic and dead-time module 10 performs a series of processing on the PWM signal, such as delay and inversion, to generate a first switch control signal and a second switch control signal, both with power rails from GND to VBAT. The first switch control signal shifts the power rails to VBST to VBST+VH1 and VSW to VSW+VH2, respectively, after passing through the level shifting module 21. Then, it is converted into a high-side drive signal after passing through the high-side drive circuit 22. The high-side drive signal controls the on and off of the high-side power transistor 23. The slope detection and dynamic adjustment module 31 receives the second switch control signal and detects the slew rate of the low-side power transistor 33. Based on the detection result, it controls the number of parallel drive transistors in the low-side drive circuit 32. The low-side drive circuit 32 outputs a low-side drive signal based on the number of parallel drive transistors and the received second switch control signal. The low-side drive signal controls the on and off of the low-side power transistor 33.

[0027] like Figure 3 The diagram shows a schematic of the slope detection and dynamic adjustment module of this invention. The slope detection and dynamic adjustment module 31 includes a slope detector 311, a VI converter 312, and a current comparator 313 connected in sequence. The output terminal of the slope detector 311 is connected to the input terminal of the VI converter 312, and the output terminal of the VI converter 312 is connected to the input terminal of the current comparator 313. The output terminal of the current comparator 313 outputs a drive control signal to control the low-side drive circuit 32. The working principle of this module is as follows: the slope detector detects the rate of change of the drain-source voltage of the low-side power transistor 33 at the switching node SW, and converts the rate of change of the drain-source voltage into a changing voltage signal, which is output to the VI converter 312. The VI converter 312 converts the changing voltage signal into a changing current signal, which is output to the current comparator 313. The changing current signal is compared with a preset current threshold in the current comparator 313 to detect whether the rate of change of the drain-source voltage has reached the preset value, thereby outputting a drive control signal to control the low-side drive circuit 32.

[0028] like Figure 4The diagram shows a schematic of the driving circuit of this invention. The driving circuit includes several PMOS driving transistors and several NMOS driving transistors, formed by the parallel connection of the source and drain of MOS devices of the same size. The switching control signal is a switching control signal jointly output by the logic and dead-time module 10 and the slope detection and dynamic adjustment module 31, used to control the switching of the PMOS and NMOS in the driving circuit. Taking the low-side driving circuit as an example, it includes n (n is a positive integer) PMOS driving transistors and n NMOS driving transistors. Specifically, the source of the first PMOS transistor PM1, the source of the second PMOS transistor PM2, ..., the source of the nth PMOS transistor PMn are connected together and connected to the BOOST input power supply VBAT. The drains of the first PMOS transistor PM1, the drain of the second PMOS transistor PM2, ..., the drain of the nth PMOS transistor PMn, the drain of the first NMOS transistor NM1, the drain of the second NMOS transistor NM2, ... The drains of the nth NMOS transistor NMn are connected together, and this connection point is set as the BOOST switch node SW. The sources of the first NMOS transistor NM1, the second NMOS transistor NM2, ..., the nth NMOS transistor NMn are all grounded. The gates of the first PMOS transistor PM1, the second PMOS transistor PM2, ..., the nth PMOS transistor PMn, the first NMOS transistor NM1, the second NMOS transistor NM2, ..., the nth NMOS transistor NMn are all connected to the input of the drive circuit. The structure of the high-side drive circuit is the same as that of the low-side drive circuit, and will not be described again here.

[0029] like Figure 5 The diagram shows the operation of the segmented drive architecture of this invention when the low-side power transistor is turned off and the high-side power transistor is turned on; as shown... Figure 6 The diagram shown illustrates the working waveform of the low-side power transistor under segmented drive control.

[0030] At the initial moment t1 when the low-side power transistor is turned off, the drive circuit uses the drive current I1 as the gate-source capacitance C of the MOS transistor. GS Discharge, gate-source voltage V of the power transistor GS Gradually decreasing, gate-source voltage V GS With MOS threshold voltage V TH The difference is greater than the drain-source voltage V of the MOS at this time. DS The power transistor is in the linear region.

[0031] At time t2, the gate-source voltage V of the power transistor is... GS Descending to V M Gate-source voltage V GS With MOS threshold voltage V TH The difference is exactly equal to the drain-source voltage V of the MOS at this time. DS The power transistor enters the saturation region. Next, the drive current I...G No longer the gate-source capacitance C of the MOS GS Instead of discharging, it is converted into the MOS gate-drain capacitance C. GD Charging, C GD The charging process causes the drain voltage of the MOS to gradually rise, thereby increasing the drain-source voltage V of the MOS. DS The voltage gradually increases at a rate of VS1. The MOS drain-source voltage V0 DS The magnitudes of the rising rates dV / dt are related as follows:

[0032] dV / dt=I G / C GD (1)

[0033] From equation (1), it can be seen that the gate-drain parasitic capacitance C of the MOS GD When the size is fixed, the drain-source voltage V of the MOS DS The magnitude of the rise rate dV / dt is related to the MOS gate drive current I. G The size is directly proportional to the size.

[0034] Since the gate drive current is always equal to the MOS gate drain capacitance C at this time... GD Charging, while the MOS gate-source capacitance C GS The voltage on the MOS gate-source voltage V did not change, therefore the MOS gate-source voltage V GS At this point, the process remains unchanged, entering the Miller plateau, where the MOS switching process becomes slower. The presence of the Miller plateau causes the MOS drain-source voltage V to... DS and leakage current I D There is significant overlap between these currents, leading to energy loss and increased power consumption. Therefore, the gate drive current I is typically increased during the initial turn-off phase of the MOSFET. G This increases dV / dt, thereby accelerating MOS turn-off, reducing the impact of the Miller plateau, and minimizing energy loss.

[0035] At time t3, the drain-source voltage V of the MOS DS Increased to the maximum value, the size is approximately V. BST The Miller plateau ends. At this point, the MOS gate drive current I... G No longer the gate-drain capacitance C of the MOS GD Instead of charging, it continues to charge the MOS gate-source capacitor C. GS Discharge, MOS gate-source voltage V GS The leakage current I in the MOS saturation region continues to decrease. D Size:

[0036]

[0037] Among them, u n C represents the carrier mobility. oxHere, W represents the gate oxide capacitance per unit area, and L represents the gate channel width and gate channel length of the MOS, respectively.

[0038] From equation (2), we can see that V GS The decrease in MOSFET leakage current I D From the maximum value I DM It begins to decrease gradually at a rate of IS1, and the inductor current enters the commutation stage and gradually flows from the low-side power transistor to the high-side power transistor.

[0039] Although at time t3, the MOS drain-source voltage V DS It has been increased to the maximum value V BST However, due to the parasitic inductance L at the VBST terminal P1 and ground parasitic inductance L P1 The existence (assuming L at this time) P1 =L P2 The commutation of inductor current from the low side to the high side causes a changing current in the two parasitic inductors, which in turn generates a changing voltage ΔV across the parasitic inductors. P1 Its size is:

[0040]

[0041] Therefore, the drain-source voltage drop V on the low-side power MOSFET DS Then it will be from V BST Gradually overshooting until time t4, the MOS gate-source voltage V GS Drop to MOS threshold voltage V TH When the power transistor is turned off, the inductor current commutation ends, and the drain-source voltage drop V... DS At this point, the overshoot reaches its maximum value (V). BST +2ΔV P1 From equation (3), it can be seen that the larger the value of the parasitic inductance, the faster the inductor current commutation speed, and the greater the voltage drop generated on the parasitic inductance, the greater the drain-source voltage drop V of the MOS. DS The greater the voltage drop it bears, the greater the risk of the power transistor being damaged.

[0042] To slow down the commutation speed of the inductor current, reduce the voltage drop across the parasitic inductance and the drain-source overshoot voltage on the power transistor, prevent the power transistor from being damaged, and at the same time ensure a large dV / dt to improve the switching speed and reduce losses, this invention provides a segmented driving method.

[0043] Starting at time t2, the slope detection and dynamic adjustment module can detect the rate of change dV / dt of the drain-source voltage of the low-side power transistor at the switch node SW, and convert the value of this rate of change into a changing current signal to compare with a preset current threshold. If the rate of change dV / dt of the drain-source voltage is greater than the set threshold, after a delay of t2 - t3, the slope detection and dynamic adjustment module will output a drive control signal at time t3 to reduce the number of parallel-connected drive transistors in the drive circuit, so that the MOS gate drive current is reduced to I2 (I2 < I1) at the initial moment t3 of the inductor current commutation, and the size of t2 is used to charge C GS discharge, V GS The rate of decline slows down, and then the MOS drain current I D The commutation speed is reduced to IS2 (IS2 < IS1). From Equation (3), it can be seen that the voltage drop generated on the parasitic inductor drops to ΔV P2 (ΔV P2 < ΔV P1 ). At time t5, the power transistor is turned off, and the inductor current commutation ends. The maximum value of the overshoot of the drain-source voltage drop V DS drops to VBST + 2ΔV P2 . In short, the slope detection and dynamic adjustment module can effectively reduce the voltage drop between the drain and source of the power MOS transistor by reducing the number of parallel-connected drive transistors in the drive circuit, thereby effectively avoiding the breakdown of the power MOS transistor.

[0044] The present invention provides a segmented drive architecture for detecting and adjusting the slew rate of a BOOST power transistor. In order to ensure a large dV / dt and effectively control dI / dt without affecting the switching speed and switching loss, this drive architecture still uses a relatively large drive current to charge C at the initial stage of the turn-off of the BOOST low-side power transistor GS discharge, reduce the influence of the Miller plateau, and at the same time detect dV / dt; the slope detection and dynamic adjustment module can adjust the number of drive transistors in the drive circuit during the inductor current commutation stage according to the breakdown voltage of the power transistor and the actual requirements to reduce the drive current, effectively reducing the inductor current commutation speed and the drain current I D The reduction speed, effectively reducing the voltage drop on the parasitic inductor and the overshoot voltage on the power transistor, effectively reducing the risk of breakdown of the power transistor, improving the overall reliability of the driver, achieving a simple structure, reducing the use cost, and being safe and reliable.

[0045] The above is only the preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. That is, all simple, equivalent changes and modifications made according to the claims and the content of the specification of the present invention application fall within the scope of the claims of the present invention patent. What is not described in detail in the present invention is all conventional technical content.

Claims

1. A segmented drive architecture with BOOST power tube swing rate detection regulation, characterized by, It includes a logic and dead-time module for receiving PWM signals, a level shift module, a high-side drive circuit and a high-side power transistor connected in sequence to the logic and dead-time module, and a slope detection and dynamic adjustment module, a low-side drive circuit and a low-side power transistor connected in sequence to the logic and dead-time module. The slope detection and dynamic adjustment module is connected to the source of the high-side power transistor and the drain of the low-side power transistor, respectively. The logic and dead-time module processes the PWM signal to generate a switching control signal. The slope detection and dynamic adjustment module receives the switching control signal and detects the slew rate of the low-side power transistor when it is turned off. Based on the detection result, it controls the number of parallel drive transistors in the low-side drive circuit. The low-side drive circuit outputs a low-side drive signal based on the number of parallel drive transistors. The low-side drive signal controls the on and off of the low-side power transistor.

2. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 1, wherein, The two outputs of the logic and dead-time module are respectively connected to the input of the level shift module and the first input of the slope detection and dynamic adjustment module. The output of the level shift module is connected to the input of the high-side drive circuit, and the output of the high-side drive circuit is connected to the gate of the high-side power transistor.

3. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 2, wherein, The output terminal of the slope detection and dynamic adjustment module is connected to the input terminal of the low-side driving circuit. The output terminal of the low-side driving circuit is connected to the gate of the low-side power transistor. The drain of the low-side power transistor is connected to the source of the high-side power transistor and the second input terminal of the slope detection and dynamic adjustment module, respectively.

4. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 1, wherein, The drain of the low-side power transistor is connected to an external inductor, and the drain of the high-side power transistor is connected to an external load.

5. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 1, wherein, The slope detection and dynamic adjustment module includes a slope detector, a VI converter, and a current comparator connected in sequence. The slope detector detects the rate of change of the drain-source voltage of the low-side power transistor and converts the rate of change of the drain-source voltage into a changing voltage signal. The VI converter converts the changing voltage signal into a changing current signal. The changing current signal is compared with a preset current threshold in the current comparator to detect whether the rate of change of the drain-source voltage of the low-side power transistor reaches a preset value, so as to output a drive control signal to control the low-side drive circuit.

6. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 5, wherein, The output terminal of the slope detector is connected to the input terminal of the VI converter, the output terminal of the VI converter is connected to the input terminal of the current comparator, and the output terminal of the current comparator outputs the drive control signal.

7. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 1, wherein, Both the high-side drive circuit and the low-side drive circuit include n PMOS drive transistors and n NMOS drive transistors, where n is a positive integer.

8. The segmented drive architecture for BOOST power tube swing rate detection regulation of claim 7, wherein, The sources of the first PMOS transistor, the second PMOS transistor, ..., and the nth PMOS transistor are connected together and connected to the input power supply; the drains of the first PMOS transistor, the second PMOS transistor, ..., the nth PMOS transistor, the first NMOS transistor, the second NMOS transistor, ..., and the nth NMOS transistor are connected together; the sources of the first NMOS transistor, the second NMOS transistor, ..., and the nth NMOS transistor are all grounded; the gates of the first PMOS transistor, the second PMOS transistor, ..., the nth PMOS transistor, the first NMOS transistor, the second NMOS transistor, ..., and the nth NMOS transistor are all connected to the output of the driving circuit.

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