Pixel array and image sensor

Abstract

The utility model discloses a pixel array and an image sensor. In the pixel array, boundary pixel columns of a boundary pixel array are correspondingly connected with internal pixel columns of an internal pixel array; at least two internal pixel units in the internal pixel column are connected through a transistor multiplexing unit, and the internal pixel units, adjacent to the boundary pixel units, in the multiple rows of internal pixel units of the internal pixel column are connected with the corresponding boundary pixel units through the transistor multiplexing units; each internal pixel unit comprises at least two pixel circuits, and the number of the pixel circuits included in the boundary pixel units in the boundary pixel columns is the same as the number of the pixel circuits included in the internal pixel units; the connection structure between the devices in the pixel circuit of the internal pixel unit is the same as the connection structure between the devices in the pixel circuit of the boundary pixel unit. According to the invention, the quantization difference between the pixel circuit row adjacent to the boundary pixel array in the internal pixel array and other pixel circuit rows in the internal pixel array can be reduced.

Description

Technical Field

[0001] This application relates to the field of image sensor technology, and in particular to a pixel array and an image sensor. Background Technology

[0002] Image sensors are widely used in various electronic devices to capture and identify images of people or scenes, such as video surveillance systems, smartphones, digital cameras, medical devices, drones, AI, and facial recognition. In particular, the rapid development of CMOS (Complementary Metal-Oxide-Semiconductor) image sensor technology has led to higher demands on the output image quality of image sensors. An image sensor is a semiconductor-based sensor that generates electrical signals in response to light. As a crucial component of digital cameras, it converts incident light signals into electrical charges, then into voltage or current signals, and finally outputs the converted electrical signals. An image sensor contains a photosensitive pixel array, which collects light signal information from the image array and converts it into electrical signal data for use by the terminal.

[0003] Image sensor pixel arrays typically include internal pixel arrays and boundary pixel arrays. Pixels in the internal pixel array can be arranged in a shared structure (i.e., a compact pixel structure). This shared structure means that transistors in at least two pixels are reused. In this case, the structure of pixels in the internal pixel array usually differs from that in the boundary pixel array. This leads to significant differences in signal fluctuations between the boundary pixel array and the internal pixel array, resulting in substantial quantization differences between rows of pixels adjacent to the boundary pixel array and other rows of pixels in the internal pixel array. Therefore, reducing these quantization differences between rows of pixels adjacent to the boundary pixel array and other rows of pixels in the internal pixel array is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0004] The purpose of this application is to provide a pixel array and an image sensor to eliminate or reduce the quantization difference between pixel rows of adjacent boundary pixel arrays and other pixel rows in the inner pixel array.

[0005] To achieve the above objectives:

[0006] In a first aspect, embodiments of this application provide a pixel array, including an inner pixel array and a boundary pixel array, wherein the boundary pixel columns of the boundary pixel array are correspondingly connected to the inner pixel columns of the inner pixel array; the boundary pixel column includes boundary pixel units; the inner pixel column includes multiple rows of inner pixel units and multiple transistor multiplexing units, at least two inner pixel units are connected through transistor multiplexing units, and the inner pixel units adjacent to the boundary pixel units in the multiple rows of inner pixel units are connected to the corresponding boundary pixel units through transistor multiplexing units; wherein, the inner pixel unit includes at least two pixel circuits, the number of pixel circuits included in the boundary pixel unit is the same as the number of pixel circuits included in the inner pixel unit, and the connection structure between the devices in the pixel circuits of the inner pixel unit is the same as the connection structure between the devices in the pixel circuits of the boundary pixel unit.

[0007] Secondly, embodiments of this application provide an image sensor, including a pixel array as described above.

[0008] By employing the above-described technical solution of this application, a pixel array is laid out in a shared structure. The number of pixel circuits included in the internal pixel units of the internal pixel array is the same as the number of pixel circuits included in the boundary pixel units of the boundary pixel array, and the structure of the pixel circuits in the internal pixel array is the same as the structure of the pixel circuits in the boundary pixel array. This eliminates or reduces the difference between signal fluctuations in the boundary pixel array and signal fluctuations in the internal pixel array. Consequently, during quantization operations, this eliminates or improves the difference between the quantization environment of the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and the quantization environment of other pixel circuit rows in the internal pixel array, thereby eliminating or reducing the quantization differences between the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and other pixel circuit rows in the internal pixel array. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0010] Figure 1 This is a schematic diagram of the frame structure of the pixel array provided in the embodiments of this application.

[0011] Figure 2 This is a schematic diagram of the latch control logic circuit provided in the second embodiment of this application.

[0012] Figure 3 This is a schematic diagram of the control circuit of the transmission transistor in the second embodiment of this application.

[0013] Figure 4 This is another schematic diagram of the latch control logic circuit exemplified in the second embodiment of this application.

[0014] Figure 5 This is a schematic diagram of the structure of pixel arrays in some implementations of examples in this application.

[0015] Figure 6 This is a schematic diagram of the pixel array provided in Example 1 of this application.

[0016] Figure 7 This is a schematic diagram of the structure of the pixel unit provided in Example 2 of this application.

[0017] Figure 8 This is a first flowchart illustrating the control method for the image sensor provided in this application.

[0018] Figure 9 This is a second flowchart illustrating the control method for the image sensor provided in this application.

[0019] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0020] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0021] It should be understood that although the terms first, second, third, etc., may be used in this document to describe various information, elements, units, or modules, these information, elements, units, or modules should not be limited to these terms. These terms are only used to distinguish information, elements, units, or modules of the same type from one another.

[0022] It should be noted that step designations such as S11 and S12 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S12 first and then S11, etc., but these should all be within the protection scope of this application.

[0023] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0024] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0025] First Embodiment

[0026] See Figure 1 This embodiment provides a pixel array including an inner pixel array and a boundary pixel array, wherein the boundary pixel columns of the boundary pixel array are connected to the inner pixel columns of the inner pixel array.

[0027] The boundary pixel column includes boundary pixel units.

[0028] The internal pixel column includes multiple rows of internal pixel units and multiple transistor multiplexing units.

[0029] At least two internal pixel units are connected by transistor multiplexing units.

[0030] Among them, the internal pixel units adjacent to the boundary pixel units in the multi-row internal pixel units are connected to the corresponding boundary pixel units through transistor multiplexing units.

[0031] The inner pixel unit includes at least two pixel circuits, the number of pixel circuits in the boundary pixel unit is the same as the number of pixel circuits in the inner pixel unit, and the connection structure between the devices in the pixel circuits of the inner pixel unit is the same as the connection structure between the devices in the pixel circuits of the boundary pixel unit.

[0032] In one embodiment, the pixel array comprises m pixel rows (or pixel unit rows) and n pixel columns, where m and n are both natural numbers greater than 0. The number of boundary pixel columns in the boundary pixel array and the number of internal pixel columns in the inner pixel array can both be n. Each pixel column in the pixel array consists of corresponding connected boundary pixel columns and inner pixel columns. The m pixel rows of the pixel array consist of a boundary pixel rows from the boundary pixel array and b inner pixel rows from the inner pixel array, where a and b are both natural numbers greater than 0, and a + b = m.

[0033] In this arrangement, at least two pixel units are connected by transistor multiplexing units, such as at least two rows of internal pixel units being connected by transistor multiplexing units, and internal pixel units adjacent to boundary pixel units in multiple rows of internal pixel units being connected to adjacent boundary pixel units by transistor multiplexing units. Therefore, the pixel array adopts a shared structure layout, which can reduce the occupied area of ​​the pixel array and / or increase the area occupancy of optoelectronic devices in the pixel array to improve the photoelectric conversion efficiency of the pixel panel.

[0034] Understandably, pixel circuits in a pixel array can characterize various circuit structures that control the transfer of charge generated by optoelectronic devices.

[0035] In one embodiment, at least two rows of internal pixel units connected through the same transistor reset unit can share the functions that the transistors in the aforementioned transistor reset unit can perform.

[0036] In one embodiment, internal pixel units and boundary pixel units connected through the same transistor reset unit can share the functions that the transistors in the aforementioned transistor reset unit can perform.

[0037] In one embodiment, the transistor multiplexing unit connects two adjacent rows of internal pixel units.

[0038] In one embodiment, the transistor multiplexing unit may include one or more of the multiple transistors in a single pixel channel that perform different functions, such as a reset transistor, a row selection transistor, etc.

[0039] In one embodiment, at least two pixel circuits within an internal pixel unit can be independent of each other, but can be connected through other transistor multiplexing units. For example, when at least two internal pixel units are connected through a reset transistor to share the functions that the reset transistor can perform, at least two pixel circuits within an internal pixel unit can be connected through a row selection transistor to share the functions that the row selection transistor can perform.

[0040] Through the above technical solution of this embodiment, the pixel array is laid out in a shared structure manner. The number of pixel circuits included in the internal pixel unit of the internal pixel array is the same as the number of pixel circuits included in the boundary pixel unit of the boundary pixel array, and the structure of the pixel circuits in the internal pixel array is the same as the structure of the pixel circuits in the boundary pixel array. This eliminates or reduces the difference between the signal fluctuations existing in the boundary pixel array and the signal fluctuations existing in the internal pixel array. In turn, during quantization operations, it eliminates or improves the difference between the quantization environment of the pixel circuit row adjacent to the boundary pixel array in the internal pixel array and the quantization environment of other pixel circuit rows in the internal pixel array, thereby eliminating or reducing the quantization difference between the pixel circuit row adjacent to the boundary pixel array in the internal pixel array and other pixel circuit rows in the internal pixel array.

[0041] Understandably, quantization can characterize the process of converting the analog signals read from each pixel circuit row of a pixel array configured in an image sensor into digital signals. In this process, the light intensity (usually expressed as charge) of the pixel formed by each pixel circuit is converted into a digital value that represents the brightness or color information of that pixel.

[0042] Understandably, eliminating or reducing the quantization difference between the pixel circuit rows of adjacent boundary pixel arrays in the inner pixel array and other pixel circuit rows in the inner pixel array can reduce the noise level, thereby enabling the image sensor configured with the aforementioned pixel array to improve the signal-to-noise ratio of the image and / or improve the consistency of the image when sensing the image.

[0043] Second Embodiment

[0044] See Figure 1 This embodiment provides a pixel array including an inner pixel array and a boundary pixel array, wherein the boundary pixel columns of the boundary pixel array are connected to the inner pixel columns of the inner pixel array.

[0045] The boundary pixel column includes boundary pixel units.

[0046] The internal pixel column includes multiple rows of internal pixel units and multiple transistor multiplexing units.

[0047] In this configuration, at least two rows of internal pixel units are connected by transistor multiplexing units.

[0048] Among them, the internal pixel units adjacent to the boundary pixel units in the multi-row internal pixel units are connected to the adjacent boundary pixel units through transistor multiplexing units.

[0049] The inner pixel unit includes at least two pixel circuits, the number of pixel circuits in the boundary pixel unit is the same as the number of pixel circuits in the inner pixel unit, and the connection structure between the devices in the pixel circuits of the inner pixel unit is the same as the connection structure between the devices in the pixel circuits of the boundary pixel unit.

[0050] Specifically, when performing quantization operations on pixel circuit rows adjacent to the boundary pixel array in the inner pixel array, at least a portion of all control signals received by the boundary pixel units in the boundary pixel array are the same as the control signals received by the inner pixel units in the inner pixel array. In other words, the influence of readout timing between different pixel unit rows is similar or consistent in both the inner and boundary pixel arrays.

[0051] In one embodiment, when the pixel circuit in the boundary pixel unit is composed of optoelectronic devices and multiple transistors that implement different control functions, all control signals received by the boundary pixel unit include signals that are externally connected to the control terminals of at least some of the transistors, and / or signals that are externally connected to the path terminals of at least some of the transistors.

[0052] Through the above technical solution of this embodiment, in the pixel array layout using a shared structure, the number of pixel circuits included in the internal pixel units of the internal pixel array is the same as the number of pixel circuits included in the boundary pixel units of the boundary pixel array, and the structure of the pixel circuits in the internal pixel array is the same as the structure of the pixel circuits in the boundary pixel array. Furthermore, when performing quantization operations on the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array, part or all of the control signals received by the boundary pixel units in the boundary pixel array are the same as the control signals received by the internal pixel units in the internal pixel array. Thus, the technical solution of this embodiment ensures both the structural integrity between the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array. This similarity ensures the similarity of control signals received by the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array when performing quantization operations on pixel circuit rows adjacent to the boundary pixel array in the internal pixel array. This further eliminates or reduces the differences in signal fluctuations between the boundary pixel array and the internal pixel array. Consequently, during quantization operations, it can more effectively eliminate or improve the differences in the quantization environment between the pixel circuit rows adjacent to the boundary pixel array and other pixel circuit rows in the internal pixel array, thus more effectively eliminating or reducing the quantization differences between the pixel circuit rows adjacent to the boundary pixel array and other pixel circuit rows in the internal pixel array.

[0053] In one embodiment, each pixel unit row of the pixel array is connected to a control circuit. The control circuit can be the logic control circuit in an existing image sensor. For example, it can generate a corresponding control signal based on a preset address (or address signal) to control the transistor in the corresponding pixel circuit.

[0054] The control signals received by the internal pixel units in the internal pixel array include the signals output by the control circuit based on the first pixel address (or the first pixel address signal).

[0055] Among them, the control signals received by the boundary pixel units in the boundary pixel array include the signals output by the control circuit based on the second pixel address (or second pixel address signal);

[0056] In other words, the control signal generated based on the first pixel address controls the internal pixel units, and the control signal generated based on the second pixel address controls the boundary pixel units. The first and second pixel addresses can be configured according to the address configuration methods in existing image sensors; that is, the pixel units corresponding to the internal pixel array and the boundary pixel array are each configured with their own addresses, so that different control signals are formed based on different address correspondences. In one implementation, the second pixel address can be obtained by the encoding circuit performing a translation process on all the first pixel addresses. Optionally, this translation method can obtain a regularly ordered address obtained by combining the boundary pixel array and the internal pixel array into a complete array.

[0057] At this time, the control circuit corresponding to the inner pixel unit row can have the same structure as the control circuit corresponding to the boundary pixel unit row, and each can perform control according to the preset image sensor timing sequence.

[0058] In one embodiment, the control circuit may include control circuit units (or sub-control circuits). The inner pixel units in the inner pixel array may correspond to the control circuit units of the control circuit in a manner consistent with the control circuit units of the control circuit. In one embodiment, the boundary pixel units in the boundary pixel array may correspond to the control circuit units of the control circuit in a manner consistent with the control circuit units of the control circuit.

[0059] In one embodiment, each pixel unit row of the pixel array may include at least two pixel circuit rows. Optionally, the control circuit connected to each pixel unit row of the pixel array may output at least two control signals to control at least two pixel circuit rows respectively.

[0060] Optionally, the control circuit connected to each pixel unit row of the pixel array may include at least two sub-control circuits, and the at least two sub-control circuits are respectively connected to at least two pixel circuit rows. Each sub-control circuit can output a control signal to control the corresponding connected pixel circuit row.

[0061] The above-described method of shifting pixel addresses using encoding circuits can accurately and effectively enable the control circuits corresponding to the internal pixel array and the control circuits corresponding to the boundary pixel array to use the same signal control logic to control the pixel circuit rows. This ensures that during quantization operations, each pixel circuit row of the pixel array can read the charge data normally according to the quantization requirements.

[0062] For example, the pixel array includes an inner pixel array and two boundary pixel arrays. The boundary pixel columns of the two boundary pixel arrays are respectively connected to the first and last inner pixel columns of the inner pixel array. The inner pixel unit of the inner pixel column includes two pixel circuits, and the two pixel circuits in the inner pixel unit correspond to two pixel circuit rows in the inner pixel array. Each boundary pixel column includes one boundary pixel unit, and the boundary pixel unit also includes two pixel circuits, and the two pixel circuits in the boundary pixel unit correspond to two pixel circuit rows in the boundary pixel array. When the inner pixel array includes 1001 pixel circuit rows, the encoding circuit can be pre-configured to correspond to all the first pixel addresses of the inner pixel array as rows 0 to 1000, and the two boundary pixel arrays each include two pixel circuit rows. In this way, the encoding circuit can perform a translation process on all the first pixel addresses to obtain the pixel addresses of rows 0 to 1004. The pixel addresses corresponding to rows 0 to 1 and the pixel addresses corresponding to rows 1003 to 1004 are the second pixel addresses corresponding to the first and last boundary pixel arrays of the inner pixel array, respectively. Thus, the encoding circuit can realize the control circuit connected to each pixel unit row of the pixel array.

[0063] Thus, the above example ensures that when quantizing a pixel circuit row adjacent to the boundary pixel array in the inner pixel array, all control signals received by the boundary pixel units in the boundary pixel array are identical to those received by the inner pixel units in the inner pixel array. This achieves both structural consistency between the inner pixel units in the inner pixel array and the boundary pixel units in the boundary pixel array, and consistency of control signals received by the inner pixel units in the inner pixel array and the boundary pixel units in the boundary pixel array when quantizing a pixel circuit row adjacent to the boundary pixel array in the inner pixel array. This further eliminates the difference between signal fluctuations in the boundary pixel array and those in the inner pixel array, and thus more effectively eliminates the difference between the quantization environment of the pixel circuit row adjacent to the boundary pixel array and other pixel circuit rows in the inner pixel array during quantization operations.

[0064] In one embodiment, each pixel circuit row of the inner pixel array is connected to a first control circuit, and each pixel circuit row of the boundary pixel array is connected to a second control circuit; the pixel circuits in both the inner pixel unit and the boundary pixel unit include a transmission transistor connected to an optoelectronic device.

[0065] In one embodiment, the first control circuit and the second control circuit can have the same structure.

[0066] The transmission transistors of the pixel circuits in the internal pixel units are controlled by the control signals output by their corresponding first control circuits.

[0067] The transmission transistors of the pixel circuits in the boundary pixel units are controlled by the control signals output by their corresponding second control circuits.

[0068] In a further example, the transfer transistor of the pixel circuit in the boundary pixel unit is controlled to be constantly on by the control signal output by its corresponding second control circuit. The photoelectric devices in the boundary pixel array do not necessarily need to output signals. To prevent them from affecting the signals of the internal pixel units in the internal pixel array, the transfer transistor can be kept constantly on to perform charge clearing operations, thereby improving image quality.

[0069] Thus, the other embodiments described above eliminate the need for the encoding circuit to perform pixel address shifting. By outputting control signals to the transmission transistors of the pixel circuits in the boundary pixel units through the second control circuit to control their constant operation, each pixel circuit row of the boundary pixel array can read out charge data normally. Therefore, during quantization operations, each pixel circuit row of the pixel array can read out charge data normally according to the quantization requirements. Therefore, the above implementation can achieve the following: while ensuring the structural consistency between the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array, some of the control signals received by the boundary pixel units in the boundary pixel array are the same as those received by the internal pixel units in the internal pixel array (i.e., the signal control logic of the boundary pixel units in the boundary pixel array is not completely the same as that of the internal pixel units in the internal pixel array). It can also reduce the difference between the signal fluctuations in the boundary pixel array and the signal fluctuations in the internal pixel array. In turn, during quantization operations, it can reduce the difference between the quantization environment of the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and the quantization environment of other pixel circuit rows in the internal pixel array, thereby reducing the quantization difference between the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and other pixel circuit rows in the internal pixel array.

[0070] In other embodiments, both the first control circuit and the second control circuit are controlled by the logic signals output by the control logic circuit through a latch.

[0071] Among them, see Figure 2 The latch control logic circuit includes latch U1, AND gate U2 and OR gate U3.

[0072] The first input terminal of AND gate U2 is connected to the first address signal interface of latch U1, and the second input terminal of AND gate U2 receives the first output control signal lat_en.

[0073] The first input terminal of OR gate U3 is connected to the output terminal of AND gate U2, the second input terminal of OR gate U3 receives the second output control signal lat_always_on_en, and the output terminal of OR gate U3 is connected to the second control circuit.

[0074] The first address signal interface of latch U1 is used to output the address signal during the idle phase.

[0075] Understandably, the output of OR gate U3 is connected to the second control circuit to output the control signal lat_addb_o to the second control circuit during the idle phase, so as to control the conduction of the transfer transistor of the pixel circuit in the boundary pixel unit.

[0076] In other embodiments, the output of AND gate U2 can be connected to a first control circuit to output a control signal lat_addb to the first control circuit during idle periods to control the transmission transistors of the pixel circuits in the internal pixel units.

[0077] In other embodiments, the device connection structures of the first control circuit and the second control circuit can be the same, with the only difference being the input control signals.

[0078] In one implementation, each first control circuit corresponds to a first latch control logic circuit, and each second control circuit corresponds to a second latch control logic circuit. The first latch control logic circuit and the second latch control logic circuit have the same structure, both including a latch U1, an AND gate U2 and an OR gate U3, which are connected to the corresponding control circuits from different interfaces as described above.

[0079] In other implementations, the structures of the first latch control logic circuit and the second latch control logic circuit are different. The first latch control logic circuit includes a latch U1 and an AND gate U2, with the output of the AND gate U2 connected to the corresponding first control circuit. The second latch control logic circuit includes a latch U1, an AND gate U2, and an OR gate U3, with the output of the OR gate U3 connected to the corresponding second control circuit.

[0080] For example, see Figure 3 This embodiment illustrates a control circuit (such as a second control circuit) for the transmission transistor TX in a pixel circuit. Driven by signals output by a latch control logic circuit at different stages, it outputs control signals to the transmission transistor TX at different stages to control the transmission transistor to be turned on or off at each stage. Figure 3 As shown, the state of the transfer transistor during the exposure phase can be controlled based on the first column of transistors, such as turning off the transfer transistor based on address control. Similarly, the state of the transfer transistor during the reset phase can be controlled based on the second column of transistors, such as turning on the transfer transistor based on address control. Similarly, the state of the transfer transistor during the idle phase can be controlled based on the third column of transistors, such as turning on the transfer transistor based on address control to perform a charge clearing operation. Here, sp_add is the exposure row address signal, sp_addb is the inverted signal of the exposure row address, sp_tx is the exposure row transfer signal, sp_txb is the inverted signal of the exposure row transfer signal, rp_add is the sampling row address signal, rp_addb is the inverted signal of the sampling row address signal, rp_tx is the sampling row transfer signal, rp_txb is the inverted signal of the sampling row transfer signal, lat_add is the latch row address signal, lat_addb is the inverted signal of the latch row address signal, lat_add_o is the latch normally open address signal, and lat_addb_o is the inverted signal of the latch normally open address signal. It should be noted that in the image sensor, the aforementioned address signal can be used to select the corresponding pixel based on a preset timing sequence. In addition, the latch U1 can use multiple MOS transistors and inverters to output address signals based on the input related signals according to a preset timing sequence to realize the operation of the image sensor.

[0081] In this embodiment, the latch control logic circuit is also shown in the example. Figure 4 See Table 1 for the truth table of the latch control logic circuit:

[0082] Table 1:

[0083]

[0084] The first output control signal lat_en indicates whether to enable the latch function. If enabled, the transfer transistor of the corresponding pixel circuit will be turned on during the idle phase to perform a charge clearing operation. The second output control signal lat_always_on_en indicates whether to enable the normally open latch function of the boundary pixel array. If enabled, the transfer transistor of the corresponding boundary pixel circuit will be turned on to perform a charge clearing operation regardless of whether the latch function is enabled, thus realizing the normally open transfer transistor.

[0085] As shown in the first row of Table 1, the normally open latch of the boundary pixel array is always active. At this time, the second input of the OR gate U3 receives the second output control signal lat_always_on_en as a high level 1. Regardless of the output signal of the AND gate U2, the corresponding output signal of the OR gate U3 is always 1, that is, lat_addb_o is 1. The normally open latch function is always active. During the idle stage, the boundary pixel transmission transistor is normally open to clear the charge. Optionally, when the normally open latch function is started, the input of the latch U1 can be any address, or of course, no address can be given. In this case, the normally open latch function can be implemented without configuring an address for the boundary pixel array.

[0086] As shown in the second row of Table 1, the normally open latch function of the boundary pixel array is always inactive. At this time: the second input terminal of AND gate U2 receives the first output control signal lat_en as low level 0, and the second input terminal of OR gate U3 receives the second output control signal lat_always_on_en as low level 0. Correspondingly, the output terminal of AND gate U2 outputs a low level 0. Then, the second output control signal lat_always_on_en received by the second input terminal of OR gate U3 determines the output signal of OR gate U3, that is, lat_addb_o is determined by lat_always_on_en. Therefore, the output signal of OR gate U3 is 0, that is, lat_addb_o is 0. The normally open latch function is always inactive, and the normally open charge clearing function of the boundary pixel unit transmission transistor is not turned on during the idle stage.

[0087] As shown in the third row of Table 1, the internal pixel latch function is active, while the boundary pixel normally open latch function is inactive. The boundary pixel transfer transistor operates according to the timing of the internal pixel transfer transistor. At this time: the second input of AND gate U2 receives the first output control signal lat_en as a high level (1), and the second input of OR gate U3 receives the second output control signal lat_always_on_en as a low level (0). The output voltage of the output of AND gate U2 is determined by the output state of the first address signal interface of latch U1. The output of AND gate U2 determines the signal corresponding to the output of OR gate U3. That is, lat_addb_o is determined by the output of AND gate U2. In other words, lat_addb_o is determined by the output state of the first address signal interface of latch U1. The transfer transistor is turned on and the charge is cleared according to the normal timing setting.

[0088] Based on the same inventive concept as the foregoing embodiments, the pixel arrays described in the foregoing embodiments will be illustrated by specific examples below:

[0089] See Figure 5In some implementations, the pixel array includes an inner pixel array and a boundary pixel array, wherein the boundary pixel column of the boundary pixel array is connected to the corresponding inner pixel column of the inner pixel array.

[0090] The internal pixel column comprises multiple rows of internal pixel units and multiple transistor multiplexing units. At least two rows of internal pixel units are connected via transistor multiplexing units. Internal pixel units adjacent to boundary pixel units in the multiple rows of internal pixel units are connected to the adjacent boundary pixel units via transistor multiplexing units. Each internal pixel unit includes two pixel circuits.

[0091] The boundary pixel column includes a virtual pixel circuit, which comprises an optoelectronic device pd, a virtual transmission transistor, a virtual floating diffusion node fd_dmy, a virtual source follower transistor sf, and a virtual double-conversion gain transistor dcg_dmy; the control terminal of the virtual transmission transistor receives control signals (such as...). Figure 5 In the above, the two terminals of the virtual transmission transistor (hi) are connected to the optoelectronic device pd and the virtual floating diffusion node fd_dmy, respectively; the control terminal of the virtual source follower transistor sf is connected to the virtual floating diffusion node fd_dmy, and the two terminals of the virtual source follower transistor sf receive power signals to remove electrons from the virtual floating diffusion node fd_dmy; the control terminal of the virtual double conversion gain transistor dcg_dmy receives control signals, and the first terminal of the virtual double conversion gain transistor dcg_dmy is connected to the first terminal of the double conversion gain transistor dcg_dmy of the first pixel circuit in the adjacent internal pixel unit through the terminal of the transistor multiplexing unit; the second terminal of the virtual double conversion gain transistor dcg_dmy is connected to the virtual floating diffusion node fd_dmy.

[0092] When quantizing the first pixel circuit row in the inner pixel unit adjacent to the pixel boundary (i.e., quantizing the first pixel single-path row of the inner pixel array), the virtual double-conversion gain transistor dcg_dmy needs to be turned off. At other times, the virtual double-conversion gain transistor dcg_dmy needs to be turned on. However, the pixel array structure in the above implementation has the following problems: (1) Only one boundary pixel circuit row where the virtual pixel circuit is located is used as the boundary pixel array, and the connection relationship of the boundary pixel circuit row is different from that of the pixel circuit in the inner pixel array, making it difficult to simulate the influence of adjacent rows in the pixel array on the quantization row; (2) Only the virtual double-conversion gain transistor dcg_dmy in the virtual pixel circuit is controlled, which cannot simulate the fluctuation of different signals in the pixel circuit in the inner pixel array. Based on the above problems, the pixel array provided by the above implementation cannot eliminate or reduce the quantization difference between the pixel circuit row adjacent to the boundary pixel array in the inner pixel array and other pixel circuit rows in the inner pixel array.

[0093] Example 1:

[0094] This example provides a pixel array based on the same inventive concept as the foregoing embodiments, to address the problems existing in the provided pixel array.

[0095] See Figure 6 The pixel array provided in this example includes an inner pixel array and a boundary pixel array, with the boundary pixel columns of the boundary pixel array corresponding to the inner pixel columns of the inner pixel array.

[0096] The boundary pixel column includes boundary pixel units.

[0097] The internal pixel column includes multiple rows of internal pixel units and multiple transistor multiplexing units.

[0098] In this configuration, at least two rows of internal pixel units are connected by transistor multiplexing units.

[0099] Among them, the internal pixel units adjacent to the boundary pixel units in the multi-row internal pixel units are connected to the adjacent boundary pixel units through transistor multiplexing units.

[0100] The internal pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor rs. The first pixel circuit and the second pixel circuit belong to two pixel circuit rows in the internal pixel array, respectively.

[0101] The first pixel circuit includes a first optoelectronic device pd, a first transmission transistor tx, a first floating diffusion node fd, a first source follower transistor sf, and a first dual conversion gain transistor dcg;

[0102] The control terminal of the first transmission transistor tx receives the control signal, and the two channels of the first transmission transistor tx are respectively connected to the first optoelectronic device pd and the first floating diffusion node fd;

[0103] The control terminal of the first source follower transistor sf is connected to the first floating diffusion node fd. The second path terminal of the first source follower transistor sf is connected to the data line through the two path terminals of the row select transistor rs. The first path terminal of the first source follower transistor sf receives the power signal. The control terminal of the row select transistor rs receives the control signal.

[0104] The control terminal of the first dual-conversion-gain transistor dcg receives a control signal, the first path terminal of the first dual-conversion-gain transistor dcg receives a first input signal, and the second path terminal of the first dual-conversion-gain transistor dcg is connected to the first floating diffusion node fd.

[0105] The second pixel circuit includes a second optoelectronic device pd, a second transmission transistor tx, a second floating diffusion node fd, a second source follower transistor sf, and a second dual conversion gain transistor dcg;

[0106] The control terminal of the second transmission transistor tx receives the control signal, and the two channels of the second transmission transistor tx are respectively connected to the second optoelectronic device pd and the second floating diffusion node fd.

[0107] The control terminal of the second source follower transistor sf is connected to the second floating diffusion node fd. The second path terminal of the second source follower transistor sf is connected to the data line through the two path terminals of the row select transistor rs. The first path terminal of the second source follower transistor sf receives the power signal.

[0108] The control terminal of the second dual-conversion gain transistor dcg receives the control signal, the second path terminal of the second dual-conversion gain transistor dcg is connected to the second floating diffusion node fd, and the first path terminal of the second dual-conversion gain transistor dcg receives the second input signal.

[0109] In one embodiment, the transistor multiplexing unit includes a reset transistor rst, and the internal pixel units connected through the transistor multiplexing unit include forward internal pixel units and backward internal pixel units.

[0110] The first path terminal of the second dual-conversion gain transistor dcg in the second pixel circuit of the forward internal pixel unit is connected to the first path terminal of the first dual-conversion gain transistor dcg in the first pixel circuit of the backward internal pixel unit.

[0111] In this configuration, the control terminal of the reset transistor rst receives a control signal, the first path terminal of the reset transistor rst receives a reference voltage, and the second path terminal of the reset transistor rst is connected to the first path terminal of the second dual-conversion gain transistor dcg in the second pixel circuit of the preceding internal pixel unit and the first path terminal of the first dual-conversion gain transistor dcg in the first pixel circuit of the following internal pixel unit. Thus, the reset transistor rst can reset the second floating diffusion node fd in the second pixel circuit of the preceding internal pixel unit and the first floating diffusion node fd in the first pixel circuit of the following internal pixel unit.

[0112] Thus, the two internal pixel units share a reset transistor rst, and the first pixel circuit and the second pixel circuit in the same internal pixel unit share a row selection transistor rs.

[0113] The number of pixel circuits included in the boundary pixel unit is the same as the number of pixel circuits included in the inner pixel unit, and the connection structure between the devices in the pixel circuit of the inner pixel unit is the same as the connection structure between the devices in the pixel circuit of the boundary pixel unit.

[0114] Specifically, the boundary pixel unit includes a first pixel circuit and a second pixel circuit. The first path terminal of the first dual-conversion gain transistor (dcg) of the first pixel circuit in the adjacent internal pixel unit is connected to the first path terminal of the second dual-conversion gain transistor (dcg) of the second pixel circuit in the adjacent boundary pixel unit. The control terminal of the reset transistor RST receives a control signal, the first path terminal of the reset transistor RST receives a reference voltage, and the second path terminal of the reset transistor RST is connected to the first path terminal of the first dual-conversion gain transistor (dcg) of the first pixel circuit in the adjacent internal pixel unit and the first path terminal of the second dual-conversion gain transistor (dcg) of the second pixel circuit in the adjacent boundary pixel unit. Thus, the reset transistor RST can reset the second floating diffusion node (fd) in the second pixel circuit of the boundary pixel unit and the first floating diffusion node (fd) in the first pixel circuit of the adjacent internal pixel unit.

[0115] In one embodiment, the boundary pixel unit may further include a row selection transistor rs, and the first pixel channel and the second pixel circuit in the boundary pixel unit may share the row selection transistor rs in the same manner as the inner pixel unit.

[0116] In one embodiment, the boundary pixel unit may further include a gain control circuit, wherein the first pixel circuit and the second pixel circuit of the boundary pixel unit belong to two adjacent pixel circuit rows in the boundary pixel array, respectively; the gain control circuit is used to output a first input signal, including a reset transistor rst and a third double-conversion gain transistor dcg.

[0117] In this circuit, the control terminal of the third dual-conversion gain transistor (DCG) receives a control signal, the first path terminal of the third DCG receives a power supply signal, and the second path terminal of the third DCG is connected to the first path terminal of the first dual-conversion gain transistor (DCG) in the first pixel circuit. Similarly, the control terminal of the reset transistor (RST) receives a control signal, the first path terminal of the reset transistor (RST) receives a reference voltage, and the second path terminal of the reset transistor (RST) is connected to both the first and third DCG paths.

[0118] Specifically, when performing quantization operations on the pixel circuit rows adjacent to the boundary pixel array in the inner pixel array, some or all of the control signals received by the boundary pixel units in the boundary pixel array are the same as the control signals received by the inner pixel units in the inner pixel array.

[0119] In one embodiment, the optoelectronic device pd can be a photodiode.

[0120] Thus, the pixel array provided in Example 1 can ensure both the structural consistency between the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array, and the similarity of the control signals received by the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array when performing quantization operations on the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array. This can eliminate or reduce the difference between the signal fluctuations existing in the boundary pixel array and the signal fluctuations existing in the internal pixel array. Consequently, during quantization operations, it can eliminate or reduce the difference between the quantization environment of the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and the quantization environment of other pixel circuit rows in the internal pixel array, thereby effectively eliminating or reducing the quantization differences between the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and other pixel circuit rows in the internal pixel array.

[0121] Example 2:

[0122] This Example 2 provides a pixel array based on the same inventive concept as the foregoing embodiments, addressing the problems existing in the pixel array provided above. The difference between the technical solution provided in this Example 2 and the technical solution in Example 2 above is that the first pixel circuit and the second pixel circuit in the internal pixel unit are respectively connected to the row selection transistor rs (i.e., the first pixel circuit and the second pixel circuit in the internal pixel unit do not share the same row selection transistor rs), and / or, the first pixel circuit and the second pixel circuit in the boundary pixel unit are respectively connected to the row selection transistor rs (i.e., the first pixel circuit and the second pixel circuit in the boundary pixel unit do not share the same row selection transistor rs).

[0123] Specifically, the two rows of pixel circuits in the internal pixel unit include a first pixel circuit and a second pixel circuit, and the first pixel circuit and the second pixel circuit belong to two rows of pixel circuits in the internal pixel array, respectively.

[0124] The first pixel circuit includes a first optoelectronic device pd, a first transmission transistor tx, a first floating diffusion node fd, a first source follower transistor sf, a first row selection transistor rs, and a first dual conversion gain transistor dcg;

[0125] The control terminal of the first transmission transistor tx receives the control signal, and the two channels of the first transmission transistor tx are respectively connected to the first optoelectronic device pd and the first floating diffusion node fd;

[0126] The control terminal of the first source follower transistor sf is connected to the first floating diffusion node fd. The second path terminal of the first source follower transistor sf is connected to the data line through the two path terminals of the first row select transistor rs. The first path terminal of the first source follower transistor sf receives the power signal. The control terminal of the first row select transistor rs receives the control signal.

[0127] The control terminal of the first dual-conversion-gain transistor dcg receives a control signal, the first path terminal of the first dual-conversion-gain transistor dcg receives a first input signal, and the second path terminal of the first dual-conversion-gain transistor dcg is connected to the first floating diffusion node fd.

[0128] The second pixel circuit includes a second optoelectronic device pd, a second transmission transistor tx, a second floating diffusion node fd, a second source follower transistor sf, a second row selection transistor rs, and a second dual conversion gain transistor dcg;

[0129] The control terminal of the second transmission transistor tx receives the control signal, and the two channels of the second transmission transistor tx are respectively connected to the second optoelectronic device pd and the second floating diffusion node fd.

[0130] The control terminal of the second source follower transistor sf is connected to the second floating diffusion node fd. The second path terminal of the second source follower transistor sf is connected to the data line through the two path terminals of the second row select transistor rs. The first path terminal of the second source follower transistor sf receives the power signal. The control terminal of the second row select transistor rs receives the control signal.

[0131] The control terminal of the second dual-conversion gain transistor dcg receives the control signal, the second path terminal of the second dual-conversion gain transistor dcg is connected to the second floating diffusion node fd, and the first path terminal of the second dual-conversion gain transistor dcg receives the second input signal.

[0132] The number of pixel circuits included in the boundary pixel unit is the same as the number of pixel circuits included in the inner pixel unit, and the connection structure between the devices in the pixel circuit of the inner pixel unit is the same as the connection structure between the devices in the pixel circuit of the boundary pixel unit.

[0133] Thus, the pixel array provided in Example 2 can ensure both the structural consistency between the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array, and the similarity of the control signals received by the internal pixel units in the internal pixel array and the boundary pixel units in the boundary pixel array when performing quantization operations on the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array. This can eliminate or reduce the difference between the signal fluctuations in the boundary pixel array and the signal fluctuations in the internal pixel array, and thus eliminate or reduce the difference between the quantization environment of the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and the quantization environment of other pixel circuit rows in the internal pixel array during quantization operations, thereby effectively eliminating or reducing the quantization differences between the pixel circuit rows adjacent to the boundary pixel array in the internal pixel array and other pixel circuit rows in the internal pixel array.

[0134] Based on the same inventive concept as the foregoing embodiments, this application also provides an image sensor, which includes the pixel array described in any of the above embodiments.

[0135] Based on the same inventive concept as the foregoing embodiments, see [link to previous document]. Figure 8 This application also provides a control method for an image sensor, applied to the above-mentioned image sensor, comprising the following steps:

[0136] S11: Input control signals to the pixel circuit rows in the boundary pixel array to perform charge readout operation;

[0137] S12: Input control signal to the first pixel circuit row adjacent to the boundary pixel array in the internal pixel array and perform quantization operation.

[0138] In one embodiment, see Figure 9 After the step of inputting control signals to the first pixel circuit row adjacent to the boundary pixel array in the inner pixel array and performing quantization operation, the following step may be included: S13: inputting control signals to other pixel circuit rows other than the first pixel circuit row in the inner pixel array and performing quantization operation.

[0139] In one embodiment, step S11, which involves inputting control signals to the pixel circuit rows in the boundary pixel array to perform charge readout operations, may include inputting control signals to the transmission transistors included in the pixel circuits of the pixel circuit rows in the boundary pixel array to control their normal operation.

[0140] The image sensor and its control method provided in this application embodiment can effectively eliminate or reduce the quantization difference between the first pixel circuit row of the internal pixel array adjacent to the boundary pixel array and other pixel circuit rows in the internal pixel array when performing quantization operation on the first pixel circuit row of the internal pixel array of the image sensor that is adjacent to the boundary pixel array.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0143] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel array, comprising: It includes an inner pixel array and a boundary pixel array, wherein the boundary pixel columns of the boundary pixel array are connected to the corresponding inner pixel columns of the inner pixel array; The boundary pixel column includes boundary pixel units; The internal pixel column includes multiple rows of internal pixel units and multiple transistor multiplexing units. At least two internal pixel units are connected through the transistor multiplexing units. The internal pixel units that are adjacent to the boundary pixel units in the multiple rows of internal pixel units are connected to the corresponding boundary pixel units through the transistor multiplexing units. The internal pixel unit includes at least two pixel circuits, the number of pixel circuits included in the boundary pixel unit is the same as the number of pixel circuits included in the internal pixel unit, and the connection structure between the devices in the pixel circuits of the internal pixel unit is the same as the connection structure between the devices in the pixel circuits of the boundary pixel unit.

2. The pixel array of claim 1, wherein, When performing a quantization operation on a pixel circuit row in the inner pixel array that is adjacent to the boundary pixel array, at least a portion of all control signals received by the boundary pixel unit in the boundary pixel array are the same as the control signals received by the corresponding inner pixel unit in the inner pixel array.

3. The pixel array of claim 1, wherein, Each row of pixel units in the pixel array is connected to a control circuit, wherein: The control signals received by the internal pixel units in the internal pixel array include signals output by the control circuit corresponding to the first pixel address; The control signals received by the boundary pixel units in the boundary pixel array include signals output by the control circuit corresponding to the second pixel address.

4. The pixel array according to claim 3, characterized in that, The internal pixel units in the internal pixel array correspond to the control circuit units of the control circuit in a row-to-row manner, and the boundary pixel units in the boundary pixel array correspond to the control circuit units of the control circuit in a row-to-row manner; and / or The second pixel address is obtained by the encoding circuit after shifting all the first pixel addresses; and / or, The control circuit corresponding to the inner pixel unit row has the same structure as the control circuit corresponding to the boundary pixel unit row.

5. The pixel array according to claim 1, characterized in that, Each pixel circuit row of the inner pixel array is connected to a first control circuit, and each pixel circuit row of the boundary pixel array is connected to a second control circuit. The pixel circuits in both the internal pixel unit and the boundary pixel unit include transmission transistors that connect to optoelectronic devices. The transmission transistor of the pixel circuit in the internal pixel unit is controlled by the control signal output by the corresponding first control circuit; The transmission transistor of the pixel circuit in the boundary pixel unit is controlled by the control signal output by the corresponding second control circuit.

6. The pixel array according to claim 5, characterized in that, The transmission transistor of the pixel circuit in the boundary pixel unit is controlled to be normally on by the control signal output by the corresponding second control circuit; and / or, The first control circuit and the second control circuit have the same structure.

7. The pixel array according to claim 5, characterized in that, The second control circuit is controlled by the logic signal output by the second latch control logic circuit. The second latch control logic circuit includes a latch, an AND gate, and an OR gate, wherein: The first input terminal of the AND gate is connected to the first address signal interface of the latch, and the second input terminal of the AND gate receives a first output control signal. The first address signal interface of the latch is used to output an address signal during the idle phase. The first input terminal of the OR gate is connected to the output terminal of the AND gate, and the second input terminal of the OR gate receives a second output control signal. The output terminal of the OR gate is connected to the second control circuit. And / or, the first control circuit is controlled by the logic signal output by the first latch control logic circuit, the first latch control logic circuit including a latch, an AND gate, and an OR gate, or, the first latch control logic circuit including a latch and an AND gate, wherein: The first input terminal of the AND gate is connected to the first address signal interface of the latch, the second input terminal of the AND gate receives the first output control signal, and the output terminal of the AND gate is connected to the first control circuit. The first address signal interface of the latch is used to output an address signal during the idle phase.

8. The pixel array of claim 1, wherein, The transistor multiplexing unit connects two adjacent rows of the internal pixel units; and / or, the internal pixel unit includes two pixel circuits.

9. The pixel array of any of claims 1 to 8, wherein, The internal pixel unit includes a first pixel circuit, a second pixel circuit, and a row selection transistor. The first pixel circuit and the second pixel circuit belong to two pixel circuit rows in the internal pixel array, respectively. The first pixel circuit includes a first optoelectronic device, a first transmission transistor, a first floating diffusion node, a first source follower transistor, and a first dual-conversion gain transistor; The control terminal of the first transmission transistor receives a control signal, and the two terminals of the first transmission transistor are respectively connected to the first optoelectronic device and the first floating diffusion node; The control terminal of the first source follower transistor is connected to the first floating diffusion node, the second path terminal of the first source follower transistor is connected to the data line through the two path terminals of the row select transistor, the first path terminal of the first source follower transistor receives a power signal, and the control terminal of the row select transistor receives a control signal. The control terminal of the first dual-conversion-gain transistor receives a control signal, the first path terminal of the first dual-conversion-gain transistor receives a first input signal, and the second path terminal of the first dual-conversion-gain transistor is connected to the first floating diffusion node. The second pixel circuit includes a second optoelectronic device, a second transmission transistor, a second floating diffusion node, a second source follower transistor, and a second dual-conversion gain transistor; The control terminal of the second transmission transistor receives a control signal, and the two terminals of the second transmission transistor are respectively connected to the second optoelectronic device and the second floating diffusion node; The control terminal of the second source follower transistor is connected to the second floating diffusion node, the second path terminal of the second source follower transistor is connected to the data line through the two path terminals of the row select transistor, and the first path terminal of the second source follower transistor receives the power signal. The control terminal of the second dual-conversion-gain transistor receives a control signal, the second path terminal of the second dual-conversion-gain transistor is connected to the second floating diffusion node, and the first path terminal of the second dual-conversion-gain transistor receives a second input signal. Alternatively, the two rows of pixel circuits in the internal pixel unit include a first pixel circuit and a second pixel circuit, wherein the first pixel circuit and the second pixel circuit belong to two pixel circuit rows in the internal pixel array, respectively: The first pixel circuit includes a first optoelectronic device, a first transmission transistor, a first floating diffusion node, a first source follower transistor, a first row selection transistor, and a first dual conversion gain transistor; The control terminal of the first transmission transistor receives a control signal, and the two terminals of the first transmission transistor are respectively connected to the first optoelectronic device and the first floating diffusion node; The control terminal of the first source follower transistor is connected to the first floating diffusion node, the second path terminal of the first source follower transistor is connected to the data line through the two path terminals of the first row select transistor, the first path terminal of the first source follower transistor receives the power signal, and the control terminal of the first row select transistor receives the control signal. The control terminal of the first dual-conversion-gain transistor receives a control signal, the first path terminal of the first dual-conversion-gain transistor receives a first input signal, and the second path terminal of the first dual-conversion-gain transistor is connected to the first floating diffusion node. The second pixel circuit includes a second optoelectronic device, a second transmission transistor, a second floating diffusion node, a second source follower transistor, a second row selection transistor, and a second dual-conversion gain transistor; The control terminal of the second transmission transistor receives a control signal, and the two terminals of the second transmission transistor are respectively connected to the second optoelectronic device and the second floating diffusion node; The control terminal of the second source follower transistor is connected to the second floating diffusion node, the second path terminal of the second source follower transistor is connected to the data line through the two path terminals of the second row select transistor, the first path terminal of the second source follower transistor receives the power signal, and the control terminal of the second row select transistor receives the control signal. The control terminal of the second dual-conversion gain transistor receives a control signal, the second path terminal of the second dual-conversion gain transistor is connected to the second floating diffusion node, and the first path terminal of the second dual-conversion gain transistor receives a second input signal.

10. The pixel array of claim 9, wherein, The transistor multiplexing unit includes a reset transistor, and the internal pixel units connected through the transistor multiplexing unit include the preceding internal pixel units and the following internal pixel units. The first path terminal of the second dual-conversion gain transistor of the second pixel circuit in the preceding internal pixel unit is connected to the first path terminal of the first dual-conversion gain transistor of the first pixel circuit in the following internal pixel unit. The control terminal of the reset transistor receives a control signal, the first path terminal of the reset transistor receives a reference voltage, and the second path terminal of the reset transistor is connected to the first path terminal of the second dual-conversion gain transistor of the second pixel circuit in the preceding internal pixel unit and the first path terminal of the first dual-conversion gain transistor of the first pixel circuit in the following internal pixel unit.

11. The pixel array of claim 9, wherein, The boundary pixel unit includes the first pixel circuit and the second pixel circuit; The first path terminal of the first dual-conversion gain transistor of the first pixel circuit in the inner pixel unit adjacent to the boundary pixel unit is connected to the first path terminal of the second dual-conversion gain transistor of the second pixel circuit in the adjacent boundary pixel unit. The control terminal of the reset transistor receives a control signal, the first path terminal of the reset transistor receives a reference voltage, and the second path terminal of the reset transistor is connected to the first path terminal of the first dual-conversion gain transistor of the first pixel circuit in the inner pixel unit adjacent to the boundary pixel unit and the first path terminal of the second dual-conversion gain transistor of the second pixel circuit in the adjacent boundary pixel unit.

12. The pixel array of claim 11, wherein, The boundary pixel unit further includes a row selection transistor and / or gain control circuit, wherein the first pixel circuit and the second pixel circuit of the boundary pixel unit belong to two adjacent pixel circuit rows in the boundary pixel array, respectively. The gain control circuit is used to output the first input signal, and includes a reset transistor and a third double-conversion gain transistor; The control terminal of the third dual-conversion gain transistor receives a control signal, the first path terminal of the third dual-conversion gain transistor receives a power supply signal, and the second path terminal of the third dual-conversion gain transistor is connected to the first path terminal of the first dual-conversion gain transistor in the first pixel circuit. The control terminal of the reset transistor receives a control signal, the first path terminal of the reset transistor receives a reference voltage, and the second path terminal of the reset transistor is connected to the first path terminal of the first dual-conversion gain transistor and the first path terminal of the third dual-conversion gain transistor.

13. An image sensor, comprising: Includes the pixel array as described in any one of claims 1 to 12.

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