Semiconductor packaging structure

Abstract

The utility model provides a semiconductor packaging structure. The semiconductor package structure includes a substrate for the semiconductor package structure. The substrate for the semiconductor packaging structure is provided with a first surface used for arranging a chip, at least partial area of the first surface is a groove arrangement area, and the groove arrangement area is provided with a plurality of grooves. According to the substrate for the semiconductor packaging structure, the plurality of grooves are formed in the groove setting area, so that when the chip is arranged, the bonding force between the substrate and the bonding glue for bonding the chip can be increased through the grooves, and the bonding force between the chip and the substrate for the semiconductor packaging structure is improved; and the destructive shearing force resistance of the semiconductor packaging product is increased, so that the service life and the reliability of the semiconductor packaging product are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Technology

[0002] In traditional semiconductor packaging processes, die bonding is a crucial front-end manufacturing process. Die bonding involves first applying an adhesive material to a substrate with a metal frame, then placing the chip on the adhesive, and finally curing the adhesive through high-temperature baking. After the adhesive cures, the semiconductor packaged product is typically subjected to destructive shear force testing using specialized equipment. A higher shear force required to push the chip during the test indicates a higher lifespan and reliability for the semiconductor packaged product. Improving the resistance of semiconductor packaged products to destructive shear forces to enhance their lifespan and reliability is a significant research direction within the industry. Summary of the Invention

[0003] This application provides a substrate for a semiconductor packaging structure. The substrate has a first surface for mounting a chip, and at least a portion of the first surface is a recessed area with multiple recesses.

[0004] In some embodiments, the plurality of grooves are arranged in parallel at intervals; or...

[0005] The plurality of grooves includes at least two portions of grooves spaced apart in at least two different directions, and at least some of the grooves spaced apart in different directions intersect.

[0006] In some embodiments, the groove opening has two opposing side edges in the groove width direction, and at least a portion of the inner wall of the groove is a straight wall surface in the direction of extension from one side edge to the other side edge.

[0007] In some embodiments, the groove has a V-shaped cross-section.

[0008] In some embodiments, the groove has a first groove wall and a second groove wall facing the opening, and the included angle between the first groove wall and the second groove wall is 88°-92°.

[0009] In some embodiments, the groove opening has two opposing side edges in the groove width direction, and the inner wall surface of the groove is at least partially formed as a curved segment in the extending direction from one side edge to the other side edge.

[0010] In some embodiments, the groove has a U-shaped cross-section.

[0011] In some embodiments, the spacing between two adjacent grooves is 0.45mm-55mm;

[0012] The depth of the groove is 0.002mm-0.025mm;

[0013] The width of the groove is 0.02mm-0.05mm.

[0014] In some embodiments, the substrate for the semiconductor packaging structure is a lead frame island, and the groove is a wire drawing groove.

[0015] This application also provides a semiconductor packaging structure, which includes a chip, an adhesive, and a substrate for the semiconductor packaging structure as described above; wherein the adhesive is disposed on a first surface of the substrate for the semiconductor packaging structure, the orthographic projection of the chip on the first surface falls within the orthographic projection range of the adhesive on the first surface, and the orthographic projection of the adhesive on the first surface at least partially overlaps with the groove setting area.

[0016] In some embodiments, the orthographic projection of the adhesive on the first surface falls into the groove setting area.

[0017] The main technical effects achieved by the embodiments of this application are:

[0018] The semiconductor packaging structure substrate and semiconductor packaging structure provided in this application embodiment use at least a portion of the first surface of the semiconductor packaging structure substrate used for setting the chip as a groove setting area, and provide multiple grooves in the groove setting area. When setting the chip, the grooves can increase the adhesion between the chip and the adhesive used to bond the chip, thereby improving the bonding force between the chip and the semiconductor packaging structure substrate, increasing the semiconductor packaging product's resistance to destructive shear forces, and thus improving the lifespan and reliability of the semiconductor packaging product. Attached Figure Description

[0019] Figure 1 This is a top view of a substrate for a semiconductor packaging structure provided in an exemplary embodiment of this application;

[0020] Figure 2 It is along Figure 1 The sectional view obtained by section line AA shown;

[0021] Figure 3 It is along Figure 1 The sectional view obtained by section line BB shown;

[0022] Figure 4 This is a partial cross-sectional view of a cross-section including a groove, provided in an exemplary embodiment of this application;

[0023] Figure 5 This is a top view of a semiconductor packaging structure provided in an exemplary embodiment of this application;

[0024] Figure 6 It is along Figure 5 The sectional view obtained by section line CC shown.

[0025] Figure 7 yes Figure 6 An enlarged view of point E is shown below;

[0026] Figure 8 It is along Figure 5 The sectional view obtained by section line DD shown. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0028] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0029] The following is in conjunction with the appendix Figures 1 to 8 This application provides a detailed description of some embodiments of the semiconductor packaging structure substrate and the semiconductor packaging structure. Unless otherwise specified, features in the following embodiments can be combined with each other.

[0030] Please refer to Figure 1 This application provides a substrate 2 for a semiconductor packaging structure. The substrate 2 for the semiconductor packaging structure has a first surface S1 for mounting a chip 1, and at least a portion of the first surface S1 is a recessed area 21, wherein the recessed area 21 is provided with a plurality of recesses 20.

[0031] The semiconductor packaging structure substrate 2 uses at least a portion of the first surface S1 of the semiconductor packaging structure substrate 2, which is used to set the chip 1, as a groove setting area 21. The groove setting area 21 is provided with multiple grooves 20. When setting the chip 1, the grooves 20 can increase the adhesion between the chip 1 and the adhesive used to bond the chip 1, thereby improving the bonding force between the chip 1 and the semiconductor packaging structure substrate 2, increasing the semiconductor packaging product's resistance to destructive shear forces, and thus improving the lifespan and reliability of the semiconductor packaging product.

[0032] like Figure 1 As shown, in some embodiments, the groove setting area 21 may be a large portion of the area including the central region of the first surface S1. Alternatively, it could be other areas, or even the entire area of ​​the first surface S1. The specific location of the groove setting area 21 can be selected according to specific needs.

[0033] In some embodiments, a plurality of the grooves 20 are arranged in parallel at intervals.

[0034] like Figure 1 As shown, multiple grooves 20 are arranged parallel to each other in a first direction L. Each groove 20 extends along a second direction W. The first direction L and the second direction W can be the length direction and the width direction of the substrate 2 for the semiconductor packaging structure, respectively. In some other embodiments, the multiple grooves 20 can also be arranged at intervals in other directions, and can be uniformly parallel or not completely parallel.

[0035] In other embodiments, the plurality of grooves 20 include at least two portions of grooves 20 spaced apart along at least two different directions, and at least some of the grooves 20 spaced apart along different directions intersect. For example, the plurality of grooves 20 include two portions of grooves 20 spaced apart along a first direction L and a second direction W, wherein the grooves spaced apart along the first direction L may intersect with the grooves spaced apart along the second direction W.

[0036] In some embodiments, the substrate 2 of the semiconductor packaging structure is a lead frame island.

[0037] In some embodiments, the groove 20 described in this application is a wire drawing groove formed by a wire drawing process. This type of groove is simple to prepare and is beneficial for cost control.

[0038] In related technologies, several methods are commonly used to improve the resistance of semiconductor packaged products to destructive shear forces. The first method is to add adhesive to the bonding agent. The second method is to roughen the substrate surface by chemical etching. The third method is to create a large groove on the substrate, partially embedding the chip 1 within the groove. However, adding adhesive to the bonding agent reduces the flowability of the adhesive material, easily causing nozzle clogging and insufficient adhesive coverage. For surface roughening by chemical etching, this technique is generally used to prevent delamination after molding, but this process is difficult, time-consuming, and costly. Furthermore, designing a partial groove on the substrate to partially embed the chip 1 is difficult to manufacture and is not conducive to testing the chip 1's shear force after die mounting. In this embodiment, the groove is formed using a wire drawing process. Compared to adding adhesive, chemical etching, or creating a large groove, this method can improve the resistance of the semiconductor packaged product to destructive shear forces while achieving better cost control.

[0039] Of course, in some other embodiments, the groove 20 can also be formed in other ways, such as chemical etching.

[0040] Combination Figure 4 As shown, in some embodiments, the groove 20 has two opposing side edges 2010, 2020 in the width direction L1 of the groove 20. In the extending direction from one side edge to the other side edge, at least a portion of the inner wall of the groove 20 is a straight wall surface. For example, in the extending direction from one side edge 2010 to the other side edge 2020, at least a portion of the inner wall of the groove 20 is a straight wall surface.

[0041] The width direction L1 can be consistent with the spacing direction L of the groove 20.

[0042] In some embodiments, the cross-section of the groove 20 is V-shaped.

[0043] The inventors discovered through research that when the cross-section of the groove is V-shaped, both a small and a large included angle of the groove sidewalls will affect the bonding force between the adhesive and the groove.

[0044] The inventors have discovered through research that, in some embodiments, the groove 20 has a first groove wall 201 and a second groove wall 202 facing the opening 2001, and the included angle between the first groove wall 201 and the second groove wall 202 is 88°-92°, which can better increase the bonding force between the adhesive and the groove, so as to better increase the resistance of the semiconductor packaged product to destructive shear force.

[0045] In some embodiments, the width l1 of the first groove wall 201 and the width l2 of the second groove wall 202 are equal.

[0046] In other embodiments, the groove 20 has two opposing side edges 2010, 2020 in the width direction of the groove 20, and at least a portion of the inner wall surface of the groove 20 is formed as a curved segment in the extending direction from one side edge to the other side edge. For example, at least a portion of the inner wall surface of the groove 20 is formed as a curved segment in the extending direction from one side edge 2010 to the other side edge 2020.

[0047] In some embodiments, the groove 20 has a U-shaped cross-section, which is easier to manufacture than a groove with a V-shaped cross-section.

[0048] In some embodiments, the distance between two adjacent grooves 20 is 0.45mm-55mm.

[0049] Through research, the inventors discovered that excessively deep grooves can negatively impact the structural strength of the substrate used in semiconductor packaging and the precision of die mounting, while shallow grooves do not effectively increase the bonding area between the adhesive and the groove. Therefore, further research revealed that a groove depth of 0.002mm-0.025mm effectively increases the bonding area between the adhesive and the groove while maintaining the structural strength of the substrate 2 used in semiconductor packaging and the precision of die mounting.

[0050] In some embodiments, the width w1 of the groove 20 is 0.02mm-0.05mm.

[0051] This application also provides a semiconductor packaging structure 100, which includes a chip 1, an adhesive 3, and a substrate 2 for the semiconductor packaging structure as described above. The adhesive is disposed on a first surface S1 of the substrate 2, the orthographic projection of the chip 1 on the first surface S1 falls within the orthographic projection range of the adhesive on the first surface S1, and the orthographic projection of the adhesive 3 on the first surface S1 at least partially overlaps with the recessed area 21.

[0052] In some embodiments, the adhesive 3 may be silver paste, solder paste, or other metal bonding materials.

[0053] In some embodiments, the orthographic projection of the adhesive 3 on the first surface S1 falls into the groove setting area 21.

[0054] like Figure 5As shown, the orthographic projection of the adhesive 3 on the first surface S1 falls into the groove setting area 21, so as to ensure that the area where the adhesive 3 is set is provided with grooves 20, so as to maximize the adhesion between the chip 1, the adhesive 3 and the substrate 2 for semiconductor packaging structure.

[0055] It should be noted that the semiconductor package structure 100 can be a TO-type device using a TO (Transistor Outline) package.

[0056] The inventors conducted destructive shear force tests on the semiconductor packaging structure and concluded that, for similar semiconductor structures, the semiconductor packaging structure formed using the substrate 2 for semiconductor packaging has significantly greater resistance to destructive shear force than the semiconductor packaging structure on the substrate without grooves.

[0057] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0058] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure includes a chip, adhesive, and a substrate for the semiconductor packaging structure. The substrate for the semiconductor packaging structure has a first surface for mounting a chip, and at least a portion of the first surface is a recess mounting area, wherein the recess mounting area is provided with multiple recesses; The adhesive is disposed on the first surface of the substrate for the semiconductor packaging structure, the orthographic projection of the chip on the first surface falls within the orthographic projection range of the adhesive on the first surface, and the orthographic projection of the adhesive on the first surface at least partially overlaps with the groove setting area. The orthographic projection of the adhesive on the first surface falls into the groove area.

2. The semiconductor packaging structure as described in claim 1, characterized in that, Multiple grooves are arranged in parallel at intervals; or, The plurality of grooves includes at least two portions of grooves spaced apart in at least two different directions, and at least some of the grooves spaced apart in different directions intersect.

3. The semiconductor packaging structure as described in claim 1, characterized in that, The groove opening has two opposing side edges in the groove width direction, and at least a portion of the inner wall of the groove is a straight wall surface in the direction of extension from one side edge to the other side edge.

4. The semiconductor packaging structure as described in claim 3, characterized in that, The groove has a V-shaped cross-section.

5. The semiconductor packaging structure as described in claim 1, characterized in that, The groove has a first groove wall and a second groove wall facing the opening, and the included angle between the first groove wall and the second groove wall is 88°-92°.

6. The semiconductor packaging structure as described in claim 1, characterized in that, The groove opening has two opposing side edges in the groove width direction, and at least a portion of the inner wall surface of the groove is a curved section extending from one side edge to the other side edge.

7. The semiconductor packaging structure as described in claim 6, characterized in that, The groove has a U-shaped cross-section.

8. The semiconductor packaging structure as described in claim 1, characterized in that, The distance between two adjacent grooves is 0.45mm-55mm; The depth of the groove is 0.002mm-0.025mm; The width of the groove is 0.02mm-0.05mm.

9. The semiconductor packaging structure as described in claim 1, characterized in that, The substrate for the semiconductor packaging structure is a lead frame island, and the groove is a wire drawing groove.

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