Core board of elevator control system

Abstract

The utility model relates to a core board of an elevator control system. The core board is arranged on the elevator control board and comprises a PCB, a processor arranged on the PCB, a plurality of types of communication interfaces electrically connected with the processor, a power supply device, a storage device, an Ethernet PHY chip, a 4G communication device and a plurality of types of communication interfaces electrically connected with the 4G communication device. The storage device comprises a nonvolatile memory and a random access memory, each of the nonvolatile memory and the random access memory is electrically connected with the processor, the 4G communication device is electrically connected with the processor and is provided with an LTE antenna port, and the communication interface is electrically connected with a peripheral device which is arranged on the elevator control panel and located outside the core board. And the Ethernet PHY chip is electrically connected with the processor. According to the utility model, the processor, the storage module, the 4G communication device and other core devices are packaged in the core board, and by directly using the core board, the hardware development efficiency and the development quality can be improved, and the development cost can be reduced.

Description

Technical Field

[0001] This utility model relates to the field of elevator technology, and in particular to the core board of elevator control system. Background Technology

[0002] In existing technologies, elevator control systems include one or more circuit boards (which can be called elevator control boards) equipped with processors. The same type of processor is often used in different types of elevator control boards. If the processor, peripheral devices, and some other important components are packaged into a core board, the development efficiency and quality of the elevator control board can be greatly increased, while reducing development costs.

[0003] The above description of the background technology is only for the purpose of facilitating a deeper understanding of the technical solution of this utility model (the technical means used, the technical problems solved, and the technical effects produced, etc.), and should not be regarded as an admission or in any form an implication that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide a core board for an elevator control system. This core board encapsulates core components such as a processor, storage device, and 4G communication device. By directly using this core board, hardware development efficiency and quality can be increased, while development costs can be reduced.

[0005] According to an embodiment of the present invention, a core board for an elevator control system is provided, which is disposed on an elevator control board and includes a PCB board and a processor disposed on the PCB board, a plurality of communication interfaces electrically connected to the processor, a power supply device, a storage device, an Ethernet PHY chip, a 4G communication device, and a plurality of communication interfaces electrically connected to the 4G communication device; the storage device includes a non-volatile memory and a random access memory, each of the non-volatile memory and the random access memory being electrically connected to the processor; the 4G communication device is electrically connected to the processor and is configured with an LTE antenna port; the Ethernet PHY chip is electrically connected to the processor; the plurality of communication interfaces electrically connected to the 4G communication device and the plurality of communication interfaces electrically connected to the processor are electrically connected to peripheral devices disposed on the elevator control board and located outside the core board; the power supply device is electrically connected to the processor, each of the plurality of communication interfaces electrically connected to the processor, the storage device, the Ethernet PHY chip, the 4G communication device, and each of the plurality of communication interfaces electrically connected to the 4G communication device.

[0006] The core board of the elevator control system may include decoupling capacitors C1 and C2 for the power pin of the processor. Decoupling capacitors C1 and C2 are located within 5mm of the power pin of the processor and are connected in parallel between the power pin and the ground pin of the processor. The capacitance value of decoupling capacitor C1 is 0.1μF and the capacitance value of decoupling capacitor C2 is 10μF.

[0007] The core board of the elevator control system may include decoupling capacitors C3 and C4 for the power supply pin of the 4G communication device. Decoupling capacitors C3 and C4 are connected in parallel between the power supply pin and the ground pin of the 4G communication device. The capacitance value of decoupling capacitor C3 is 0.1μF and the capacitance value of decoupling capacitor C4 is 4.7μF.

[0008] Multiple types of communication interfaces electrically connected to the processor may include RS485 interface, ADC interface, GPIO interface, I2C interface, I2S interface, SPI, UART interface, RMII, USB interface, CAN interface, and quadrature decoding interface.

[0009] The various types of communication interfaces electrically connected to the 4G communication device may include UART interface, SGMII interface, SDIO interface and USB interface, and these interfaces can also be electrically connected to SIM cards and SD cards located on the elevator control board and outside the core board.

[0010] Each of the non-volatile memory and random access memory can be electrically connected to the processor via a parallel bus interface and an SPI bus, and the 4G communication device can be connected to the processor via the SPI bus.

[0011] The processor can be an STM32 series MCU with an ARM Cortex-M4 core.

[0012] The core board of the elevator control system may further include a crystal oscillator circuit that is electrically connected to the processor and the Ethernet PHY chip.

[0013] A PCB board may include a ground plane and a power plane.

[0014] The core board of the elevator control system may further include indicator lights that are electrically connected to a 4G communication device.

[0015] This utility model adopts the above technical solution, which has the following beneficial effects: The core board of the elevator control system of this utility model encapsulates core components such as a processor, power supply, storage device, 4G communication device, and Ethernet PHY chip, enabling reliable execution of elevator control logic, stable IoT connection, and secure data storage, thus forming a compact and efficient core module of the elevator control system. Reusing the core board allows for rapid product iteration, increases the development efficiency and quality of the elevator control board, and reduces development costs. Attached Figure Description

[0016] The exemplary embodiments of this utility model will be described in more detail below with reference to the accompanying drawings. For clarity, the same components in different drawings are shown with the same reference numerals. It should be noted that the drawings are for illustrative purposes only and are not necessarily drawn to scale. In these drawings:

[0017] Figure 1 This is a schematic diagram of the core board of the elevator control system according to the embodiment of this utility model.

[0018] Figure 2 This is a circuit diagram of decoupling capacitors C1 and C2 for the power supply pin of a processor according to an exemplary embodiment of the present invention.

[0019] Figure 3 This is a circuit diagram of decoupling capacitors C3 and C4 for the power supply pin of a 4G communication device according to an exemplary embodiment of the present invention. Detailed Implementation

[0020] The following provides a detailed description of the implementation scheme of this utility model. This implementation scheme is carried out based on the technical solution of this utility model and provides detailed implementation methods and specific operation processes. However, the protection scope of this utility model is not limited to the following implementation scheme.

[0021] Figure 1 This is a structural schematic diagram of the core board of the elevator control system according to an embodiment of this utility model. (See diagram below.) Figure 1 As shown, the core board 10 according to the embodiment of the present invention includes a PCB board 11 and a processor 12, a power supply device 13, a storage device 14, a 4G communication device 15, an Ethernet physical layer (PHY) chip 16 disposed on the PCB board 11, as well as multiple types of communication interfaces 17 electrically connected to the processor 12 and multiple types of communication interfaces 18 electrically connected to the 4G communication device 15.

[0022] Preferably, the PCB board 11 may include a ground layer and a power layer to reduce electromagnetic interference. The processor 12, power supply 13, storage device 14, 4G communication device 15, Ethernet PHY chip 16, and communication interfaces 17 and 18 described above can be mounted on the same surface of the PCB board 11 using surface mount technology, specifically, the power layer surface.

[0023] Power supply unit 13 is electrically connected to each of the processor 12, storage device 14, 4G communication device 15, Ethernet PHY chip 16, and communication interfaces 17 and 18, respectively, and is configured to convert the input voltage into the voltage required by these components to supply power. For example, the 4G communication device 15 requires 3.8V. Power supply unit 13 can adapt to different voltage inputs and convert the external input voltage into the voltage required by each component of the core board 10 to ensure the reliability and stability of the power supply. Specifically, power supply unit 13 can be a DC / DC module or a low dropout regulator (LDO) module.

[0024] In an exemplary embodiment, the core board 10 may include decoupling capacitors C1 and C2 for the power pins of the processor 12, for filtering out high-frequency noise and providing instantaneous current to ensure the stability of high-frequency operation. Figure 2 This is a circuit diagram of decoupling capacitors C1 and C2 for the power supply pins of a processor according to an exemplary embodiment of the present invention. Figure 2 As shown, decoupling capacitors C1 and C2 are positioned close to the power supply pin of processor 12. Specifically, decoupling capacitors C1 and C2 can be placed within 5mm of the power supply pin VDD of processor 12. Decoupling capacitors C1 and C2 are connected in parallel between the processor's power supply pin VDD and the ground pin. Decoupling capacitors C1 and C2 can be ceramic capacitors, with C1 having a capacitance of 0.1μF and C2 having a capacitance of 10μF.

[0025] For decoupling purposes, the core board 10 may include decoupling capacitors C3 and C4 for the power supply pins of the 4G communication device 15. Figure 3 This is a circuit diagram of decoupling capacitors C3 and C4 for the power supply pin of a 4G communication device according to an exemplary embodiment of the present invention. Figure 3 As shown, decoupling capacitors C3 and C4 are connected in parallel between the +3.8V power supply pin and the ground pin of the 4G communication device 15. Decoupling capacitors C3 and C4 can be ceramic capacitors; the capacitance of decoupling capacitor C3 is 0.1μF, and the capacitance of decoupling capacitor C4 is 4.7μF.

[0026] Back Figure 1 The storage device 14 is electrically connected to the processor 12. Specifically, the storage device 14 and the processor 12 are electrically connected via a parallel bus interface and a Serial Peripheral Interface (SPI) bus. The storage device 14 is configured to store the elevator operation program and the data generated during program execution. The storage device 14 may include non-volatile memory and random access memory. The non-volatile memory may be data storage flash memory (NAND Flash), and the random access memory may be synchronous dynamic random access memory (SDRAM). The data storage flash memory (NAND Flash) stores the elevator operation program, and the SDRAM stores the data generated during program execution.

[0027] The 4G communication device 15 is electrically connected to the processor 12 (specifically, via the SPI bus). The 4G communication device 15 is used to implement the elevator Internet of Everything (IoE) functionality, one of the core functions of the elevator, and is equipped with a Long Term Evolution (LTE) antenna port to support network connectivity. Specifically, the 4G communication device 15 can be a Quectel EC20.

[0028] In a preferred embodiment, the core board 10 further includes an indicator light electrically connected to the 4G communication device 15, the indicator light being used to indicate the current network status.

[0029] Ethernet PHY chip 16 is electrically connected to processor 12. Ethernet PHY chip 16 is used to connect the Media Access Control (MAC) layer and the physical layer. In terms of connecting the physical layer, Ethernet PHY chip 16 is used to connect the elevator control system and devices with Ethernet interfaces (such as cameras) in the elevator system via network cables.

[0030] As described above, the processor 12 is electrically connected to each of the storage device 14, the 4G communication device 15, and the Ethernet PHY chip 16, thereby performing overall control over the storage device 14, the 4G communication device 15, and the Ethernet PHY chip 16. Specifically, the processor 12 can be a chip integrating a Cortex-M series core, such as an STM32 series microcontroller (MCU) with an ARM Cortex-M4 core.

[0031] In a preferred embodiment, the core board 10 may include a crystal oscillator circuit electrically connected to the processor 12 and the Ethernet PHY chip 16, the crystal oscillator circuit providing clock signals to the processor 12 and the Ethernet PHY chip 16.

[0032] In various embodiments of this utility model, a core board 10, which encapsulates a processor 12, a power supply 13, a storage device 14, a 4G communication device 15, and an Ethernet PHY chip 16, is installed on the elevator control board instead of a separate processor. The core board 10 enables reliable execution of elevator control logic, stable IoT connectivity, and secure data storage, forming a compact and efficient core module of the elevator control system. Reusing the core board 10 allows for rapid product iteration, increases the development efficiency and quality of the elevator control board, and reduces development costs.

[0033] On the other hand, since the Bluetooth module and WIFI module are used for elevator debugging and are peripheral functions of the elevator control system, the Bluetooth module and WIFI module are set on the elevator control board but are located outside the core board 10, not inside the core board 10.

[0034] To enable the core board 10 to electrically connect with peripheral devices (such as Bluetooth modules and WIFI modules) on the elevator control board and to meet the connection requirements of different circuit control boards, the core board 10 includes multiple types of communication interfaces 17 electrically connected to the processor 12. The communication interfaces 17 are electrically connected to peripheral devices located on the elevator control board and outside the core board 10, thereby enabling the processor 12 to establish connections with these peripheral devices.

[0035] Specifically, the communication interface 17 includes an RS485 interface, an Analog-to-Digital Converter (ADC) interface, a General Purpose Input Output (GPIO) interface, an Inter-Integrated Circuit (I2C) interface, an Inter-IC Sound (I2S) interface, SPI, a Universal Asynchronous Receiver / Transmitter (UART) interface, a Reduced Media Independent Interface (RMII), a Universal Serial Bus (USB) interface, a Controller Area Network (CAN) interface, and an orthogonal decoding interface.

[0036] In addition, the core board 10 includes multiple types of communication interfaces 18 electrically connected to the 4G communication device 15. These communication interfaces 18 include a UART interface, a Serial Gigabit Media Independent Interface (SGMII), a Secure Digital Input Output (SDIO) interface, and a USB interface. The communication interfaces 18 are electrically connected to a Subscriber Identity Module (SIM) card and a Secure Digital (SD) card located on the elevator control board and external to the core board 10, thereby establishing a connection between the SIM card, SD card, and processor 12.

[0037] Specifically, communication interfaces 17 and 18 can be brought out in the form of stamp holes.

[0038] As an example, the core board 10 can be a square with a length and width of 55mm. The core board 10 is very small and can be easily installed on the elevator control board.

[0039] According to the embodiment of this utility model, the core board 10 of the elevator control system encapsulates core components such as a processor 12, a power supply 13, a storage device 14, a 4G communication device 15, and an Ethernet PHY chip 16. This enables reliable execution of elevator control logic, stable IoT connectivity, and secure data storage, forming a compact and efficient core module for the elevator control system. Reusing the core board 10 allows for rapid product iteration, increases the development efficiency and quality of the elevator control board, and reduces development costs.

[0040] The various embodiments of this utility model are not an exhaustive list of all possible combinations, but are intended to describe representative aspects of the utility model, and the contents described in the various embodiments can be applied independently or in two or more combinations.

[0041] The description of the exemplary embodiments presented above is merely illustrative of the technical solutions of this utility model and is not intended to be exhaustive or to limit the utility model to the precise forms described. Obviously, those skilled in the art can make many changes and variations based on the above teachings. The exemplary embodiments were chosen and described to explain the specific principles of this utility model and its practical applications, thereby enabling others skilled in the art to understand, implement, and utilize the various exemplary embodiments of this utility model and their various alternatives and modifications. The scope of protection of this utility model is intended to be defined by the appended claims and their equivalents.

Claims

1. A core board for an elevator control system, characterized in that, It is installed on the elevator control board and includes a PCB board, a processor installed on the PCB board, multiple types of communication interfaces electrically connected to the processor, a power supply device, a storage device, an Ethernet PHY chip, a 4G communication device, and multiple types of communication interfaces electrically connected to the 4G communication device. The storage device includes non-volatile memory and random access memory, each of which is electrically connected to the processor. The 4G communication device is electrically connected to the processor and is equipped with an LTE antenna port; The Ethernet PHY chip is electrically connected to the processor; Multiple types of communication interfaces electrically connected to the 4G communication device and multiple types of communication interfaces electrically connected to the processor are electrically connected to peripheral devices mounted on the elevator control board and located outside the core board. The power supply is electrically connected to the processor, each of the various types of communication interfaces electrically connected to the processor, the storage device, the Ethernet PHY chip, the 4G communication device, and each of the various types of communication interfaces electrically connected to the 4G communication device.

2. The core board of the elevator control system according to claim 1, characterized in that, This includes decoupling capacitors C1 and C2 for the processor's power pin. Decoupling capacitors C1 and C2 are located within 5mm of the processor's power pin and are connected in parallel between the processor's power pin and ground pin. The capacitance of decoupling capacitor C1 is 0.1μF and the capacitance of decoupling capacitor C2 is 10μF.

3. The core board of the elevator control system according to claim 1, characterized in that, The device includes decoupling capacitors C3 and C4 for the power supply pin of the 4G communication device. Decoupling capacitors C3 and C4 are connected in parallel between the power supply pin and the ground pin of the 4G communication device. The capacitance of decoupling capacitor C3 is 0.1μF and the capacitance of decoupling capacitor C4 is 4.7μF.

4. The core board of the elevator control system according to claim 1, characterized in that, Multiple types of communication interfaces electrically connected to the processor include RS485, ADC, GPIO, I2C, I2S, SPI, UART, RMII, USB, CAN, and quadrature decoding interfaces.

5. The core board of the elevator control system according to claim 1, characterized in that, The multiple types of communication interfaces electrically connected to the 4G communication device include UART interface, SGMII interface, SDIO interface and USB interface, and these multiple types of communication interfaces electrically connected to the 4G communication device are also electrically connected to the SIM card and SD card located on the elevator control board and outside the core board.

6. The core board of the elevator control system according to claim 1, characterized in that, Each of the non-volatile memory and random access memory is electrically connected to the processor via a parallel bus interface and an SPI bus, and the 4G communication device is connected to the processor via an SPI bus.

7. The core board of the elevator control system according to claim 1, characterized in that, The processor is an STM32 series MCU with an ARM Cortex-M4 core.

8. The core board of the elevator control system according to claim 1, characterized in that, It further includes a crystal oscillator circuit that is electrically connected to the processor and the Ethernet PHY chip.

9. The core board of the elevator control system according to claim 1, characterized in that, A PCB board includes a ground plane and a power plane.

10. The core board of the elevator control system according to claim 1, characterized in that, It further includes indicator lights that are electrically connected to 4G communication devices.

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