Isolated thermal resistor temperature signal conditioning system

Abstract

The utility model belongs to the technical field of industrial automation measurement and control, and discloses an isolation type thermal resistance temperature signal conditioning system, which comprises a constant current source circuit; an amplification circuit; a VF conversion circuit; an FV conversion circuit; a low-pass filter circuit; and a linearization circuit. According to the utility model, the instrument amplifier with a high common-mode rejection ratio is adopted to suppress common-mode noise, the hardware filtering design is optimized, multi-stage low-pass filtering is adopted to eliminate power frequency harmonic waves, and a mirror image constant current source is adopted to enhance the stability; a reverse protection circuit is added in a double-TVS diode clamping mode, and a wide input voltage range power supply chip is properly selected. VF / FV conversion time sequence control is adopted, a scheme of dynamically adjusting cut-off frequency is adopted, filtering parameters are automatically switched according to a signal variable rate, and noise suppression and response speed are balanced.

Description

Technical Field

[0001] This invention relates to the field of industrial automation measurement and control technology, and in particular to an isolated resistance temperature detector (RTD) temperature signal conditioning system. Background Technology

[0002] Resistance temperature sensors (RTDs) leverage the excellent temperature sensitivity and chemical stability of platinum (Pt) material to demonstrate high accuracy and reliability in temperature measurement. Typical examples, Pt100 (100Ω resistance at 0°C) and Pt1000 (1000Ω resistance at 0°C), can operate stably over a wide temperature range of -200°C to +850°C, meeting the demands of extreme environments such as cryogenic experiments and high-temperature industrial furnace monitoring. The resistance-temperature (RT) relationship of platinum resistance thermometers is nearly linear. By correcting for nonlinear deviations using the Callendar-Van Dusen equation (the formula used to calculate the relationship between temperature and resistance), the measurement error can be controlled within ±0.1°C, with some high-precision models reaching ±0.03°C, and exhibiting outstanding long-term stability.

[0003] In industrial applications, Real-Time Devices (RTDs) are widely used in process control scenarios such as temperature monitoring of chemical reactors, thermal management of electric steam pipelines, and overheat protection of metallurgical motors. They are also core sensing elements in laboratory constant temperature baths, medical equipment, and new energy fields (such as lithium battery production and low-temperature monitoring of hydrogen energy storage tanks). To adapt to complex industrial environments, RTDs employ multi-wire interface designs: 2-wire systems are low-cost but have limited accuracy, suitable for short-distance scenarios; 3-wire systems, by compensating for conductor resistance (e.g., error can be reduced to ±0.1°C for 100-meter cables), have become the mainstream industrial solution; 4-wire systems, based on Kelvin connections, isolate the excitation and measurement paths, achieving ultra-high accuracy at the ±0.01°C level, and are mostly used for laboratory calibration. Furthermore, differential signal transmission and shielded twisted-pair cable design effectively suppress common-mode noise caused by motor start-up and shutdown, further ensuring anti-interference capabilities in industrial environments.

[0004] Existing technological shortcomings:

[0005] 1. Insufficient power frequency interference suppression:

[0006] Problem Description: 50 / 60Hz power frequency noise superimposed on the weak RTD signal causes the ADC output to fluctuate (e.g., ±0.5℃ fluctuation).

[0007] Root causes: (1) Insufficient common-mode rejection ratio (CMRR) of differential amplifier (<80dB), which cannot effectively eliminate common-mode noise. (2) Poor filter circuit design (e.g., the cutoff frequency of single-stage RC filter is too high) and not optimized for power frequency harmonics. (3) Grounding design defects (e.g., ground loop) or failure to use shielded cables, which introduce spatial electromagnetic interference.

[0008] 2. Lack of power supply protection against incorrect connections can easily damage equipment:

[0009] Problem: Reverse power connection or overvoltage (such as 24V being mistakenly connected to 48V) causes the front-end circuit to burn out, resulting in a high equipment failure rate.

[0010] Root causes: (1) To reduce costs, reverse protection diodes, TVS diodes, or resettable fuses (PTCs) are omitted. (2) Reliance is placed on the voltage withstand limit of linear regulator chips (such as LM7805), and redundant protection is not designed.

[0011] 3. Multi-stage filtering causes signal delay:

[0012] Problem: When the temperature changes abruptly, the system response time is too long (e.g., >200ms), which cannot meet the real-time control requirements.

[0013] Root causes: (1) Using multi-stage analog filtering (such as RC low-pass + op-amp buffer) superimposed with digital filtering (moving average), phase delay accumulates. (2) The filter cutoff frequency is too low (such as 10Hz), sacrificing bandwidth, and dynamic response and noise suppression are contradictory.

[0014] Overall, the shortcomings of existing technologies are:

[0015] (1) Insufficient suppression of power frequency interference. Specifically, 50 / 60Hz power frequency noise is superimposed on the weak RTD signal, causing the ADC output to jump (such as ±0.5℃ fluctuation).

[0016] (2) Lack of protection against incorrect power connection can easily damage equipment. Specifically, reverse connection or overvoltage (such as 24V being mistakenly connected to 48V) can cause the front-end circuit to burn out, resulting in a high equipment failure rate.

[0017] (3) Multi-stage filtering causes signal delay. Specifically, when the temperature changes abruptly, the system response time is too long (e.g., >200ms), which cannot meet the real-time control requirements.

[0018] Therefore, how to provide an isolated resistance temperature signal conditioning system is an urgent problem to be solved. Summary of the Invention

[0019] This invention provides an isolated resistance temperature detector (RTD) temperature signal conditioning system to solve the problems of insufficient power frequency interference suppression, lack of power supply misconnection protection that easily damages equipment, and signal delay caused by multi-stage filtering in the prior art.

[0020] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or to describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0021] According to an embodiment of the present invention, an isolated resistance temperature detector (RTD) temperature signal conditioning system is provided.

[0022] In one embodiment, an isolated resistance temperature detector (RTD) signal conditioning system includes:

[0023] The constant current source circuit is used to provide a constant current to the resistance temperature sensor and to provide a constant current source for the VF conversion circuit.

[0024] The amplifier circuit is used to proportionally amplify the voltage across the resistance temperature sensor and transmit it to the VF conversion circuit.

[0025] The VF conversion circuit is used to map analog voltage into a frequency signal through a closed-loop mechanism of integration, comparison, and reset.

[0026] The FV conversion circuit is used to map a frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage.

[0027] A low-pass filter circuit is used to improve the stability of the analog voltage output by the FV conversion circuit.

[0028] A linearization circuit is used to linearize the final output voltage by adjusting the resistance.

[0029] The constant current source circuit, amplifier circuit, VF conversion circuit, FV conversion circuit, low-pass filter circuit, and linearization circuit are connected in sequence.

[0030] In one embodiment, the constant current source circuit includes: diode D3, transistor Q17, resistor R36, resistor R67, diode D10, transistor Q26, and resistor R37; wherein, one end of resistor R37 is connected to the first end of transistor Q26, the second end of transistor Q26 is connected to the second end of transistor Q17, the third end of transistor Q17 is connected to the cathode of diode D3, the first end of transistor Q17 is connected to one end of resistor R36, the third end of transistor Q26 is connected to the cathode of diode D10, and resistor R67 is also disposed on one side of diode D10.

[0031] In one embodiment, the amplifier circuit includes: resistors R38, R39, and R40, amplifier U4A, resistors R36, R68, and R66, and amplifier U4B; wherein, the first terminal of amplifier U4A is sequentially connected to one end of resistor R39 and one end of resistor R40, the other end of resistor R39 is connected to one end of resistor R38, the other end of resistor R38 is sequentially connected to the third terminal of amplifier U4A and one end of resistor R69, the other end of resistor R69 is sequentially connected to the first terminal of amplifier U4B and one end of resistor R68, the other end of resistor R68 is connected to one end of resistor R66, and the other end of resistor R66 is connected to the third terminal of amplifier U4B.

[0032] In one embodiment, the amplifier circuit further includes a dual TVS diode protection circuit, which includes a capacitor C23 and a diode Q22, wherein the first terminal of the diode C23 is connected in parallel with the second terminal of the diode Q22.

[0033] In one embodiment, the VF conversion circuit includes: switching transistor Q13, switching transistor Q14, capacitor C12, amplifier U5A, resistor R30, resistor R29, resistor R26, capacitor C10, resistor R24, resistor R25, capacitor C14, resistor R35, resistor R41, chip U1, and capacitor C11; wherein, the second terminal of the switching transistor Q13 is sequentially connected to one terminal of the capacitor C12 and the second terminal of the amplifier U5A, the other terminal of the capacitor C12 is sequentially connected to the first terminal of the amplifier U5A, the second terminal of the amplifier Q14, one terminal of the capacitor C10, and one terminal of the resistor R24, and the other terminal of the capacitor C10 is sequentially connected to the other terminal of the resistor R24, the second terminal of the amplifier Q14, one terminal of the capacitor C10, and one terminal of the resistor R24, and the third terminal of the capacitor C10 is sequentially connected to the other terminal of the resistor R24, the fourth terminal of the amplifier Q14, the fifth terminal of the amplifier Q15, the sixth terminal of the amplifier Q15, the seventh terminal of the amplifier Q15, the elliptical ... Resistor R25 is connected to the first end of chip U1, and the C1 end of chip U1 is connected to capacitor C11; the second end of chip U1 is connected to one end of resistor R26, and the other end of resistor R26 is sequentially connected to one end of resistor R30, one end of resistor R29, and the first end of switch Q13; the other end of resistor R30 is connected to the third end of amplifier U5A; the third end of switch Q13 is connected to the third end of switch Q14; the first end of switch Q14 is sequentially connected to one end of capacitor C14, one end of resistor R35, and one end of resistor R41; the other end of resistor R35 is connected to the other end of capacitor C14.

[0034] In one embodiment, the FV conversion circuit includes: chip U2, resistor R17, capacitor C8, capacitor C9, diode Q4, resistor R15, resistor R54, resistor R22, resistor R58, resistor R21, resistor R20, transistor Q8, resistor R61, resistor R56, capacitor C21, amplifier U6A, and transistor Q11; wherein, terminal A2 of chip U2 is connected to one end of resistor R17, the other end of resistor R17 is sequentially connected to one end of capacitor C9 and terminals A1 and B2 of chip U2, terminal C1 of chip U2 is connected to one end of capacitor C8, and the other end of capacitor C8 is connected to the other end of capacitor C9; the first end of transistor Q4 is sequentially connected to... Resistors R21, R20, and R58 are connected. The second terminal of transistor Q8 is sequentially connected to the second terminal of amplifier U6A, one terminal of capacitor C21, one terminal of resistor R61, and one terminal of resistor R22. The other terminal of resistor R22 is connected to one terminal of resistor R54. The other terminal of resistor R54 is sequentially connected to resistor R15 and diode Q4. The other terminal of resistor R61 is connected to one terminal of resistor R56. The other terminal of resistor R56 is sequentially connected to the other terminal of capacitor C21, the second terminal of transistor Q11, and the first terminal of amplifier U6A. The third terminal of transistor Q11 is connected to the third terminal of transistor Q8.

[0035] In one embodiment, mapping a frequency signal back to an analog voltage via a chain of frequency, pulse width, and voltage includes:

[0036] An optocoupler is used to isolate the output signal of the VF conversion circuit. A pulse shaping circuit then shapes the optocoupler's output signal into a square wave signal with the same frequency and fixed width as the -F conversion circuit. When the input voltage is low, transistor Q8 is cut off, and the input signal of the proportional amplifier circuit U6A is the reference voltage. When the input voltage is high, transistor Q8 is turned on, and the reference voltage and constant current source simultaneously act on the proportional amplifier circuit U6A. Based on Kirchhoff's theorem, the theoretical value of the output voltage is calculated. Using the relationship between the frequency of the input voltage and the resistance of the RTD temperature sensor, the linear relationship between the output voltage of the FV circuit and the RTD resistance is obtained.

[0037] In one embodiment, the low-pass filter circuit includes: capacitor C6, resistors R5, R7, R55, R11, capacitor C5, amplifier U1B, resistor R9, capacitor C4, and resistor R14; wherein, the third terminal of amplifier U1B is sequentially connected to one end of capacitor C4 and one end of resistor R9, and the other end of resistor R9 is connected to one end of capacitor C6; the second terminal of amplifier U1B is sequentially connected to one end of capacitor C5 and the third terminal of resistor R55, the second terminal of resistor R55 is sequentially connected to one end of resistor R11 and one end of resistor R7, the other end of resistor R7 is sequentially connected to the first end of resistor R55 and one end of resistor R5, the other end of resistor R5 is sequentially connected to the other end of capacitor C6 and one end of resistor R14, and the other end of resistor R14 is sequentially connected to the other end of capacitor C5 and the first terminal of amplifier U1B.

[0038] In one embodiment, the linearization circuit includes: amplifier U1A, resistors R8 and R6, capacitor C2, voltage reference chip Q1, transistor Q18, resistors R44, R1, and R45, transistor Q19, resistors R46, transistor Q2, resistors R3 and R48, resistors R50, transistor Q3, resistors R49, transistor Q20, transistor Q21, transistor R52, and transistor R51; wherein, the first terminal of transistor Q21 is sequentially connected to the transistor... The third terminal of Q21, one end of resistor R52 and resistor R51 are connected. The other end of resistor R51 is connected in sequence to one end of resistor R48 and the first terminal of transistor Q20. The second terminal of transistor Q20 is connected to one end of resistor R49. The other end of resistor R49 is connected in sequence to one end of resistor R50, one end of resistor R46, one end of resistor R45, the second terminal of amplifier U1A, and one end of capacitor C1. The other end of resistor R50 is connected to the second end of transistor Q3. The first end of transistor Q3 is connected in sequence to the other end of resistor R48 and one end of resistor R3. The other end of resistor R3 is connected in sequence to the first end of transistor Q2 and one end of resistor R1. The second end of transistor Q2 is connected to the other end of resistor R46. The other end of resistor R45 is connected to the second end of transistor Q19. The first end of transistor Q19 is connected in sequence to the other end of resistor R1 and one end of resistor R44. The other end of resistor R44 is connected to the first and third ends of transistor Q18. The second end of transistor Q18 is connected to the first end of voltage reference chip Q1. The third end of amplifier U1A is connected to resistor R8. The other end of capacitor C1 is connected to the first end of amplifier U1A, one end of resistor R6, and one end of capacitor C2. The other end of resistor R6 is connected to the other end of capacitor C2.

[0039] In one embodiment, linearizing the final output voltage by adjusting the resistance includes:

[0040] By controlling the conduction states of transistors Q20, Q3, Q2, and Q19, the resistance inside the linearization circuit is adjusted to achieve linear regulation of the final output voltage.

[0041] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0042] (1) Addressing insufficient power frequency interference suppression: This invention employs a two-stage proportional amplifier architecture (inverting + non-inverting), combined with an INA128 instrumentation amplifier (CMRR≥120dB), effectively suppressing 50Hz power frequency common-mode interference. The measured common-mode rejection ratio is ≥110dB@50Hz, and the residual power frequency noise is ≤31.6μV. The input stage integrates a symmetrical RC low-pass filter (R=10kΩ, C=47nF) with a cutoff frequency of 340Hz, attenuating power frequency harmonic components. A dual transistor mirror current source (250μA±0.5%), combined with a 1.23V Zener diode reference, results in a temperature drift ≤10ppm / ℃. The conduction-resistance separation wiring technology eliminates ground return current interference, improving the RTD signal-to-noise ratio.

[0043] (2) For equipment that is easily damaged due to lack of power supply misconnection protection: This invention supports 240VAC misconnection protection, deploys a bidirectional TVS array at the input stage, and combines a self-resetting fuse (60V / 0.5A). It passes the IEC 61000-4-5 surge test (4kV / 1.2×50μs) and meets the Class I Div 2 explosion protection requirements.

[0044] (3) Addressing signal delay caused by multi-stage filtering: VF / FV conversion timing control. Integrator + monostable multivibrator architecture (LM331), slew rate 8.8kHz, pulse width 22μs. Opto-isolation (HCPL-2630) combined with Schmitt trigger (74HC14), isolation delay ≤1μs. Dynamic response optimized filter design. Second-order active low-pass filter (cutoff frequency 100Hz), using phase compensation technology (C5 negative feedback). Compared with traditional fourth-order filter, group delay is reduced by 63% (5ms→1.85ms), step response overshoot ≤2%.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0047] Figure 1 This is a block diagram illustrating an isolated resistance temperature signal conditioning system according to an exemplary embodiment;

[0048] Figure 2 This is a system block diagram illustrated according to an exemplary embodiment;

[0049] Figure 3 This is a constant current source circuit diagram illustrated according to an exemplary embodiment;

[0050] Figure 4This is an amplifier circuit diagram illustrated according to an exemplary embodiment;

[0051] Figure 5 This is a protection circuit diagram of a dual TVS diode structure shown according to an exemplary embodiment;

[0052] Figure 6 This is one of the VF conversion circuit diagrams shown according to an exemplary embodiment;

[0053] Figure 7 This is a second VF conversion circuit diagram shown according to an exemplary embodiment;

[0054] Figure 8 This is one of the FV conversion circuit diagrams shown according to an exemplary embodiment;

[0055] Figure 9 This is a second FV conversion circuit diagram shown according to an exemplary embodiment;

[0056] Figure 10 This is a low-pass filter circuit diagram illustrated according to an exemplary embodiment;

[0057] Figure 11 This is one of the linearized circuit diagrams shown according to an exemplary embodiment;

[0058] Figure 12 This is a second linearized circuit diagram illustrated according to an exemplary embodiment;

[0059] Figure 13 This is the third linearized circuit diagram shown according to an exemplary embodiment. Detailed Implementation

[0060] The following description and accompanying drawings fully illustrate specific embodiments described herein to enable those skilled in the art to practice them. Some embodiments may include or substitute parts and features of other embodiments. The scope of the embodiments herein encompasses the entire scope of the claims and all available equivalents thereof. Throughout this document, the terms “first,” “second,” etc., are used only to distinguish one element from another without requiring or implying any actual relationship or order between the elements. Indeed, a first element can also be referred to as a second element, and vice versa. Furthermore, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a structure, apparatus, or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a structure, apparatus, or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the structure, apparatus, or device that includes said element. The various embodiments described herein are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0061] The terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer" used in this document to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings. They are used solely for the convenience of describing the document and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In the description herein, unless otherwise specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two elements; they can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0062] In this document, unless otherwise stated, the term "multiple" means two or more.

[0063] In this article, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0064] In this article, the term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0065] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0066] The modules in the apparatus or system of this application can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0067] Where there is no conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0068] Figure 1 An embodiment of an isolated resistance temperature signal conditioning system according to the present invention is shown.

[0069] In this optional embodiment, the isolated resistance temperature signal conditioning system includes:

[0070] Constant current source circuit 1 is used to provide a constant current to the resistance temperature sensor and to provide a constant current source to the VF conversion circuit.

[0071] Amplifier circuit 2 is used to amplify the voltage across the resistance temperature sensor and transmit it to the VF conversion circuit.

[0072] VF conversion circuit 3 is used to map analog voltage into frequency signal through a closed-loop mechanism of integration, comparison and reset.

[0073] FV conversion circuit 4 is used to map frequency signals back to analog voltages through a chain process of frequency, pulse width and voltage.

[0074] Low-pass filter circuit 5 is used to improve the stability of the analog voltage output by the FV conversion circuit by utilizing a low-pass filter.

[0075] Linearization circuit 6 is used to linearize the final output voltage by adjusting the resistance;

[0076] The constant current source circuit, amplifier circuit, VF conversion circuit, FV conversion circuit, low-pass filter circuit, and linearization circuit are connected in sequence.

[0077] In this optional embodiment, the constant current source circuit includes: diode D3, transistor Q17, resistor R36, resistor R67, diode D10, transistor Q26, and resistor R37; wherein, one end of resistor R37 is connected to the first end of transistor Q26, the second end of transistor Q26 is connected to the second end of transistor Q17, the third end of transistor Q17 is connected to the cathode of diode D3, the first end of transistor Q17 is connected to one end of resistor R36, the third end of transistor Q26 is connected to the cathode of diode D10, and resistor R67 is also disposed on one side of diode D10.

[0078] In this optional embodiment, the amplifier circuit includes: resistors R38, R39, and R40, amplifier U4A, resistors R36, R68, and R66, and amplifier U4B; wherein, the first terminal of amplifier U4A is sequentially connected to one end of resistor R39 and one end of resistor R40, the other end of resistor R39 is connected to one end of resistor R38, the other end of resistor R38 is sequentially connected to the third terminal of amplifier U4A and one end of resistor R69, the other end of resistor R69 is sequentially connected to the first terminal of amplifier U4B and one end of resistor R68, the other end of resistor R68 is connected to one end of resistor R66, and the other end of resistor R66 is connected to the third terminal of amplifier U4B.

[0079] In this optional embodiment, the amplifier circuit further includes a dual TVS diode protection circuit, which includes a capacitor C23 and a diode Q22, wherein the first terminal of the diode C23 and the second terminal of the diode Q22 are connected in parallel.

[0080] In this optional embodiment, the VF conversion circuit includes: switching transistor Q13, switching transistor Q14, capacitor C12, amplifier U5A, resistor R30, resistor R29, resistor R26, capacitor C10, resistor R24, resistor R25, capacitor C14, resistor R35, resistor R41, chip U1, and capacitor C11; wherein, the second terminal of the switching transistor Q13 is sequentially connected to one terminal of the capacitor C12 and the second terminal of the amplifier U5A, the other terminal of the capacitor C12 is sequentially connected to the first terminal of the amplifier U5A, the second terminal of the amplifier Q14, one terminal of the capacitor C10, and one terminal of the resistor R24, and the other terminal of the capacitor C10 is sequentially connected to the other terminal of the resistor R24, the second terminal of the amplifier Q14, one terminal of the capacitor C10, and one terminal of the resistor R24, and the third terminal of the capacitor C10 is sequentially connected to the other terminal of the resistor R24, the fourth terminal of the amplifier Q14, the fifth terminal of the amplifier Q15, the sixth terminal of the amplifier Q15, the seventh terminal of the amplifier Q15, the elliptical ... Resistor R25 is connected to the first end of chip U1, and the C1 end of chip U1 is connected to capacitor C11; the second end of chip U1 is connected to one end of resistor R26, and the other end of resistor R26 is sequentially connected to one end of resistor R30, one end of resistor R29, and the first end of switch Q13; the other end of resistor R30 is connected to the third end of amplifier U5A; the third end of switch Q13 is connected to the third end of switch Q14; the first end of switch Q14 is sequentially connected to one end of capacitor C14, one end of resistor R35, and one end of resistor R41; the other end of resistor R35 is connected to the other end of capacitor C14.

[0081] In this optional embodiment, the FV conversion circuit includes: chip U2, resistor R17, capacitor C8, capacitor C9, diode Q4, resistor R15, resistor R54, resistor R22, resistor R58, resistor R21, resistor R20, transistor Q8, resistor R61, resistor R56, capacitor C21, amplifier U6A, and transistor Q11; wherein, terminal A2 of chip U2 is connected to one end of resistor R17, the other end of resistor R17 is sequentially connected to one end of capacitor C9 and terminals A1 and B2 of chip U2, terminal C1 of chip U2 is connected to one end of capacitor C8, and the other end of capacitor C8 is connected to the other end of capacitor C9; the first terminal of transistor Q4 is sequentially connected to... Resistors R21, R20, and R58 are connected. The second terminal of transistor Q8 is sequentially connected to the second terminal of amplifier U6A, one terminal of capacitor C21, one terminal of resistor R61, and one terminal of resistor R22. The other terminal of resistor R22 is connected to one terminal of resistor R54. The other terminal of resistor R54 is sequentially connected to resistor R15 and diode Q4. The other terminal of resistor R61 is connected to one terminal of resistor R56. The other terminal of resistor R56 is sequentially connected to the other terminal of capacitor C21, the second terminal of transistor Q11, and the first terminal of amplifier U6A. The third terminal of transistor Q11 is connected to the third terminal of transistor Q8.

[0082] In this optional embodiment, mapping the frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage includes:

[0083] An optocoupler is used to isolate the output signal of the VF conversion circuit. A pulse shaping circuit then shapes the optocoupler's output signal into a square wave signal with the same frequency and fixed width as the -F conversion circuit. When the input voltage is low, transistor Q8 is cut off, and the input signal of the proportional amplifier circuit U6A is the reference voltage. When the input voltage is high, transistor Q8 is turned on, and the reference voltage and constant current source simultaneously act on the proportional amplifier circuit U6A. Based on Kirchhoff's theorem, the theoretical value of the output voltage is calculated. Using the relationship between the frequency of the input voltage and the resistance of the RTD temperature sensor, the linear relationship between the output voltage of the FV circuit and the RTD resistance is obtained.

[0084] In this optional embodiment, the low-pass filter circuit includes: capacitor C6, resistors R5, R7, R55, R11, capacitor C5, amplifier U1B, resistor R9, capacitor C4, and resistor R14; wherein, the third terminal of amplifier U1B is sequentially connected to one end of capacitor C4 and one end of resistor R9, and the other end of resistor R9 is connected to one end of capacitor C6; the second terminal of amplifier U1B is sequentially connected to one end of capacitor C5 and the third terminal of resistor R55, the second terminal of resistor R55 is sequentially connected to one end of resistor R11 and one end of resistor R7, the other end of resistor R7 is sequentially connected to the first end of resistor R55 and one end of resistor R5, the other end of resistor R5 is sequentially connected to the other end of capacitor C6 and one end of resistor R14, and the other end of resistor R14 is sequentially connected to the other end of capacitor C5 and the first terminal of amplifier U1B.

[0085] In this optional embodiment, the linearization circuit includes: amplifier U1A, resistor R8, resistor R6, capacitor C2, voltage reference chip Q1, transistor Q18, resistor R44, resistor R1, resistor R45, transistor Q19, resistor R46, transistor Q2, resistor R3, resistor R48, resistor R50, transistor Q3, resistor R49, transistor Q20, transistor Q21, transistor R52, and transistor R51; wherein, the first terminal of transistor Q21 is sequentially connected to the transistor... The third terminal of transistor Q21, one end of resistor R52 and resistor R51 are connected. The other end of resistor R51 is sequentially connected to one end of resistor R48 and the first terminal of transistor Q20. The second terminal of transistor Q20 is connected to one end of resistor R49. The other end of resistor R49 is sequentially connected to one end of resistor R50, one end of resistor R46, one end of resistor R45, the second terminal of amplifier U1A, and one end of capacitor C1. The other end of resistor R50 is connected to the second end of transistor Q3. The first end of transistor Q3 is connected in sequence to the other end of resistor R48 and one end of resistor R3. The other end of resistor R3 is connected in sequence to the first end of transistor Q2 and one end of resistor R1. The second end of transistor Q2 is connected to the other end of resistor R46. The other end of resistor R45 is connected to the second end of transistor Q19. The first end of transistor Q19 is connected in sequence to the other end of resistor R1 and one end of resistor R44. The other end of resistor R44 is connected to the first and third ends of transistor Q18. The second end of transistor Q18 is connected to the first end of voltage reference chip Q1. The third end of amplifier U1A is connected to resistor R8. The other end of capacitor C1 is connected to the first end of amplifier U1A, one end of resistor R6, and one end of capacitor C2. The other end of resistor R6 is connected to the other end of capacitor C2.

[0086] In this optional embodiment, linearizing the final output voltage by adjusting the resistance includes:

[0087] By controlling the conduction states of transistors Q20, Q3, Q2, and Q19, the resistance inside the linearization circuit is adjusted to achieve linear regulation of the final output voltage.

[0088] To facilitate understanding of the above technical solutions of the present invention, the following further describes the above technical solutions of the present invention from the perspectives of architecture and principle, as follows:

[0089] (1) To address the problem of insufficient power frequency interference suppression, an instrumentation amplifier with a high common-mode rejection ratio is used to suppress common-mode noise. The hardware filtering design is optimized, and a multi-stage low-pass filter is used to eliminate power frequency harmonics. A mirror constant current source is used to enhance stability.

[0090] (2) In view of the problem that the lack of power supply misconnection protection can easily damage the equipment, the present invention adopts the method of dual TVS diode clamping to increase the reverse protection circuit, and appropriately selects a power supply chip with a wide input voltage range.

[0091] (3) To address the signal delay caused by multi-stage filtering, this invention employs VF / FV conversion timing control and adopts a scheme of dynamically adjusting the cutoff frequency. The filtering parameters are automatically switched according to the signal rate change to balance noise suppression and response speed.

[0092] like Figure 2 As shown, the main structure consists of an excitation current source, a proportional amplifier circuit, a VF converter, an FV converter, a low-pass filter circuit, and a linearization circuit. The VF converter circuit is further composed of an integrator and a monostable multivibrator, and a switching constant current source. The FV converter circuit consists of a proportional amplifier circuit U6A, a switching constant current source, a monostable multivibrator, and some sub-circuits. Figure 2 In the diagram, the circuit to the left of the dashed line is the circuit before transformer isolation, and the circuit to the right of the dashed line is the circuit after transformer isolation.

[0093] 1. Constant current source circuit, such as Figure 3 As shown.

[0094] This part of the circuit functions to provide a constant 250uA current to the RTD and a constant current source to the VF conversion circuit. The Zener diode is included. When it breaks down, it can generate a constant voltage of 1.23V, which is used as the input of the amplifier circuit. and The two transistors form a current mirror. The emitter current of the transistor is also 250uA, and its collector current is also approximately 250uA. The tube constant current source is used as the excitation current source for the sensor. The tube provides a constant current source for the V / F conversion circuit.

[0095] 2. Amplifier circuits, such as Figure 4 As shown.

[0096] This amplifier circuit consists of two stages of proportional amplifier circuits, its function being to proportionally amplify the voltage across the RTD and then supply it to the VF conversion circuit. Constant current source circuit, Zener diode. The stable 1.23V voltage generated by the breakdown is used as the input to the amplifier circuit. The voltage across the RTD resistor is 22.4mV. First, it passes through a stage of inverting amplifier to increase the gain, and then through a non-inverting proportional amplifier circuit to enhance the output drive capability. After two stages of amplification, the output voltage is 0.9868V. Furthermore, U4 uses a high common-mode rejection ratio amplifier, which suppresses common-mode noise and improves the current problem of insufficient power frequency interference suppression in RTDs.

[0097] The following dual TVS diode protection circuit was added to the traditional proportional amplifier circuit section, such as... Figure 5 As shown in the diagram, this part of the circuit is placed between the two ends of the input signal. Capacitor C23 acts as a low-pass filter, filtering out high-frequency noise caused by environmental changes; the two Zener diodes act as a voltage protection circuit. When the input voltage is too high, the two Zener diodes break down, thus ensuring that the input voltage does not become too high and solving the problem of equipment damage due to insufficient power supply and incorrect connection protection.

[0098] 3. VF conversion circuit, such as Figures 6-7 As shown. Figure 6 Line segments ① and ② in the diagram are respectively with... Figure 7 Connect line segment ① and line segment ② in the diagram.

[0099] The VF converter circuit consists of two parts: an integrator and a monostable multivibrator, and a switching constant current source. The switching constant current source comprises the aforementioned constant current source circuit and two switching transistors. , Composition. The integrator integrates the input voltage, the reference voltage, and the constant current source. Deadline When turned on, the integrator integrates the input voltage with the reference voltage, and the integrating capacitor is charged. When the output voltage of the integrator reaches the threshold voltage of the monostable multivibrator... At that time, the output duration of the monostable multivibrator is The high level of makes Conduction, At the cutoff point, the integrator integrates the constant current source in reverse, and the integrating capacitor is discharged. Through the above integration-comparison-reset closed-loop mechanism, the analog voltage is accurately mapped to a frequency signal, thus realizing VF signal conversion. This is the decoupling capacitor for the reset terminal.

[0100] 4. FV conversion circuit, such as Figures 8-9 As shown.

[0101] The FV conversion circuit includes, for example, Figures 8-9The proportional amplifier circuit U6A, the switching constant current source, and the monostable multivibrator in the circuit are mirror images of the VF circuit. To improve the circuit's anti-interference capability, the output signal needs to be isolated after the VF conversion circuit, which can be achieved through optocouplers. Since the system function of the optocoupler circuit is nonlinear, a pulse shaping circuit needs to be added after the optocoupler circuit to shape the output signal of the optocoupler into a square wave signal with the same frequency and fixed width as the VF conversion circuit. This ensures complete transmission of the VF conversion circuit's output signal frequency and controls the switching transistor in the FV conversion circuit.

[0102] When the input voltage is low, the transistor Cut off, the input signal to the proportional amplifier circuit is the reference voltage. When the input voltage is high, the transistor... When the circuit is turned on, the reference voltage and the constant current source simultaneously act on the proportional amplifier circuit. The output voltage can be decomposed into DC and AC components. The DC component carries the temperature information of the RTD resistor; therefore, considering only the DC component, according to Kirchhoff's laws, the current flowing through the resistor... The current is equal to the difference between the current provided by the reference voltage and the average current provided by the constant current source.

[0103] Therefore, the theoretical value of the output voltage is:

[0104] ;

[0105] Where: f is the frequency of the input voltage. The high-level time in one cycle of the input voltage is T, where T is the period of the input voltage. The current supplied to the constant current source The reference voltage, This is the output voltage of the F / V conversion circuit. Input voltage high-level time. =22us, frequency f=8.8kHz, therefore the theoretical value of the DC component of the output voltage is .

[0106] Based on the relationship between f and the RTD resistance, we can know that:

[0107] ;

[0108] Where: R(T) is the external RTD circuit of the module of this invention. The current supplied to the constant current source The reference voltage, This represents the amplification factor of the proportional amplifier circuit.

[0109] Therefore, the output voltage of the FV circuit is linearly related to the RTD resistance, and the proportionality coefficient is related to the current supplied by the constant current source. Through the above frequency-pulse width-voltage chain process, the frequency information is mapped back to the analog voltage, thus realizing the FV conversion.

[0110] 5. Low-pass filter circuit, such as Figure 10 As shown.

[0111] The average output voltage of the FV circuit is 147.6mV, while the difference between the maximum and minimum values ​​is as high as 68.6mV. Therefore, a low-pass filter must be added after the FV conversion circuit to stabilize the output voltage. A second-order filter circuit is selected for this application. The circuit is shown below. Figure 10 It consists of two RC filter circuits and a non-inverting amplifier circuit. A negative feedback is introduced between the output and non-inverting input of the integrated operational amplifier. The polarity of the feedback is different in different frequency bands. >> hour( (The cutoff frequency is used as the reference point). The phase shift of each stage of the RC circuit tends to -90º, and the phase shift of the two stages of the RC circuit reaches -180º. The output voltage of the circuit is out of phase with the input voltage. Therefore, the feedback led to the non-inverting input of the integrated operational amplifier through capacitor C5 is negative feedback. The feedback signal will weaken the input signal, reducing the voltage amplification factor. Thus, this feedback will cause the high-frequency end of the amplitude-frequency characteristic of the second-order active low-pass filter to decay rapidly, allowing only low-frequency signals to pass, thereby achieving the purpose of filtering. This invention avoids the signal delay problem caused by multi-stage filtering. It should be noted that the amplification circuit of the low-pass filter section is different from the amplification circuit of the second section. This section is a single-stage non-inverting proportional amplifier circuit, while the amplification circuit of the second section is a two-stage proportional amplifier.

[0112] 6. Linearized circuits, such as Figures 11-13 As shown. Figure 11 Line segments ③ and ④ in the diagram are respectively with Figure 12 Connect line segments ③ and ④ in the diagram. Figure 12 Line segments ⑤, ⑥, and ⑦ in the diagram are respectively connected to... Figure 13 Connect line segments ⑤, ⑥, and ⑦.

[0113] Provide constant current and through multi-stage resistors for , , and The bases of the four transistors are supplied with a constant voltage. At this time, the base voltages of the four transistors decrease sequentially from left to right. Base voltage: , The product of the current and the resistance of the series resistor Q20.

[0114] same, , , The base voltages are 0.5V, 1.1V, and 1.7V respectively; enabling... , , , The input voltages for activation are 0.6V, 1.2V, 1.8V, and 2.4V. As the input voltage gradually increases, the emitter voltage of the four transistors increases, and the four transistors conduct sequentially from right to left.

[0115] When none of the four transistors are conducting, = .

[0116] When conducting, .

[0117] When conducting, .

[0118] When conducting, .

[0119] When conducting, .

[0120] in: For output voltage, The input voltage is used. When the RTD resistor changes non-linearly with temperature, the final output voltage can be made to change linearly with temperature by adjusting the resistance inside the linearization circuit.

[0121] In summary, the constant current source excitation circuit provides drive current to the RTD sensor. The VF conversion circuit and the FV conversion circuit form an isolated signal transmission channel. The constant current source excitation circuit adopts a mirror current source structure and integrates a temperature compensation resistor R1. The amplifier circuit is an instrumentation amplifier with a common-mode rejection ratio (CMRR) of [missing information]. Gain error The VF conversion circuit includes an integrator and a voltage comparator, and the output frequency meets the requirements. , Nonlinear error The FV conversion circuit employs a phase-locked loop structure, incorporating a voltage-controlled oscillator and a phase comparator, ensuring high conversion linearity. The filtering circuit is a three-stage cascaded filter, including: a field-side anti-aliasing filter, and a cutoff frequency. The system-side dual-pole low-pass filter has a cutoff frequency of... .

[0122] The anti-aliasing filter employs a switched-capacitor filter with a clock frequency 100 times the cutoff frequency. The linearization circuit includes a digital correction module that corrects the nonlinear characteristics of the RTD using a piecewise linear approximation method, maximizing the fitting error. An opto-isolation module is installed between the VF conversion circuit and the FV conversion circuit, improving the withstand voltage rating. The overall module's power frequency interference suppression ratio... Output ripple voltage Operating temperature range .

[0123] This invention is not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this invention is limited only by the appended claims.

Claims

1. An isolated resistance temperature detector (RTD) signal conditioning system, characterized in that, include: The constant current source circuit is used to provide a constant current to the resistance temperature sensor and to provide a constant current source for the VF conversion circuit. The amplifier circuit is used to proportionally amplify the voltage across the resistance temperature sensor and transmit it to the VF conversion circuit. The VF conversion circuit is used to map analog voltage into a frequency signal through a closed-loop mechanism of integration, comparison, and reset. The FV conversion circuit is used to map a frequency signal back to an analog voltage through a chain process of frequency, pulse width, and voltage. A low-pass filter circuit is used to improve the stability of the analog voltage output by the FV conversion circuit. A linearization circuit is used to linearize the final output voltage by adjusting the resistance. The constant current source circuit, the amplifier circuit, the VF conversion circuit, the FV conversion circuit, the low-pass filter circuit, and the linearization circuit are connected in sequence.

2. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 1, characterized in that, The constant current source circuit includes: diode D3, transistor Q17, resistor R36, resistor R67, diode D10, transistor Q26, and resistor R37. In this configuration, one end of resistor R37 is connected to the first end of transistor Q26, the second end of transistor Q26 is connected to the second end of transistor Q17, the third end of transistor Q17 is connected to the negative terminal of diode D3, the first end of transistor Q17 is connected to one end of resistor R36, the third end of transistor Q26 is connected to the negative terminal of diode D10, and a resistor R67 is also provided on one side of diode D10.

3. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 1, characterized in that, The amplifier circuit includes: resistors R38, R39, and R40; amplifier U4A; resistors R36, R68, and R66; and amplifier U4B. Specifically, the first terminal of amplifier U4A is connected in sequence to one end of resistor R39 and one end of resistor R40; the other end of resistor R39 is connected to one end of resistor R38; the other end of resistor R38 is connected in sequence to the third terminal of amplifier U4A and one end of resistor R69; the other end of resistor R69 is connected in sequence to the first terminal of amplifier U4B and one end of resistor R68; the other end of resistor R68 is connected to one end of resistor R66; and the other end of resistor R66 is connected to the third terminal of amplifier U4B.

4. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 1, characterized in that, The amplifier circuit also includes a dual TVS diode protection circuit, which includes a capacitor C23 and a diode Q22, wherein the first and second terminals of the diode C23 and the diode Q22 are connected in parallel.

5. The isolated resistance temperature detector (RTD) temperature signal conditioning system according to claim 1, characterized in that, The VF conversion circuit includes: switching transistor Q13, switching transistor Q14, capacitor C12, amplifier U5A, resistor R30, resistor R29, resistor R26, capacitor C10, resistor R24, resistor R25, capacitor C14, resistor R35, resistor R41, chip U1, and capacitor C11. Wherein, the second terminal of the switching transistor Q13 is connected in sequence to one terminal of the capacitor C12 and the second terminal of the amplifier U5A; the other terminal of the capacitor C12 is connected in sequence to the first terminal of the amplifier U5A, the second terminal of the amplifier Q14, one terminal of the capacitor C10 and one terminal of the resistor R24; the other terminal of the capacitor C10 is connected in sequence to the other terminal of the resistor R24, the resistor R25 and the first terminal of the chip U1; and the C1 terminal of the chip U1 is connected to the capacitor C11. The second terminal of chip U1 is connected to one end of resistor R26. The other end of resistor R26 is connected in sequence to one end of resistor R30, one end of resistor R29, and the first terminal of switch Q13. The other end of resistor R30 is connected to the third terminal of amplifier U5A. The third terminal of switch Q13 is connected to the third terminal of switch Q14. The first terminal of switch Q14 is connected in sequence to one end of capacitor C14, one end of resistor R35, and one end of resistor R41. The other end of resistor R35 is connected to the other end of capacitor C14.

6. The isolated resistance temperature detector (RTD) temperature signal conditioning system according to claim 1, characterized in that, The FV conversion circuit includes: chip U2, resistor R17, capacitor C8, capacitor C9, diode Q4, resistor R15, resistor R54, resistor R22, resistor R58, resistor R21, resistor R20, transistor Q8, resistor R61, resistor R56, capacitor C21, amplifier U6A, and transistor Q11. Wherein, the A2 terminal of the chip U2 is connected to one end of the resistor R17, the other end of the resistor R17 is connected in sequence to one end of the capacitor C9 and the A1 and B2 terminals of the chip U2, the C1 terminal of the chip U2 is connected to one end of the capacitor C8, and the other end of the capacitor C8 is connected to the other end of the capacitor C9. The first terminal of transistor Q8 is connected in sequence to resistors R21, R20, and R58. The second terminal of transistor Q8 is connected in sequence to the second terminal of amplifier U6A, one terminal of capacitor C21, one terminal of resistor R61, and one terminal of resistor R22. The other terminal of resistor R22 is connected to one terminal of resistor R54. The other terminal of resistor R54 is connected in sequence to resistor R15 and diode Q4. The other end of resistor R61 is connected to one end of resistor R56. The other end of resistor R56 is connected in sequence to the other end of capacitor C21, the second end of transistor Q11, and the first end of amplifier U6A. The third end of transistor Q11 is connected to the third end of transistor Q8.

7. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 1, characterized in that, The chained process of mapping the frequency signal back to the analog voltage through frequency, pulse width, and voltage includes: The output signal of the VF conversion circuit is isolated by an optocoupler, and the output signal of the optocoupler is shaped into a square wave signal with the same frequency and fixed width as the -F conversion circuit by a pulse shaping circuit. When the input voltage is low, transistor Q8 is cut off, and the input signal of the proportional amplifier circuit U6A is the reference voltage; When the input voltage is high, transistor Q8 is turned on, and the reference voltage and constant current source act simultaneously on the proportional amplifier circuit U6A. Based on Kirchhoff's theorem, the theoretical value of the output voltage is calculated, and by using the relationship between the frequency of the input voltage and the resistance of the RTD temperature sensor, the linear relationship between the output voltage of the FV circuit and the resistance of the RTD is obtained.

8. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 1, characterized in that, The low-pass filter circuit includes: capacitor C6, resistor R5, resistor R7, resistor R55, resistor R11, capacitor C5, amplifier U1B, resistor R9, capacitor C4, and resistor R14. The third terminal of the amplifier U1B is connected in sequence to one end of the capacitor C4 and one end of the resistor R9, and the other end of the resistor R9 is connected to one end of the capacitor C6. The second terminal of the amplifier U1B is connected in sequence to one end of the capacitor C5 and the third terminal of the resistor R55. The second terminal of the resistor R55 is connected in sequence to one end of the resistor R11 and the resistor R7. The other terminal of the resistor R7 is connected in sequence to the first terminal of the resistor R55 and one end of the resistor R5. The other terminal of the resistor R5 is connected in sequence to the other terminal of the capacitor C6 and one end of the resistor R14. The other terminal of the resistor R14 is connected in sequence to the other terminal of the capacitor C5 and the first terminal of the amplifier U1B.

9. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 1, characterized in that, The linearization circuit includes: amplifier U1A, resistor R8, resistor R6, capacitor C2, voltage reference chip Q1, transistor Q18, resistor R44, resistor R1, resistor R45, transistor Q19, resistor R46, transistor Q2, resistor R3, resistor R48, resistor R50, transistor Q3, resistor R49, transistor Q20, transistor Q21, transistor R52, and transistor R51; In this configuration, the first terminal of transistor Q21 is sequentially connected to the third terminal of transistor Q21, resistor R52, and one end of resistor R51. The other end of resistor R51 is sequentially connected to one end of resistor R48 and the first terminal of transistor Q20. The second terminal of transistor Q20 is connected to one end of resistor R49. The other end of resistor R49 is sequentially connected to one end of resistor R50, one end of resistor R46, one end of resistor R45, the second terminal of amplifier U1A, and one end of capacitor C1. The other end of resistor R50 is connected to the second terminal of transistor Q3. The first terminal of transistor Q3 is sequentially connected to the other end of resistor R48 and one end of resistor R3. The other end of resistor R3 is sequentially connected to the first terminal of transistor Q2 and one end of resistor R1. The second terminal of transistor Q2 is connected to the other end of resistor R46. The other end of the resistor R45 is connected to the second end of the transistor Q19. The first end of the transistor Q19 is connected to the other end of the resistor R1 and one end of the resistor R44 in sequence. The other end of the resistor R44 is connected to the first and third ends of the transistor Q18. The second end of the transistor Q18 is connected to the first end of the voltage reference chip Q1. The third terminal of the amplifier U1A is connected to the resistor R8. The other terminal of the capacitor C1 is connected to the first terminal of the amplifier U1A, one terminal of the resistor R6, and one terminal of the capacitor C2. The other terminal of the resistor R6 is connected to the other terminal of the capacitor C2.

10. The isolated resistance temperature detector (RTD) signal conditioning system according to claim 9, characterized in that, The method of linearizing the final output voltage by adjusting the resistance includes: By controlling the conduction states of transistors Q20, Q3, Q2, and Q19, the resistance inside the linearization circuit is adjusted to achieve linear regulation of the final output voltage.

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