Differential amplification circuit, power amplifier and electronic equipment

Abstract

The utility model discloses a differential amplification circuit, a power amplifier and electronic equipment, relates to the field of electronic circuits, and solves the problem of low linearity of a differential amplifier adopting a current multiplexing structure. Input power supply voltage is fed into the first-stage amplification circuit through the input transformer, current is multiplexed to the second-stage amplification circuit, the first-stage amplification circuit is in alternating current grounding through the bypass capacitor, the second-stage amplification circuit is directly grounded, and after an input signal is amplified by the first-stage amplification circuit, the second-stage amplification circuit is directly grounded. According to the differential amplifier, the alternating current signal grounding is more ideal, the voltage swing on a transistor in the cascode amplification circuit is higher, the linearity of the amplifier can be remarkably improved, the cascade linearity is ensured, and the problem that the linearity is deteriorated due to a traditional current multiplexing structure of the differential amplifier is solved.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuits, and in particular to a differential amplifier circuit, a power amplifier, and an electronic device. Background Technology

[0002] Amplifiers are a crucial component of wireless transceiver systems, and low-power, high-linearity differential amplifiers are particularly important in satellite communications, primarily due to their impact on signal quality, system energy efficiency, and reliability. Satellite equipment is typically constrained by energy supply; low-power designs can significantly improve overall system performance, extend equipment lifespan, or even reduce battery size. Differential circuitry provides immunity to common-mode interference and effectively suppresses noise in the electromagnetic environment, improving signal integrity—crucial for stable communication in complex space environments. Simultaneously, high linearity reduces signal distortion, enhances signal integrity, and prevents increased bit error rates due to nonlinear effects, further ensuring the quality of the communication link.

[0003] Differential amplifiers typically employ a current-reused structure, which achieves low-power design by having multiple stages of transistors share a current path. This structure causes the operating points of each stage of transistors to deviate from the optimal linear region.

[0004] When multi-stage amplifiers operate dynamically, the shared current fluctuates with the input signal, causing the operating points of each stage transistor to shift and resulting in nonlinear superposition, especially the superposition of third-order intermodulation distortion (IMD3). This nonlinearity mainly originates from the change in the transconductance of the transistor with the amplitude of the input signal (AM-AM distortion), and the traditional current multiplexing structure exacerbates this nonlinear characteristic.

[0005] It is evident that the low linearity of differential amplifiers employing current multiplexing structures is a technical problem that urgently needs to be solved by those skilled in the art. Utility Model Content

[0006] The purpose of this invention is to provide a differential amplifier circuit, a power amplifier, and an electronic device to solve the problem of low linearity in differential amplifiers using current multiplexing structures.

[0007] To solve the above-mentioned technical problems, this utility model provides a differential amplifier circuit, comprising:

[0008] The amplifier circuit includes an input transformer, a first-stage amplifier circuit, an intermediate transformer, a second-stage amplifier circuit, an output transformer, and a bypass capacitor. The first-stage amplifier circuit is a common-source amplifier circuit, and the second-stage amplifier circuit is a common-source cascode amplifier circuit.

[0009] The input terminal of the input transformer receives the input voltage signal. The output terminal of the input transformer is connected to the input terminal of the first-stage amplifier circuit. The output terminal of the first-stage amplifier circuit is connected to the input terminal of the intermediate transformer. The output terminal of the intermediate transformer is connected to the input terminal of the second-stage amplifier circuit. The output terminal of the second-stage amplifier circuit is connected to the input terminal of the output transformer. The common terminal of the first-stage amplifier circuit is connected to the center tap of the main coil of the output transformer. The common terminal of the first-stage amplifier circuit is grounded through a bypass capacitor, and the common terminal of the second-stage amplifier circuit is directly grounded.

[0010] As an alternative, in the above differential amplifier circuit, the first stage amplifier circuit includes: a first transistor, a second transistor, a first neutralizing capacitor, and a second neutralizing capacitor;

[0011] The first end of the secondary coil of the input transformer is connected to the gate of the first transistor, and the second end of the secondary coil of the input transformer is connected to the gate of the second transistor; the source of the first transistor and the source of the second transistor are connected to the first end of the bypass capacitor and the center tap of the main coil of the output transformer; the second end of the bypass capacitor is grounded; the gate of the first transistor is connected to the drain of the second transistor and the second end of the main coil of the intermediate transformer through the second neutralizing capacitor; the gate of the second transistor is connected to the drain of the first transistor and the first end of the main coil of the intermediate transformer through the first neutralizing capacitor.

[0012] As an alternative, in the above differential amplifier circuit, the second stage amplifier circuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor;

[0013] The first end of the secondary coil of the intermediate transformer is connected to the gate of the third transistor, the source of the third transistor is grounded, the drain of the third transistor is connected to the source of the fourth transistor, the gate of the fourth transistor is connected to the first bias power supply, and the gate of the fourth transistor is grounded through the first capacitor.

[0014] The second end of the secondary coil of the intermediate transformer is connected to the gate of the fifth transistor, the source of the fifth transistor is grounded, the drain of the fifth transistor is connected to the source of the sixth transistor, the gate of the sixth transistor is connected to the first bias power supply, and the gate of the sixth transistor is grounded through the second capacitor.

[0015] The drain of the fourth transistor is connected to the first end of the main coil of the output transformer, and the drain of the sixth transistor is connected to the second end of the main coil of the output transformer.

[0016] As an alternative, in the above differential amplifier circuit, the second stage amplifier circuit further includes: a seventh transistor, an eighth transistor, a first DC blocking capacitor, and a second DC blocking capacitor;

[0017] The gate of the seventh transistor is connected to the first terminal of the secondary coil of the intermediate transformer through the first DC blocking capacitor. The gate of the seventh transistor is connected to the second bias power supply. The source of the seventh transistor is grounded. The drain of the seventh transistor is connected to the drain of the third transistor.

[0018] The gate of the eighth transistor is connected to the second terminal of the secondary coil of the intermediate transformer through the second DC blocking capacitor. The gate of the eighth transistor is connected to the second bias power supply. The source of the eighth transistor is grounded. The drain of the eighth transistor is connected to the drain of the fourth transistor.

[0019] As an optional solution, in the above differential amplifier circuit, the second stage amplifier circuit further includes: a first resistor, a second resistor, and

[0020] The gate of the fourth transistor is connected to the first bias power supply through the first resistor; the gate of the sixth transistor is connected to the first bias power supply through the second resistor.

[0021] As an optional solution, in the above differential amplifier circuit, the second stage amplifier circuit further includes: a third resistor, a fourth resistor, and...

[0022] The drain of the seventh transistor is connected to the drain of the third transistor; the drain of the eighth transistor is connected to the drain of the fourth transistor.

[0023] As an optional solution, in the above differential amplifier circuit, the first stage amplifier circuit further includes: a third capacitor;

[0024] The third capacitor is connected in parallel between the drain of the first transistor and the drain of the second transistor.

[0025] As an optional solution, the differential amplifier circuit described above also includes: a fourth capacitor;

[0026] The fourth capacitor is connected in parallel across the secondary coil of the output transformer.

[0027] To solve the above-mentioned technical problems, this utility model also provides a power amplifier, including the differential amplifier circuit described above.

[0028] To solve the above-mentioned technical problems, this utility model provides an electronic device, including a transmitter; the transmitter uses the power amplifier described above.

[0029] The differential amplifier circuit provided by this utility model feeds the input power supply voltage into the first-stage amplifier circuit through an input transformer, and the current is multiplexed into the second-stage amplifier circuit. The first-stage amplifier circuit is AC grounded through a bypass capacitor, while the second-stage amplifier circuit is directly grounded. After the input signal is amplified by the first-stage amplifier circuit, the second-stage amplifier circuit is directly grounded, which is beneficial for more ideal AC signal grounding. The voltage swing of the transistor in the common-source common-gate amplifier circuit is higher, which can significantly improve the linearity of the amplifier and ensure the cascade linearity. This solves the problem of linearity degradation caused by the traditional current multiplexing structure of differential amplifiers.

[0030] In addition, this utility model also provides a power amplifier and electronic device, including the above-mentioned differential amplifier circuit, with the same effect. Attached Figure Description

[0031] To more clearly illustrate the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a differential amplifier circuit provided in an embodiment of this application;

[0033] Figure 2 A circuit diagram of a differential amplifier circuit provided in an embodiment of this application;

[0034] The attached figures are labeled as follows:

[0035] 11-Input transformer; 12-First stage amplifier circuit; 13-Intermediate transformer; 14-Second stage amplifier circuit; 15-Output transformer. Detailed Implementation

[0036] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0037] The core of this utility model is to provide a differential amplifier circuit, a power amplifier, and an electronic device.

[0038] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Traditional current-reusing structures achieve low-power designs by sharing current paths among multiple transistor stages. However, this structure causes the operating points of each transistor stage to deviate from their optimal linear regions. During dynamic operation, the shared current of the multi-stage amplifier fluctuates with the input signal, causing the operating points of each transistor stage to shift and resulting in nonlinear superposition, particularly the superposition of third-order intermodulation distortion (IMD3). This nonlinearity primarily stems from the variation of transistor transconductance with the amplitude of the input signal (AM-AM distortion), and the traditional current-reusing structure exacerbates this nonlinear characteristic.

[0040] To address the aforementioned problems, embodiments of this application provide a differential amplifier circuit. Figure 1 This is a schematic diagram of a differential amplifier circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, it includes:

[0041] The circuit includes an input transformer 11, a first-stage amplifier circuit 12, an intermediate transformer 13, a second-stage amplifier circuit 14, an output transformer 15, and a bypass capacitor; wherein, the first-stage amplifier circuit 12 is a common-source amplifier circuit, and the second-stage amplifier circuit 14 is a common-source cascode amplifier circuit.

[0042] The input terminal of the input transformer 11 receives the input voltage signal. The output terminal of the input transformer 11 is connected to the input terminal of the first-stage amplifier circuit 12. The output terminal of the first-stage amplifier circuit 12 is connected to the input terminal of the intermediate transformer 13. The output terminal of the intermediate transformer 13 is connected to the input terminal of the second-stage amplifier circuit 14. The output terminal of the second-stage amplifier circuit 14 is connected to the input terminal of the output transformer 15. The common terminal of the first-stage amplifier circuit 12 is connected to the center tap of the main coil of the output transformer 15. The common terminal of the first-stage amplifier circuit 12 is grounded through a bypass capacitor, and the common terminal of the second-stage amplifier circuit 14 is directly grounded.

[0043] In this embodiment, the input transformer 11 is used to receive the input voltage signal. The input voltage signal enters through the input terminal of the input transformer 11, receives the external input voltage signal, converts it into a voltage signal suitable for processing by the first-stage amplifier circuit 12, and transmits it to the input terminal of the first-stage amplifier circuit 12. The first-stage amplifier circuit 12 adopts a common-source amplifier circuit structure, which is a common-source amplifier circuit composed of transistors. In the common-source amplifier circuit structure, the input signal is initially amplified and provides sufficient gain and linearity. The bypass capacitor is connected to the common terminal (i.e., the common-source terminal) of the first-stage amplifier circuit 12 for grounding and filtering out high-frequency noise. Specifically, the appropriate capacitance value and withstand voltage rating are selected according to the noise frequency characteristics and the circuit operating voltage.

[0044] The amplified signal is transmitted from the output of the first-stage amplifier circuit 12 to the intermediate transformer 13. The intermediate transformer 13 is used for signal transmission between the first-stage amplifier circuit 12 and the second-stage amplifier circuit 14, transmitting the amplified signal to the input of the second-stage amplifier circuit 14, while achieving impedance matching and signal isolation.

[0045] The second-stage amplifier circuit 14 employs a common-source, common-gate amplifier circuit, a basic two-stage amplifier circuit. Appropriate transistor types and bias circuits are selected based on gain, linearity, and stability requirements. In the common-source, common-gate amplifier circuit structure, the signal is further amplified, improving the overall circuit gain and linearity.

[0046] The amplified signal is output from the output terminal of the second-stage amplifier circuit 14 and connected to the output transformer 15. The output transformer 15 outputs the amplified signal to the load, while achieving impedance matching and signal isolation.

[0047] The direct grounding of the second-stage amplifier circuit 14 makes the AC signal grounding more ideal, and the voltage swing of the transistor in the common-source common-gate amplifier circuit is higher, which can significantly improve the linearity of the amplifier.

[0048] In specific applications, if the signal frequency is low and the impedance matching requirements are not high, the input transformer 11 and the output transformer 15 can be replaced by direct coupling or capacitive coupling instead of transformer coupling.

[0049] The differential amplifier circuit provided in this application includes: an input transformer 11, a first-stage amplifier circuit 12, an intermediate transformer 13, a second-stage amplifier circuit 14, an output transformer 15, and a bypass capacitor; wherein, the first-stage amplifier circuit 12 is a common-source amplifier circuit, and the second-stage amplifier circuit 14 is a common-source common-gate amplifier circuit; the input terminal of the input transformer 11 receives the input voltage signal, the output terminal of the input transformer 11 is connected to the input terminal of the first-stage amplifier circuit 12, the output terminal of the first-stage amplifier circuit 12 is connected to the input terminal of the intermediate transformer 13, the output terminal of the intermediate transformer 13 is connected to the input terminal of the second-stage amplifier circuit 14, the output terminal of the second-stage amplifier circuit 14 is connected to the input terminal of the output transformer 15, and the common terminal of the first-stage amplifier circuit 12 is connected to the center tap point of the main coil of the output transformer 15; the common terminal of the first-stage amplifier circuit 12 is grounded through the bypass capacitor, and the common terminal of the second-stage amplifier circuit 14 is directly grounded. The input power supply voltage is fed into the first-stage amplifier circuit 12 through the input transformer 11, and the current is multiplexed to the second-stage amplifier circuit 14. The first-stage amplifier circuit 12 is AC grounded through a bypass capacitor, while the second-stage amplifier circuit 14 is directly grounded. After the input signal is amplified by the first-stage amplifier circuit 12, the second-stage amplifier circuit 14 is directly grounded, which is beneficial for more ideal AC signal grounding. The voltage swing of the transistor in the common-source common-gate amplifier circuit is higher, which can significantly improve the linearity of the amplifier, ensure the cascade linearity, and solve the problem of linearity degradation caused by the traditional current multiplexing structure of differential amplifiers.

[0050] Based on the above embodiments, this application provides a specific implementation scheme. Figure 2 A circuit diagram of a differential amplifier circuit provided in an embodiment of this application is shown below. Figure 2 As shown, the first-stage amplifier circuit 12 includes: a first transistor M1, a second transistor M2, a first neutralizing capacitor Cc1, and a second neutralizing capacitor Cc2;

[0051] The first end of the secondary coil of the input transformer 11 is connected to the gate of the first transistor M1, and the second end of the secondary coil of the input transformer 11 is connected to the gate of the second transistor M2; the source of the first transistor M1 and the source of the second transistor M2 are connected to the first end of the bypass capacitor and the center tap of the main coil of the output transformer 15; the second end of the bypass capacitor is grounded; the gate of the first transistor M1 is connected to the drain of the second transistor M2 and the second end of the main coil of the intermediate transformer 13 through the second neutralizing capacitor Cc2; the gate of the second transistor M2 is connected to the drain of the first transistor M1 and the first end of the main coil of the intermediate transformer 13 through the first neutralizing capacitor Cc1.

[0052] In this embodiment, the source of the first transistor M1 and the source of the second transistor M2 are connected together to the first terminal of the bypass capacitor and the center tap of the main coil of the output transformer 15. This achieves current multiplexing of the signal, reduces power consumption, and provides a certain bias voltage through the center tap of the main coil of the output transformer 15.

[0053] Bypass capacitor grounding helps filter out high-frequency noise, provides RF grounding, and enhances circuit balance.

[0054] The two neutralizing capacitors are used to improve the gain and stability of the amplifier circuit and reduce frequency response problems caused by transistor parasitic capacitance.

[0055] Additionally, it should be noted that the center tap of the main coil of the intermediate transformer 13 is connected to the power supply VDD; the inductors LP1 and LS1 constitute the input transformer 11 (k1 is the coupling coefficient of the inductors LP1 and LS1) to achieve wide input matching, and the center tap of the secondary coil LS1 provides bias voltage VG1 to the first transistor M1 and the second transistor M2.

[0056] In this embodiment, when the input signal is applied to the gates of the two transistors through the input transformer 11, the signal is initially amplified due to the amplification effect of the transistors. Current flows out through the common path between the sources of the two transistors, achieving current multiplexing and reducing power consumption. The neutralizing capacitor compensates for the effects of the transistor's parasitic capacitance, improving the circuit's frequency response and stability. The bypass capacitor provides an AC ground path for the first-stage amplifier circuit 12, filtering out high-frequency noise.

[0057] According to the above embodiments, this application provides a specific implementation scheme, wherein the second-stage amplifier circuit 14 includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2;

[0058] The first end of the secondary coil of the intermediate transformer 13 is connected to the gate of the third transistor M3. The source of the third transistor M3 is grounded. The drain of the third transistor M3 is connected to the source of the fourth transistor M4. The gate of the fourth transistor M4 is connected to the first bias power supply VG3. The gate of the fourth transistor M4 is grounded through the first capacitor C1.

[0059] The second end of the secondary coil of the intermediate transformer 13 is connected to the gate of the fifth transistor M5. The source of the fifth transistor M5 is grounded. The drain of the fifth transistor M5 is connected to the source of the sixth transistor M6. The gate of the sixth transistor M6 is connected to the first bias power supply VG3. The gate of the sixth transistor M6 is grounded through the second capacitor C2.

[0060] The drain of the fourth transistor M4 is connected to the first end of the main coil of the output transformer 15, and the drain of the sixth transistor M6 is connected to the second end of the main coil of the output transformer 15.

[0061] Inductors LP2 and LS2 form an intermediate transformer 13 (k2 is the coupling coefficient of inductors LP2 and LS2) to achieve interstage matching. The center tap of the main coil LP2 provides the power supply voltage VDD, and the center tap of the secondary coil LS2 provides the bias voltage VG2A to the cores M3 and M5.

[0062] In this embodiment, when the signal output from the first-stage amplifier circuit 12 is applied to the gates of the third transistor M3 and the fifth transistor M5 via the intermediate transformer 13, these two transistors further amplify the signal. The cascode structure (composed of M3-M4 and M5-M6) improves the circuit's gain and linearity, and reduces signal distortion. The first capacitor C1 and the second capacitor C2 bypass high-frequency noise, improving circuit stability. The output transformer 15 matches and outputs the amplified signal, ensuring that the signal can be efficiently transmitted to the next stage circuit.

[0063] According to the above embodiments, this application provides a specific implementation scheme, wherein the second-stage amplifier circuit 14 further includes: a seventh transistor M7, an eighth transistor M8, a first DC blocking capacitor Cf1, and a second DC blocking capacitor Cf2;

[0064] The gate of the seventh transistor M7 is connected to the first terminal of the secondary coil of the intermediate transformer 13 through the first DC blocking capacitor Cf1. The gate of the seventh transistor M7 is connected to the second bias power supply VG2B. The source of the seventh transistor M7 is grounded. The drain of the seventh transistor M7 is connected to the drain of the third transistor M3.

[0065] The gate of the eighth transistor M8 is connected to the second terminal of the secondary coil of the intermediate transformer 13 through the second DC blocking capacitor Cf2. The gate of the eighth transistor M8 is connected to the second bias power supply VG2B. The source of the eighth transistor M8 is grounded. The drain of the eighth transistor M8 is connected to the drain of the fourth transistor M4.

[0066] This embodiment adds a seventh transistor M7 and an eighth transistor M8 as auxiliary amplification chips for the cascode structure.

[0067] The drain current of a transistor can be expressed as follows by Taylor series expansion:

[0068] ;

[0069] In the formula, This represents the drain-source current of the transistor. Indicates the transconductance of a transistor. Indicates the nominal DC current. This represents the gate-source voltage of a transistor.

[0070] In the above formula The cubic term is significantly correlated with the third-order crosstalk point;

[0071] When transistors M3 or M5 are biased at VG2A (VG2A > threshold voltage Vth), g"m < 0;

[0072] At this point, adjust the bias voltage VG2B of the auxiliary amplification transistors M7 and M8 so that transistors M7 and M8 are in the subthreshold region, and g"m>0.

[0073] When the signal is amplified and combined by the main amplifier transistor and the auxiliary amplifier transistor respectively, the third-order intermodulation components of the main amplifier transistor and the third-order intermodulation components of the auxiliary amplifier transistor will cancel each other out, thereby achieving high linearity output.

[0074] The first DC blocking capacitor Cf1 and the second DC blocking capacitor Cf2 isolate the DC signal while allowing the AC signal to pass through, thereby avoiding the influence of DC bias on the amplifier circuit.

[0075] After the input signal is amplified by the first stage, it is coupled to the gates of the seventh transistor M7 and the eighth transistor M8 in the second-stage amplifier circuit 14 through the intermediate transformer 13. The seventh transistor M7 and the eighth transistor M8, as auxiliary amplifiers in a cascode structure, work together with the third transistor M3 and the fourth transistor M4 (the main amplifier) ​​to provide higher voltage swing and linearity. By adjusting the voltage of the second bias power supply (VG2B), the operating state of the seventh transistor M7 and the eighth transistor M8 can be controlled, causing them to cancel out the third-order intermodulation components generated by the main amplifier, thereby increasing the third-order intermodulation point of the circuit and achieving high linearity output.

[0076] According to the above embodiments, this application provides a specific implementation scheme, wherein the second-stage amplifier circuit 14 further includes: a first resistor R1, a second resistor R2, and...

[0077] The gate of the fourth transistor M4 is connected to the first bias power supply VG3 through the first resistor R1; the gate of the sixth transistor M6 is connected to the first bias power supply VG3 through the second resistor R2.

[0078] In this embodiment, the transistor's gate is connected to the bias power supply via a resistor, which limits the current in the circuit and prevents overcurrent damage to circuit components. It also acts as a voltage regulator. When the power supply output voltage fluctuates significantly, the voltage in the circuit can be stabilized by adjusting the resistor value. This ensures the stability and reliability of the circuit while protecting the transistor and other circuit components. It also prevents signal attenuation, thereby improving the circuit's sensitivity and stability. Furthermore, the large gate resistor also provides isolation, preventing mutual interference between circuits.

[0079] Similarly, the second-stage amplifier circuit 14 also includes: a third resistor R3, a fourth resistor R4,

[0080] The drain of the seventh transistor M7 is connected to the drain of the third transistor M3; the drain of the eighth transistor M8 is connected to the drain of the fourth transistor M4.

[0081] According to the above embodiments, this application provides a specific implementation scheme, wherein the first-stage amplifier circuit 12 further includes: a third capacitor C3;

[0082] The third capacitor C3 is connected in parallel between the drain of the first transistor M1 and the drain of the second transistor M2.

[0083] It also includes: the fourth capacitor C4;

[0084] The fourth capacitor C4 is connected in parallel across the secondary coil of the output transformer 15.

[0085] The third capacitor, C3, is a parallel capacitor and participates in inter-stage matching. The fourth capacitor, C4, is a parallel capacitor and participates in output matching.

[0086] Finally, this application also provides a power amplifier including the differential amplifier circuit described above.

[0087] This application also provides an electronic device, including a transmitter; the power amplifier described above is included in the transmitter.

[0088] The electronic device provided in this application embodiment includes a transmitter, and the power amplifier used in the transmitter includes a differential amplifier circuit. By using the circuit structure of the first-stage amplifier current multiplexing the second-stage amplifier circuit 14, the power supply voltage can be increased and the circuit power consumption and cost can be reduced.

[0089] The differential amplifier circuit, power amplifier, and electronic device provided by this utility model have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to this utility model without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this utility model.

[0090] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A differential amplifier circuit, characterized in that, include: Input transformer (11), first-stage amplifier circuit (12), intermediate transformer (13), second-stage amplifier circuit (14), output transformer (15), bypass capacitor; wherein, the first-stage amplifier circuit (12) is a common-source amplifier circuit, and the second-stage amplifier circuit (14) is a common-source common-gate amplifier circuit; The input terminal of the input transformer (11) receives the input voltage signal. The output terminal of the input transformer (11) is connected to the input terminal of the first stage amplifier circuit (12). The output terminal of the first stage amplifier circuit (12) is connected to the input terminal of the intermediate transformer (13). The output terminal of the intermediate transformer (13) is connected to the input terminal of the second stage amplifier circuit (14). The output terminal of the second stage amplifier circuit (14) is connected to the input terminal of the output transformer (15). The common terminal of the first stage amplifier circuit (12) is connected to the center tap point of the main coil of the output transformer (15). The common terminal of the first stage amplifier circuit (12) is grounded through a bypass capacitor, and the common terminal of the second stage amplifier circuit (14) is directly grounded.

2. The differential amplifier circuit according to claim 1, characterized in that, The first stage amplifier circuit (12) includes: a first transistor, a second transistor, a first neutralizing capacitor, and a second neutralizing capacitor; The first end of the secondary coil of the input transformer (11) is connected to the gate of the first transistor, and the second end of the secondary coil of the input transformer (11) is connected to the gate of the second transistor; the source of the first transistor and the source of the second transistor are connected to the first end of the bypass capacitor and the center tap of the main coil of the output transformer (15); the second end of the bypass capacitor is grounded; the gate of the first transistor is connected to the drain of the second transistor and the second end of the main coil of the intermediate transformer (13) through the second neutralizing capacitor; the gate of the second transistor is connected to the drain of the first transistor and the first end of the main coil of the intermediate transformer (13) through the first neutralizing capacitor.

3. The differential amplifier circuit according to claim 1, characterized in that, The second-stage amplifier circuit (14) includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor; The first end of the secondary coil of the intermediate transformer (13) is connected to the gate of the third transistor, the source of the third transistor is grounded, the drain of the third transistor is connected to the source of the fourth transistor, the gate of the fourth transistor is connected to the first bias power supply, and the gate of the fourth transistor is grounded through the first capacitor. The second end of the secondary coil of the intermediate transformer (13) is connected to the gate of the fifth transistor. The source of the fifth transistor is grounded. The drain of the fifth transistor is connected to the source of the sixth transistor. The gate of the sixth transistor is connected to the first bias power supply. The gate of the sixth transistor is grounded through the second capacitor. The drain of the fourth transistor is connected to the first end of the main coil of the output transformer (15), and the drain of the sixth transistor is connected to the second end of the main coil of the output transformer (15).

4. The differential amplifier circuit according to claim 3, characterized in that, The second-stage amplifier circuit (14) also includes: a seventh transistor, an eighth transistor, a first DC blocking capacitor, and a second DC blocking capacitor; The gate of the seventh transistor is connected to the first end of the secondary coil of the intermediate transformer (13) through the first DC blocking capacitor. The gate of the seventh transistor is connected to the second bias power supply. The source of the seventh transistor is grounded. The drain of the seventh transistor is connected to the drain of the third transistor. The gate of the eighth transistor is connected to the second end of the secondary coil of the intermediate transformer (13) through the second DC blocking capacitor. The gate of the eighth transistor is connected to the second bias power supply. The source of the eighth transistor is grounded. The drain of the eighth transistor is connected to the drain of the fourth transistor.

5. The differential amplifier circuit according to claim 3, characterized in that, The second-stage amplifier circuit (14) also includes: a first resistor and a second resistor; The gate of the fourth transistor is connected to the first bias power supply through the first resistor; the gate of the sixth transistor is connected to the first bias power supply through the second resistor.

6. The differential amplifier circuit according to claim 4, characterized in that, The second-stage amplifier circuit (14) also includes: a third resistor and a fourth resistor; The drain of the seventh transistor is connected to the drain of the third transistor; the drain of the eighth transistor is connected to the drain of the fourth transistor.

7. The differential amplifier circuit according to claim 2, characterized in that, The first stage amplifier circuit (12) also includes: a third capacitor; The third capacitor is connected in parallel between the drain of the first transistor and the drain of the second transistor.

8. The differential amplifier circuit according to any one of claims 1 to 7, characterized in that, Also includes: Fourth capacitor; The fourth capacitor is connected in parallel across the secondary coil of the output transformer (15).

9. A power amplifier, characterized in that, Includes the differential amplifier circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes a transmitter; the transmitter employs the power amplifier as described in claim 9.

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