Low-current mismatch charge pump circuit applied to phase-locked loop

Abstract

The utility model relates to a low-current mismatch charge pump circuit applied to a CMOS charge pump phase-locked loop (CPPLL). According to the low-current mismatch circuit, through a negative feedback loop formed by a source follower (SF), an operational amplifier (OPA) and a common gate buffer (CG), the drain end voltage of a common source of a cascode current source is clamped, and the change of the drain end voltage of the current source caused by the change of the drain end voltage of a common gate of a cascode current mirror is suppressed, so that low-current mismatch is realized. In addition, through a buffer formed by a cascode current mirror, a current source and drain electrode switch tube and a rail-to-rail operational amplifier capable of clamping an output point, the problems of electric leakage of a charge pump with a conventional structure, mismatch of currents of a positive current source and a negative current source and charge sharing are solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology. Background Technology

[0002] Clock generation circuits are among the most important functional circuits in integrated circuit chip systems, finding wide applications in wireless communication, microprocessor systems, smart wearable devices, portable electronic devices, medical measurement equipment, and more. High-speed ADCs (Analog to Digital Converters) require a stable, low-jitter clock signal as a sampling reference clock to ensure sampling accuracy. Digital circuits also require a high-quality reference clock to ensure normal operation and logic signal processing. This reference clock is typically implemented using phase-locked loops (PLLs). The design must meet the aforementioned low clock jitter performance requirements while also satisfying the requirements of low power consumption, low cost, and small area, which places higher demands on the design of integrated clock circuits.

[0003] Charge pump phase-locked loops (PLLs) in CMOS integrated phase-locked loops (PLLs) have become one of the most widely used PLL architectures due to their advantages such as large open-loop gain, wide frequency capture range, and ease of fabrication into fractional-order PLLs. As the core module for digital-to-analog conversion, the charge pump circuit's performance indicators, including charge / discharge current mismatch, switching speed, voltage output swing range, and low noise, all affect the two key indicators of the entire PLL system: phase noise and spurious emissions. The magnitude of the charge pump current mismatch affects the input tuning voltage ripple of the voltage-controlled oscillator (VCO) in the PLL; severe mismatch worsens reference spurious emissions and increases clock jitter. Therefore, research on low-mismatch charge pump circuits applied to CPPLLs is of great significance. Summary of the Invention

[0004] The purpose of this invention is to provide a simple and practical charge pump circuit with low charge / discharge current mismatch for CMOS charge pump phase-locked loop circuits. This reduces clock jitter in the charge pump phase-locked loop output signal. Based on a drain-switched charge pump with operational amplifiers, this invention achieves drain voltage clamping of the common-source current source of a cascode current source by applying two five-transistor transconductance amplifiers (5OTA) and four source followers, thereby achieving lower charge / discharge current mismatch while retaining the original reliable circuitry. Figure 1 (3, 4, 5) The basic structure charge pump has advantages such as suppressing charge sharing and current mismatch, and can operate at higher frequencies. Attached Figure Description

[0005] Figure 1. A charge pump circuit with low current mismatch applied to a phase-locked loop.

[0006] Figure 2. MOS diode connection and reference and replica current sources.

[0007] Figure 3. Schematic diagram of current mirror and mirror current source

[0008] Figure 4. Measurement, negative feedback loop, discharge current source and replica current source and 5OTA structure

[0009] Figure 5. Schematic diagram of switch and rail-to-rail operational amplifier structure

[0010] Figure 6. Comparison of the degree of change in charging current before and after the circuit structure change under static operation.

[0011] Figure 7 Comparison of the degree of change in discharge current before and after the circuit structure change under static operation

[0012] Figure 8 Comparison of the degree of change in charging and discharging current under static operation after circuit modification

[0013] Figure 9 Comparison of the degree of change in charging and discharging current under dynamic operation after circuit modification

[0014] To achieve the above objectives, the technical solution adopted by this invention is as follows: a current bias circuit employing a common-source, common-gate structure replicates a discharge reference current source and a discharge current source; after the discharge reference current source flows through an adaptive charging reference current source (a PMOS connected to a diode), a discharge current source is replicated from the discharge reference current source. The specific implementation is as follows:

[0015] M1 gate and drain connected to iu <0> The source of M1 is connected to the drain of M2; the gate of M2 is connected to iu. <0> The source of M2 is connected to G, and the drain of M2 is connected to M1.

[0016] M3 gate connection iu <0> The source of M3 is connected to the drain of M4, and the drain of M3 is connected to iu. <1> M4 gate connection iu <0> The source of M4 is connected to G, and the drain of M4 is connected to the source of M3.

[0017] M5 gate connection iu <0> The source of M5 is connected to the drain of M6, and the drain of M5 is connected to the gates of M19 and M20, and then connected to the drain of M20; the gate of M6 is connected to iu. <1> The source of M6 is connected to G, and the drain of M6 is connected to the source of M5;

[0018] M7 gate connection iu <0> The source of M7 is connected to the drain of M8, and the drain of M7 is connected to the gates of M21 and M20, and then connected to the drain of M20; the gate of M8 is connected to iu. <1> The source of M8 is connected to G, and the drain of M8 is connected to the source of M7;

[0019] M9 gate connection iu <0> The source of M9 is connected to the drain of M10, the drain of M9 is connected to the source of M15 and then connected to the positive terminal of M42; the gate of M10 is connected to iu. <1> The source of M10 is connected to G, and the drain of M10 is connected to the source of M9;

[0020] M11 gate connection iu <0> M11 is connected to the drain of M12, the drain of M11 is connected to the source of M16 and then to the negative terminal of M42; the gate of M12 is connected to iu. <1> The source of M12 is connected to G, and the drain of M12 is connected to the source of M11;

[0021] The gate of M19 is connected to the gate of M20 and to the drains of M20 and M5. The source of M19 is connected to V, and the drain of M19 is connected to the source of M20. The gate of M20 is connected to the drain of M20, the source of M20 is connected to the drain of M19, and the drain of M20 is connected to the drain of M5. The gate of M21 is connected to the drains of M7 and M22. The source of M21 is connected to V, and the drain of M21 is connected to the source of M22. The gate of M22 is connected to the gate of M20, the source of M22 is connected to the drain of M21, and the drain of M22 is connected to the drain of M7 and to the gate of M21. M23's gate is connected to M21's gate, M23's source is connected to V, and M23's drain is connected to M24's source. M24's gate is connected to M20's gate, M24's source is connected to M23's drain, and M24's drain is connected to M29's source and then to the positive terminal of M41. M25's gate is connected to M21's gate, M25's source is connected to V, and M25's drain is connected to M26's source. M26's gate is connected to M20's gate, M26's source is connected to M25's drain, and M26's drain is connected to M30's source and then to the negative terminal of M41. M13's gate is connected to iu. <0> The source of M13 is connected to the drain of M14 and the gate of M29. The drain of M13 is connected to the drain of M28 and the gates of M27 and M31.

[0022] M14 gate connection iu <1> The source of M14 is connected to G, and the drain of M14 is connected to the source of M13 and then to the gate of M29. The gate of M15 is connected to the drain of M27 and then to the source of M28. The source of M15 is connected to the drain of M9 and then to the positive terminal of M42. The drain of M15 is connected to V. The gate of M16 is connected to the drain of M31 and then to the source of M32. The source of M16 is connected to the drain of M11 and then to the negative terminal of M42. The drain of M16 is connected to V. The gate of M17 is connected to the output of M41. The source of M17 is connected to the gate of M30 and then to the drain of M18. The drain of M17 is connected to the sources of M35, M36, M39, and M40. The gate of M18 is connected to iu. <1> The source of M18 is connected to G, the drain of M18 is connected to the source of M17 and then to the gate of M30; the gate of M27 is connected to the drain of M28 and then to the gate of M31, the source of M27 is connected to V, the drain of M27 is connected to the source of M28 and then to the gate of M15; the gate of M28 is connected to the gate of M19 and then to the drain of M20, the source of M28 is connected to the drain of M27 and then to the gate of M15, the drain of M28 is connected to the gates of M27 and M31; the gate of M29 is connected to the source of M13 and then to the drain of M14, the source of M29; the positive terminal of M41 is connected to the drain of M24, the drain of M29 is connected to G; the gate of M30 is connected to the source of M17 and then to the drain of M18, the source of M30 is connected to the drain of M26 and then to the negative terminal of M41, the drain of M30 is connected to G;

[0023] The gate of M31 is connected to the drains of M13 and M28 and then to the gate of M27. The source of M31 is connected to V. The drain of M31 is connected to the gate of M16 and then to the source of M32. The gate of M32 is connected to the output of M42. The source of M32 is connected to the gate of M16 and then to the drain of M31. The drain of M32 is connected to the sources of M33, M34, M37, and M38. The positive terminal of M41 is connected to the drain of M24 and then to the source of M29. The negative terminal of M41 is connected to the drain of M26 and then to the source of M30. The output of M41 is connected to the gate of M17. The positive terminal of M42 is connected to the drain of M9 and then to the source of M15. The negative terminal of M42 is connected to the drain of M11 and then to the source of M16. The output of M42 is connected to the gate of M32. Since the basic charge structure also has clock feedthrough, charge sharing, and leakage, this invention further uses a drain switch structure with operational amplifier buffer, which achieves a very small mismatch between the charging and discharging current sources. The specific implementation is as follows:

[0024] The gate of M33 is connected to UPB and then to the gate of M38. The source of M33 is connected to the sources of M34, M37, and M38 and then to the drain of M32. The drain of M33 is connected to the drains of M34, M35, and M36 and then to the negative terminal of M43 and the output.

[0025] The gate of M34 is connected to UP and then to the gate of M37. The source of M34 is connected to the sources of M33, M37, and M38 and then to the drain of M32. The drain of M34 is connected to the drains of M33, M35, and M36 and then to the negative terminal of M43 and the output.

[0026] The gate of M35 is connected to DNB and then to the gate of M40. The source of M35 is connected to the sources of M36, M39, and M40 and then to the drain of M17. The drain of M35 is connected to the drains of M33, M34, and M36 and then to the negative terminal of M43 and the output.

[0027] The gate of M36 is connected to DN and then to the gate of M39. The source of M36 is connected to the sources of M35, M39, and M40 and then to the drain of M17. The drain of M36 is connected to the drains of M33, M34, and M36 and then to the negative terminal of M43 and the output.

[0028] The gate of M37 is connected to UP and the gate of M34. The source of M37 is connected to the sources of M33, M34, and M38 and the drain of M32. The drain of M37 is connected to the drains of M38, M39, and M40 and the positive terminal of M43 and Iout.

[0029] The gate of M38 is connected to UPB and then to the gate of M33. The source of M38 is connected to the sources of M33, M34, and M37 and then to the drain of M32. The drain of M38 is connected to the drains of M37, M39, and M40 and then to the positive terminal of M43 and Iout.

[0030] The gate of M39 is connected to DN and then to the gate of M36. The source of M39 is connected to the sources of M35, M36, and M40 and then to the drain of M17. The drain of M39 is connected to the drains of M37, M38, and M40 and then to the positive terminal of M43 and Iout.

[0031] The gate of M40 is connected to DNB and then to the gate of M35. The source of M40 is connected to the sources of M35, M36, and M40 and then to the drain of M17. The drain of M40 is connected to the drains of M37, M38, and M39 and then to the positive terminal of M43 and Iout.

[0032] The positive terminal of M43 is connected to the drains of M37, M38, M39, and M40, and then connected to Iout. The negative terminal of M43 is connected to the output of M43 and then connected to the drains of M33, M34, M35, and M36. Based on the above scheme, the beneficial effects of the present invention are:

[0033] In the circuit structure designed in this invention, the current sources in the bias circuit and the core circuit adopt a common-source, common-gate structure, such as... Figure 1Numbers 1, 2, 3, and 4 in the diagram. This structure has a high output resistance, which inherently reduces current mismatch caused by manufacturing processes, power supply voltage fluctuations, and temperature changes. The bias circuit provides a current source and current reference for the SF, OP, and core circuits. In the core module, on the current transmission path ( Figure 1 In sections 3 and 4), the common-gate (CG) transistor, along with the five-transconductance operational amplifier (5OTA) and the source follower (SF), forms a current-voltage negative feedback loop, increasing the small-signal output resistance: Rout = A * gm * ro1 * ro2. Therefore, when the common-source transistor is used as a current source, the voltage change at the common-gate drain is reflected in the common-source drain by dividing by Rout. The source follower is responsible for detecting the drain voltage difference between the reference current source and the output current source, raising this voltage difference by a gate-source voltage value before applying it to the operational amplifier. Therefore, this operational amplifier can use a conventional, simple common-source common-gate current source load 5OTA. Due to the high gain of the operational amplifier, Figure 1 The common source drain voltages of 1 and 3 are approximately equal, resulting in a very small current mismatch. Detailed Implementation

[0034] This invention is illustrated using a design example:

[0035] In the Bias circuit shown in Figure 2, <iu0> ， <iu1>The current source provided for the reference circuit (in this example, an ideal current source is used instead of a reference source, and iu is made to...) <0> =iu <1> =5uA), and common-source (CS) and common-gate (CG) bias voltages are generated through diode-connected M1 and M4 respectively (as shown in Figure 2). M2 operates in the linear region and is equivalent to a resistor, while the CG stage increases the small-signal output impedance. The common-source (CS) and common-gate (CG) are connected in series as a mirror common-source and common-gate current source to complete the charging and discharging current bias of this circuit, as shown in Figures 2 and 3. The common-source of the current mirror can be replicated separately and used as a current source independently with proper drain connection.

[0036] M1 gate and drain connection iu <0> The source of M1 is connected to the drain of M2; the gate of M2 is connected to iu. <0> M2's source is connected to G, and M2's drain is connected to M1; M3's gate is connected to iu. <0> The source of M3 is connected to the drain of M4, and the drain of M3 is connected to iu. <1> M4 gate connection iu <0> M4's source is connected to G, and M4's drain is connected to M3's source; M5's gate is connected to iu. <0> The source of M5 is connected to the drain of M6, and the drain of M5 is connected to the gates of M19 and M20, and then connected to the drain of M20; the gate of M6 is connected to iu. <1> M6 source is connected to G, M6 drain is connected to M5 source; M7 gate is connected to iu. <0> The source of M7 is connected to the drain of M8, and the drain of M7 is connected to the gates of M21 and M20, and then connected to the drain of M20; the gate of M8 is connected to iu. <1> M8's source is connected to G, and M8's drain is connected to M7's source; M9's gate is connected to iu. <0> The source of M9 is connected to the drain of M10, and the drain of M9 is connected to the source of M15 and then to the positive terminal of M42; the gate of M10 is connected to iu. <1> M10 source is connected to G, M10 drain is connected to M9 source; M11 gate is connected to iu. <0> The source of M11 is connected to the drain of M12, and the drain of M11 is connected to the source of M16 and then to the negative terminal of M42.M12 gate connection iu <1> M12 source connected to G, M12 drain connected to M11 source; M19 gate connected to M20 gate and connected to M20 and M5 drain, M19 source connected to V, M19 drain connected to M20 source; M20 gate connected to M20 drain, M20 source connected to M19 drain, M20 drain connected to M5 drain; M21 gate connected to M7 and M22 drain, M21 source connected to V, M21 drain connected to M22 source; M22 gate connected to M20 gate, M22 source connected to M21 drain, M22 drain connected to M7 drain and connected to M21 gate; M23 gate connected to M21 gate, M23 source connected to V, M23 drain connected to M24 source; M24 gate connected to M20 gate, M24... The source of M24 is connected to the drain of M23, and the drain of M24 is connected to the source of M29 and then to the positive terminal of M41. The gate of M25 is connected to the gate of M21, the source of M25 is connected to V, and the drain of M25 is connected to the source of M26. The gate of M26 is connected to the gate of M20, the source of M26 is connected to the drain of M25, and the drain of M26 is connected to the source of M30 and then to the negative terminal of M41. The bias circuit provides a discharge reference current source for the core circuit (Figure 1, 1). The charging reference current source consists of a PMOS diode connected to a CG stage (biased by the bias voltage) (Figure 1, 2), i.e., Ip=In. In Figure 1, 4 replicates the current of 1, and 3 replicates the current of 2. Taking the discharge current source as an example, two identical PMOS source followers (P-SF) measure the drain voltage difference (nodes A and B) of the CS stage at points 1 and 4, respectively. This difference is amplified by an operational amplifier (5OTA) and fed back to the amplifier, thus forming a negative feedback loop. The charging current source works similarly, except that the SF is replaced with an NMOS type (N-SF), and the 5OTA is replaced with a combination of an NMOS input transistor and a PMOS common-gate current source load.

[0037] M13 gate connection iu <0> The source of M13 is connected to the drain of M14 and then to the gate of M29. The drain of M13 is connected to the drain of M28 and then to the gates of M27 and M31. The gate of M14 is connected to iu. <1> M14 source connected to G, M14 drain connected to M13 source and M29 gate; M15 gate connected to M27 drain and M28 source, M15 source connected to M9 drain and M42 positive terminal, M15 drain connected to V; M16 gate connected to M31 drain and M32 source, M16 source connected to M11 drain and M42 negative terminal, M16 drain connected to V; M17 gate connected to M41 output, M17 source connected to M30 gate and M18 drain; M17 drain connected to M35, M36, M39, and M40 sources; M18 gate connected to iu <1> M18 source connected to G, M18 drain connected to M17 source and M30 gate; M27 gate connected to M28 drain and M31 gate, M27 source connected to V, M27 drain connected to M28 source and M15 gate; M28 gate connected to M19 gate and M20 drain, M28 source connected to M27 drain and M15 gate, M28 drain connected to M27 and M31 gates; M29 gate connected to M13 source and M14 drain, M29 source M41 positive terminal connected to M24 drain, M29 drain connected to G; M30 gate connected to M17 source and M18 drain, M30 source connected to M26 drain and M41 negative terminal, M30... Drain connected to G; Gate of M31 connected to drains of M13 and M28 and gate of M27; Source of M31 connected to V; Drain of M31 connected to gate of M16 and source of M32; Gate of M32 connected to output of M42; Source of M32 connected to gate of M16 and drain of M31; Drain of M32 connected to sources of M33, M34, M37, and M38; Positive terminal of M41 connected to drain of M24 and source of M29; Negative terminal of M41 connected to drain of M26 and source of M30; Output of M41 connected to gate of M17; Positive terminal of M42 connected to drain of M9 and source of M15; Negative terminal of M42 connected to drain of M11 and source of M16; Output of M42 connected to gate of M32; 5-OTA1: NMOS: M44, M45, M46 PMOS: M47, M48, M49, M50; M44 gate is connected to M21 gate, M44 source is connected to V, and M44 drain is connected to M45 and M46 source.M45 gate is connected to V+, M45 source is connected to M44 drain and then to M46 source, M45 drain is connected to M47 drain and then to gates M49 and M50; M46 gate is connected to V-, M46 source is connected to M44 drain and then to M45 source, M46 drain is connected to M48 drain and then to Vout1; M47 gate is connected to iu <0> The source of M47 is connected to the drain of M49, the drain of M47 is connected to the drain of M45 and then to the gates of M49 and M50; the gate of M48 is connected to iu. <0> M48 source connected to M50 drain, M48 drain connected to Vout1; M49 gate connected to M45 drain, M49 source connected to G, M49 drain connected to M47 source; M50 gate connected to M45 drain, M50 source connected to G, M50 drain connected to M48 source; 5-OTA2: NMOS: M51, M52, M53; PMOS: M54, M55, M56, M57; M51 gate connected to iu <1> M51 source connected to G, M51 drain connected to the sources of M52 and M53; M52 gate connected to V+, M52 source connected to the drain of M51 and then to the source of M53, M52 drain connected to the drain of M54 and then to the gates of M56 and M57; M53 gate connected to V-, M53 source connected to the drain of M51 and then to the source of M52, M53 drain connected to the drain of M55 and then to Vout1; M54 gate connected to the gate of M20, M54 source connected to the drain of M56, M54 drain connected to the drain of M53 and then to the gates of M56 and M57; M55 gate connected to the gate of M20, M55 source connected to the drain of M57, M55 drain connected to Vout1; M56 gate connected to the drain of M52, M56... The source of M56 is connected to V, and the drain of M56 is connected to the source of M54. The gate of M57 is connected to the drain of M52, the source of M57 is connected to V, and the drain of M57 is connected to the source of M55. Four sets of switches control the direction of the charge pump via external timing signals, where UPB is the inverted UP signal and DNB is the inverted DN signal. When UP and DN are both high, switches 1 and 2 are both on, allowing a small current to flow in or out. When UP and DN are both low (i.e., when UPB and DNB are both high), switches 3 and 4 are both on, allowing a small current to flow in or out. When UP is high and DN is low, switch 1 is on, charging the signal; switch 2 is off; switch 3 is off; switch 4 is on, and the current flows into V via the operational amplifier.When UP is low and DN is high, switch 2 is on to discharge charge, switch 1 is off, switch 4 is off, and switch 3 is on. Current is introduced into G through the operational amplifier. The issue of charge sharing between switches is resolved by voltage clamping via M43.

[0038] M58's gate is connected to M21's gate, M58's source is connected to V, and M58's drain is connected to the sources of M59 and M60; M59's gate is connected to V+, M59's source is connected to M58's drain and then to M60's source, and M59's drain is connected to M66 and M67's gates and then to M64's drain; M60's gate is connected to V-, M60's source is connected to M58's drain, and M60's drain is connected to Vout; M61's gate is connected to V+, and M61's source is connected to M63's drain and then...

[0039] The source of M62 and the drain of M61 are connected to the gates of M64 and M65, and then to the drain of M64; the gate of M62 is connected to V-, the source of M62 is connected to the drain of M63, and the drain of M62 is connected to Vout; the gate of M63 is connected to iu. <1> M63 source is connected to G, M63 drain is connected to the sources of M61 and M62f; M64 gate is connected to the drain of M61, M64 source is connected to V, M64 drain is connected to the drain of M61; M65 gate is connected to the drain of M61, M65 source is connected to V, M65 drain is connected to Vout; M66 gate is connected to the drain of M59, M66 source is connected to G, M66 drain is connected to the drain of M59; M67 gate is connected to the drain of M59, M67 source is connected to G, M67 drain is connected to Vout; The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless specifically stated otherwise, may be replaced by other equivalent or similar features; all disclosed features, or steps in all methods or processes, except for mutually exclusive features and / or steps, may be combined in any way. < / iu0>

Claims

1. A charge pump circuit with low current mismatch applied to a phase-locked loop, comprising a current bias section and a core section, wherein the current bias section provides a reference current and a bias voltage, and the core section includes a switching transistor, a current source, and an operational amplifier and is used to implement charging and discharging functions, characterized in that, The circuit clamps the common-source drain voltage of the cascode current mirror through a negative feedback loop consisting of a source follower, an operational amplifier, and a current buffer, and suppresses the current source drain voltage change caused by the common-gate drain voltage change of the cascode current mirror, thereby achieving low current mismatch. The source follower includes NMOS transistors M15 and M16 and PMOS transistors M29 and M30, the operational amplifier includes M41 and M42, and the current buffer includes NMOS transistor M17 and PMOS transistor M32.

2. The charge pump circuit according to claim 1, characterized in that, The core component includes: NMOS transistors: M13~M18, M33, M35, M37, M39; PMOS transistors: M27~M32, M34, M36, M38, M40; The input pair is a five-transistor transconductance amplifier (5OTA) M42 with NMOS transistors; The input pair is a five-transistor transconductance amplifier (5OTA) M41 with PMOS transistors; Rail-to-rail operational amplifier M43; Among them, the gate of M13 is connected to the current input iu <0> The source of M13 is connected to the drain of M14 and then to the gate of M29. The drain of M13 is connected to the drain of M28 and then to the gates of M27 and M31. The gate of M14 is connected to the current input iu. <1> M14 source is connected to ground (G), M14 drain is connected to M13 source and M29 gate; M15 gate is connected to M27 drain and M28 source, M15 source is connected to M9 drain and M42 positive terminal, M15 drain is connected to power supply voltage (V); M16 gate is connected to M31 drain and M32 source, M16 source is connected to M11 drain and M42 negative terminal, M16 drain is connected to power supply voltage (V); M17 gate is connected to M41 output, M17 source is connected to M30 gate and M18 drain; M18 gate is connected to current input iu <1> M18 source connected to ground (G), M18 drain connected to M17 source and M30 gate; M27 gate connected to M28 drain and M31 gate, M27 source connected to power supply voltage (V), M27 drain connected to M28 source and M15 gate; M28 gate connected to M19 gate and M20 drain, M28 source connected to M27 drain and M15 gate, M28 drain connected to M27 and M31 gates; M29 gate connected to M13 source and M14 drain, M29 source connected to the positive terminal of M41 and M24 drain, M29 drain connected to ground (G); M30 gate connected to M17 source and M18 drain, M30 source connected to M26 drain and M41 negative terminal, M30... Drain connected to ground (G); Gate of M31 connected to drains of M13 and M28 and gate of M27; Source of M31 connected to power supply voltage (V); Drain of M31 connected to gate of M16 and source of M32; Gate of M32 connected to output of M42; Source of M32 connected to gate of M16 and drain of M31; Drain of M32 connected to sources of M33, M34, M37, and M38; Gate of M33 connected to control signal UPB and gate of M38; Source of M33 connected to sources of M34, M37, and M38 and drain of M32; Drain of M33 connected to drains of M34, M35, and M36 and negative terminal and output of M43; Gate of M34 connected to control signal UP and gate of M37; Source of M34 connected to M33, M37, and M38. The source is connected to the drain of M32, and the drain of M34 is connected to the drains of M33, M35, and M36, and then connected to the negative terminal and output of M43.M35's gate is connected to the control signal DNB and then to the gate of M40. M35's source is connected to the sources of M36, M39, and M40, and then to the drain of M17. M35's drain is connected to the drains of M33, M34, and M36, and then to the negative terminal of M43 and the output. M36's gate is connected to the control signal DN and then to the gate of M39. M36's source is connected to the sources of M35, M39, and M40, and then to the drain of M17. M36's drain is connected to the drains of M33, M34, and M36, and then to the negative terminal of M43 and the output. M37's gate is connected to the control signal UP and then to the gate of M34. M37's source is connected to the sources of M33, M34, and M38, and then to the drain of M32. M37's drain is connected to the drains of M38, M39, and M40, and then to the positive terminal of M43 and the output current Iout. M38... The gate of M38 is connected to the control signal UPB and then to the gate of M33. The source of M38 is connected to the sources of M33, M34, and M37 and then to the drain of M32. The drain of M38 is connected to the drains of M37, M39, and M40 and then to the positive terminal of M43 and the output current Iout. The gate of M39 is connected to the control signal DN and then to the gate of M36. The source of M39 is connected to the sources of M35, M36, and M40 and then to the drain of M17. The drain of M39 is connected to the drains of M37, M38, and M40 and then to the positive terminal of M43 and the output current Iout. The gate of M40 is connected to the control signal DNB and then to the gate of M35. The source of M40 is connected to the sources of M35, M36, and M40 and then to the drain of M17. The drain of M40 is connected to the drains of M37, M38, and M39 and then to M43. The positive terminal of M41 is connected to the drain of M24 and the source of M29; the negative terminal of M41 is connected to the drain of M26 and the source of M30; the output of M41 is connected to the gate of M17. The positive terminal of M42 is connected to the drain of M9 and the source of M15; the negative terminal of M42 is connected to the drain of M11 and the source of M16; the output of M42 is connected to the gate of M32. The positive terminal of M43 is connected to the drains of M37, M38, M39, and M40 and the output current Iout; the negative terminal of M43 is connected to the output of M43 and the drains of M33, M34, M35, and M36.

3. The charge pump circuit according to claim 1, characterized in that, The current biasing portion includes: NMOS transistors: M1~M12; PMOS transistors: M19~M26; where the gate and drain of M1 are connected to the current input iu. <0> The source of M1 is connected to the drain of M2; the gate of M2 is connected to the current input iu. <0> The source of M2 is connected to ground (G), and the drain of M2 is connected to M1; the gate of M3 is connected to the current input iu. <0> The source of M3 is connected to the drain of M4, and the drain of M3 is connected to the current input iu. <1> M4 gate connection current input iu <0> The source of M4 is connected to ground (G), and the drain of M4 is connected to the source of M3; the gate of M5 is connected to the current input iu. <0> The source of M5 is connected to the drain of M6, and the drain of M5 is connected to the gates of M19 and M20, and then connected to the drain of M20; the gate of M6 is connected to the current input iu. <1> The source of M6 is connected to ground (G), and the drain of M6 is connected to the source of M5; the gate of M7 is connected to the current input iu. <0> The source of M7 is connected to the drain of M8, and the drain of M7 is connected to the gates of M21 and M20, and then to the drain of M20; the gate of M8 is connected to the current input iu. <1> M8 source is connected to ground (G).

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