Series ceramic capacitor chip and ceramic capacitor

Abstract

The utility model discloses a series ceramic capacitor chip and a ceramic capacitor, comprising two cylindrical ceramic substrates distributed at an interval, the two ceramic substrates are respectively provided with a first surface and a second surface which are oppositely arranged in parallel, and a connecting bridge is arranged between the first surfaces of the two ceramic substrates. The two ceramic matrixes and the connecting bridge are connected into a whole through one-time pressing and sintering of ceramic materials, the upper surface of the connecting bridge and the first surfaces of the two ceramic matrixes are located on the same plane, the first surface and the second surface are covered with a first electrode layer and a second electrode layer respectively, the upper surface of the connecting bridge is covered with a third electrode layer, and the third electrode layer is covered with a second electrode layer. And the third electrode layer and the first electrode layers on the two ceramic substrates are integrally connected by electrode slurry through one-time printing, baking and sintering. The two ceramic substrates are integrally formed and connected by adopting the connecting bridge, so that the two ceramic capacitor chips are kept at a stable distance, and the stability and the consistency of the performance of the series ceramic capacitor are improved.

Description

Technical Field

[0001] This utility model relates to the field of capacitor technology, specifically to a series ceramic capacitor chip and a ceramic capacitor. Background Technology

[0002] Ceramic capacitors, as basic passive components, are widely used in power supplies, home appliances, automobiles, and other equipment, serving functions such as filtering, oscillation, and coupling. Two key performance indicators in capacitor specifications are capacitance and voltage withstand capability. When using a capacitor, the voltage applied across its terminals must be less than its voltage withstand value; otherwise, the capacitor will break down.

[0003] To improve the voltage withstand capability of capacitors, a structure of multiple capacitors connected in series is required. Existing series ceramic capacitors mainly use wire bonding to form a series structure of two independent ceramic capacitor chips. This method increases the production process and is prone to phenomena such as cold solder joints and false solder joints. It can also cause the pad layer of the ceramic capacitor to deform due to heat, affecting the performance of the capacitor. Chinese utility model patent with authorization announcement number CN213845051U discloses a single-layer series ceramic capacitor chip, which forms two series ceramic capacitors without the need for wire bonding by setting a second electrode and a fourth electrode connected as one electrode on the same surface of a single-layer ceramic substrate. However, since they share the same single-layer ceramic substrate, the separation between the two capacitors is not obvious, the electric field distribution is unstable, and the actual working performance of the capacitor is affected. Utility Model Content

[0004] This invention addresses the shortcomings of existing technologies by providing a series ceramic capacitor chip and a ceramic capacitor, which can improve the production efficiency of series ceramic capacitor chips, enhance the stability of the electric field distribution in series ceramic capacitors, and improve the actual working performance of series ceramic capacitors.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A series-connected ceramic capacitor chip includes two spaced-apart cylindrical ceramic substrates. Each substrate has a first surface and a second surface arranged parallel to each other. A connecting bridge is provided between the first surfaces of the two substrates. The two ceramic substrates and the connecting bridge are integrally formed by pressing and sintering ceramic material in a single process. The upper surface of the connecting bridge is on the same plane as the first surfaces of the two ceramic substrates. The first and second surfaces are respectively covered with a first electrode layer and a second electrode layer. The upper surface of the connecting bridge is covered with a third electrode layer. The third electrode layer and the first electrode layers on the two ceramic substrates are integrally connected by electrode paste through a single printing, baking, and sintering process. By using a connecting bridge to integrally connect the two ceramic substrates, the thickness of the two ceramic substrates is ensured to maintain a consistent thickness, and the two series-connected ceramic capacitor chips maintain a stable spacing, avoiding performance changes caused by spacing variations, thus improving the stability and consistency of the series-connected ceramic capacitor performance. Simultaneously, the two ceramic capacitor chips formed in this way still maintain independence, avoiding the influence of other dielectric materials connecting the two ceramic substrates on the capacitance performance, resulting in a more stable electric field distribution during operation and improving the reliability of the series-connected ceramic capacitor.

[0007] As a preferred technical solution, the center-to-center distance between the two ceramic substrates is greater than the sum of the radii of the two ceramic substrates.

[0008] As a preferred technical solution, the second surfaces of the two ceramic substrates are on the same plane.

[0009] As a preferred technical solution, the two ceramic substrates have the same thickness, which is 0.5 to 5 mm.

[0010] As a preferred technical solution, the thickness of the connecting bridge is 0.3 to 1 times the thickness of the ceramic substrate.

[0011] As a preferred technical solution, the width of the connecting bridge is 0.3 to 0.8 times the diameter of the ceramic substrate.

[0012] As a preferred technical solution, the connecting bridge is located at the center line connecting the first surfaces of the two ceramic substrates.

[0013] As a preferred technical solution, the connection between the connecting bridge and the ceramic substrate, and the connection between the third electrode layer and the first electrode layer, are formed with arc-shaped chamfers.

[0014] This utility model also provides a capacitor, including an insulating enclosure, in which the aforementioned series ceramic capacitor chip is encapsulated. The second electrode layer of the series ceramic capacitor chip is welded with leads, and a portion of the leads is exposed on the outer surface of the insulating enclosure.

[0015] As a preferred technical solution, the pin is Z-shaped, and the pin has a welded end that is welded to the second electrode layer and an exposed end that extends out of the insulating enclosure.

[0016] Compared with existing technologies, this invention has significant advantages and beneficial effects. Specifically, by using a connecting bridge to integrally connect two ceramic substrates, the two series-connected ceramic capacitor chips maintain a stable spacing, avoiding performance changes caused by spacing variations and improving the stability and consistency of the series-connected ceramic capacitor performance. Simultaneously, the two capacitors formed in this way still maintain their independence, resulting in more stable electrical performance and electric field distribution. Furthermore, the first electrode layers of the two ceramic substrates are integrally connected through a third electrode layer, eliminating the need for wire bonding, improving production efficiency, and avoiding poor contact caused by incomplete soldering or false soldering, thus enhancing the stability and reliability of the series-connected ceramic capacitor operation.

[0017] To more clearly illustrate the structural features, technical means, and specific objectives and functions achieved by this utility model, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments: Attached Figure Description

[0018] Figure 1 This is a first-view assembly structure diagram of the series ceramic capacitor chip of this utility model;

[0019] Figure 2 This is a second-view assembly structure diagram of the series ceramic capacitor chip of this utility model;

[0020] Figure 3 This is a schematic diagram of the cross-sectional structure of the series ceramic capacitor chip of this utility model;

[0021] Figure 4 This is a schematic diagram of the cross-sectional structure of the ceramic capacitor of this utility model.

[0022] Explanation of reference numerals in the attached diagram:

[0023] 10. Ceramic substrate; 11. First electrode layer; 12. Second electrode layer

[0024] 20. Connecting bridge; 21. Third electrode layer; 30. Insulating encapsulation.

[0025] 40. Pin. Detailed Implementation

[0026] In the description of this utility model, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the position or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0027] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0028] like Figure 1-3 As shown, a series ceramic capacitor chip of this utility model includes two cylindrical ceramic substrates 10 spaced apart. Each of the two ceramic substrates 10 has a first surface and a second surface arranged relatively parallel to each other. A connecting bridge 20 is provided between the first surfaces of the two ceramic substrates 10. The two ceramic substrates 10 and the connecting bridge 20 are integrally connected by pressing and sintering ceramic material in one step. The upper surface of the connecting bridge 20 is on the same plane as the first surface of the two ceramic substrates 10. The second surfaces of the two ceramic substrates 10 are on the same plane. The first surface and the second surface are respectively covered with a first electrode layer 11 and a second electrode layer 12. The upper surface of the connecting bridge 20 is covered with a third electrode layer 21. The third electrode layer 21 and the first electrode layer 11 on the two ceramic substrates 10 are integrally connected by electrode paste through one-time printing, baking and sintering. By using a connecting bridge 20 to integrally connect the two ceramic substrates 10, the two series-connected ceramic capacitor chips maintain a stable spacing, avoiding performance changes caused by spacing variations and improving the stability and consistency of the series-connected ceramic capacitor performance. Simultaneously, the two capacitors formed in this way retain their independence, resulting in a more stable electric field distribution. It should be noted that the pressing and sintering processes used in the forming of the two ceramic substrates 10 and the connecting bridge 20 are mature existing processes readily conceived by those skilled in the art. Similarly, the printing, baking, and sintering processes used in the forming of the first electrode layer 11, the second electrode layer 12, and the third electrode layer 21 are also mature processes readily conceived by those skilled in the art, and will not be elaborated upon here.

[0029] In this invention, the center-to-center distance between the two ceramic substrates 10 is greater than the sum of their radii. The two ceramic substrates 10 have the same thickness, ranging from 0.5 to 5 mm. The thickness of the connecting bridge 20 is 0.3 to 1 times the thickness of the ceramic substrate, and the width of the connecting bridge 20 is 0.3 to 0.8 times the diameter of the ceramic substrate 10. The connecting bridge 20 is located at the line connecting the centers of the first surfaces of the two ceramic substrates 10. To avoid tip discharge and improve the stability of the electric field distribution, the connection points between the connecting bridge 20 and the ceramic substrate 10, and between the third electrode layer 21 and the first electrode layer 11, are formed with arc-shaped chamfers.

[0030] like Figure 4 As shown, this utility model also provides a ceramic capacitor, including an insulating enclosure 30, in which the aforementioned series-connected ceramic capacitor chip is encapsulated. The second electrode layer 12 of the series-connected ceramic capacitor chip has leads 40 welded to it, with portions of the leads 40 exposed on the outer surface of the insulating enclosure 30. Specifically, the leads 40 are Z-shaped, having a welded end connected to the second electrode layer 12 and an exposed end extending outside the insulating enclosure 30.

[0031] In summary, this invention uses a connecting bridge to integrally connect two ceramic substrates, thereby maintaining a stable spacing between the two series-connected ceramic capacitor chips. This avoids performance changes caused by spacing variations, improving the stability and consistency of the series-connected ceramic capacitor's performance. Simultaneously, the two capacitors remain independent, preventing the connection between the two ceramic substrates through other dielectrics from affecting capacitor performance. This results in a more stable electric field distribution during operation, improving the reliability of the series-connected ceramic capacitor's electrical performance. Furthermore, the first electrode layers of the two ceramic substrates are integrally connected via a third electrode layer, eliminating the need for wire bonding, improving production efficiency, and avoiding poor contact caused by incomplete or false soldering, thus enhancing the operational stability of the series-connected ceramic capacitor.

[0032] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model. Therefore, any modifications, equivalent substitutions, improvements, etc., made to the above embodiments based on the actual technical aspects of the present utility model shall still fall within the scope of the technical solution of the present utility model.

Claims

1. A series-connected ceramic capacitor chip, characterized in that, The device comprises two cylindrical ceramic substrates spaced apart. Each ceramic substrate has a first surface and a second surface arranged in parallel. A connecting bridge is provided between the first surfaces of the two ceramic substrates. The two ceramic substrates and the connecting bridge are integrally formed by pressing and sintering ceramic material in one step. The upper surface of the connecting bridge is on the same plane as the first surface of the two ceramic substrates. The first surface and the second surface are respectively covered with a first electrode layer and a second electrode layer. The upper surface of the connecting bridge is covered with a third electrode layer. The third electrode layer and the first electrode layer on the two ceramic substrates are integrally connected by electrode paste through one-step printing, baking, and sintering.

2. The series ceramic capacitor chip according to claim 1, characterized in that, The center-to-center distance between the two ceramic substrates is greater than the sum of the radii of the two ceramic substrates.

3. A series ceramic capacitor chip according to claim 1, characterized in that, The second surfaces of the two ceramic substrates are in the same plane.

4. A series ceramic capacitor chip according to claim 1, characterized in that, The two ceramic substrates have the same thickness, which is 0.5 to 5 mm.

5. A series ceramic capacitor chip according to claim 4, characterized in that, The thickness of the connecting bridge is 0.3 to 1 times the thickness of the ceramic substrate.

6. A series ceramic capacitor chip according to claim 1, characterized in that, The width of the connecting bridge is 0.3 to 0.8 times the diameter of the ceramic substrate.

7. A series ceramic capacitor chip according to claim 1, characterized in that, The connecting bridge is located at the center line connecting the first surfaces of the two ceramic substrates.

8. A series ceramic capacitor chip according to claim 1, characterized in that, The connection between the connecting bridge and the ceramic substrate, as well as the connection between the third electrode layer and the first electrode layer, are formed with arc-shaped chamfers.

9. A ceramic capacitor, characterized in that, The device includes an insulating enclosure containing a series ceramic capacitor chip as described in any one of claims 1-8, wherein the second electrode layer of the series ceramic capacitor chip is welded with leads, and a portion of the leads is exposed on the outer surface of the insulating enclosure.

10. A ceramic capacitor according to claim 9, characterized in that, The pin is Z-shaped and has a welded end that is welded to the second electrode layer and an exposed end that extends out of the insulating enclosure.

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