Read assist circuit, memory, and electronic device
By using voltage selectors and switching units in SRAM to provide asymmetrical drive voltages for the bit lines and reverse bit lines, and combining this with coupling capacitor branches to reduce the ground terminal voltage, the problem of insufficient SRAM read capability is solved, read stability and accuracy are improved, and power consumption is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2025-05-20
- Publication Date
- 2026-05-26
AI Technical Summary
During SRAM manufacturing, due to process deviations and feature size miniaturization, the read and write capabilities of memory cells are insufficient. Traditional read auxiliary circuits cannot effectively improve the bit line voltage difference when faced with abnormal MOS transistor operating conditions, leading to read errors.
An auxiliary reading circuit is employed, which provides asymmetrical drive voltages to the bit line and reverse bit line through a voltage selector and a switching unit, and reduces the ground terminal voltage by combining a coupling capacitor branch, thereby enhancing the driving capability of the pull-down transistor and improving the reading current and bit line voltage difference.
It improves the stability and data accuracy of the SRAM read process, reduces power consumption, and enhances the performance of memory and electronic devices.
Smart Images
Figure CN224287784U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory technology, and in particular to a read-aid circuit, a memory, and an electronic device. Background Technology
[0002] Static RAM (SRAM) has become an indispensable storage solution in modern large-scale integrated circuits due to its advantages such as high-speed access performance, process compatibility, and design maturity. However, in the SRAM manufacturing process, due to process variation and feature size miniaturization, memory cells generally suffer from insufficient read and write operation capabilities.
[0003] To ensure correct SRAM read operations, related technologies often employ auxiliary circuits such as word line underdrive (WLUD), power supply voltage boosting (Vcs Boosting), and suppressed bitline (SBL) to improve SRAM read capabilities.
[0004] However, for abnormal MOSFET operating states caused by factors such as process disturbances, traditional read auxiliary circuit adjustment mechanisms are simplistic. The voltage drop setting of WLUD exacerbates the on-resistance of the PG transistor; while the bit line voltage suppression of SBL amplifies the RC delay characteristics of the access path, causing the read current I... read If the voltage difference is too small, the bit line voltage difference cannot reach the trigger threshold of the sensitive amplifier within the predetermined timing window, ultimately resulting in a read error. Utility Model Content
[0005] Therefore, it is necessary to provide a read auxiliary circuit, memory, or electronic device that can at least increase the bit line voltage difference and improve the stability of the SRAM read process when the threshold of the MOS transistor increases due to factors such as process disturbances.
[0006] To address the aforementioned technical problems and other issues, according to some embodiments, one aspect of this application provides a readout auxiliary circuit applied to a sensitive amplifier, comprising:
[0007] A voltage selector is configured such that its input is connected to a first drive signal and its output is used to provide different drive voltages to the bit line and the inverted bit line connected to the sensitive amplifier.
[0008] First switching unit;
[0009] The second switching unit is connected to the first switching unit;
[0010] The driver is configured such that a first input terminal is connected to the output terminal of a voltage selector via a first switching unit, and a second input terminal is connected to the output terminal of a voltage selector via a second switching unit.
[0011] The first switching unit is used to transmit the driving voltage on the bit line to the first input terminal of the driver when the second driving signal is received; the second switching unit is used to transmit the driving voltage on the reverse bit line to the second input terminal of the driver when the third driving signal is received.
[0012] In the read auxiliary circuit of the above embodiment, the voltage gating module connects the bit line and the reverse bit line, and provides asymmetrical drive voltages to the bit line and the reverse bit line in conjunction with the first switching unit and the second switching unit. Upon receiving the first drive signal, the first switching unit applies a drive voltage to the target bit line, while the second switching unit maintains the other bit line at a standard pre-charge level. This establishes a gradient voltage difference between the bit line and the reverse bit line, making it easier for the driver to detect the potential difference, thereby ensuring the accuracy and stability of the read data. Compared to SBL, the bit line pre-discharge-recharge cycle is avoided, significantly reducing power consumption.
[0013] In some embodiments, the reading auxiliary circuit further includes:
[0014] The capacitor branch is configured such that its input receives the fourth drive signal, and its output is grounded and connected to the ground terminal of the sensitive amplifier to reduce the potential of the ground terminal.
[0015] In the readout auxiliary circuit of the above embodiment, the principle that the potential difference between the two ends of the coupling capacitor branch does not change abruptly is utilized. When the fourth drive signal is received, a negative voltage is generated at the ground terminal of the sensitive amplifier, thereby reducing the voltage at the ground terminal (common source terminal of the pull-down transistor), increasing the gate-source voltage of the pull-down transistor, and thus strengthening its driving capability and increasing the readout current.
[0016] In some embodiments, the voltage gate includes:
[0017] The first selection transistor is configured such that: its first terminal is connected to a first voltage, its gate-controlled terminal forms the input terminal of a voltage selector and is connected to a first driving signal, and its second terminal forms the output terminal of a voltage selector and is connected to a bit line and an inverted bit line, and is used to be in the conducting state when the first driving signal is the first electrical signal;
[0018] The second gating transistor is configured such that: its first terminal is connected to the second voltage, its gate control terminal is connected to the gate control terminal of the first gating transistor, and its second terminal is connected to the second terminal of the first gating transistor, and is used to be in the on state when the first driving signal is the second electrical signal.
[0019] In the voltage selector of the above embodiment, the first selector transistor and the second selector transistor share the same drive signal and have complementary operating states (one is on while the other is off). The coordinated operation of the dual selector transistors can avoid unnecessary voltage fluctuations or current paths.
[0020] In some embodiments, the first switching unit is configured such that: a first terminal is connected to a second driving signal, a second terminal is connected to the output terminal and bit line of a voltage selector, a third terminal is connected to the first input terminal of a driver, and a fourth terminal is connected to a third driving signal;
[0021] The second switching unit is configured such that: the first terminal is connected to the fourth terminal of the first switching unit, the second terminal is connected to the output terminal and the inverting bit line of the voltage selector, the third terminal is connected to the second input terminal of the driver, and the fourth terminal is connected to the first terminal of the first switching unit.
[0022] In some embodiments, the first switching unit includes:
[0023] The third gating transistor is configured such that: the gate-controlled terminal forms the first terminal of the first switching unit, the first terminal forms the second terminal of the first switching unit and is connected to the output terminal and bit line of the voltage selector, and the second terminal forms the third terminal of the first switching unit and is connected to the first input terminal of the driver, and is used to be in the conducting state when receiving the second driving signal;
[0024] The fourth gating transistor is configured such that its gate-controlled terminal forms the fourth terminal of the first switching unit, its first terminal is connected to the first terminal of the third gating transistor, and its second terminal is connected to the second terminal of the third gating transistor, and is used to be in the off state when receiving the third driving signal.
[0025] In some embodiments, the second switching unit includes:
[0026] The fifth selector transistor is configured such that: the gate-controlled terminal forms the first terminal of the second switching unit and is connected to the fourth terminal of the first switching unit; the first terminal forms the second terminal of the second switching unit and is connected to the output terminal of the voltage selector and the inverted bit line; and the second terminal forms the third terminal of the second switching unit and is connected to the second input terminal of the driver, and is used to be in the on state when receiving the third drive signal.
[0027] The sixth gating transistor is configured such that its gate-controlled terminal forms the fourth terminal of the second switching unit and is connected to the first terminal of the first switching unit, its first terminal is connected to the first terminal of the fifth gating transistor, and its second terminal is connected to the second terminal of the fifth gating transistor, and is used to be in the off state when receiving the second drive signal.
[0028] In the first switching unit and the second switching unit of the above embodiments, the structures of the first switching unit and the second switching unit are symmetrical. By controlling the switching of the third and fourth gate transistors, the fifth and sixth gate transistors, the bit line and the reverse bit line are complementaryly controlled to ensure the unit line is loaded with voltage.
[0029] In some embodiments, the first gating transistor, the third gating transistor, and the fifth gating transistor are NMOS transistors;
[0030] The second, fourth, and sixth gate transistors are PMOS transistors.
[0031] In the above embodiments, the conduction conditions of the selector transistors are complementary, which can form complementary drive paths, simplify the control logic, and reduce wiring complexity and signal delay.
[0032] In some embodiments, the reading auxiliary circuit includes a signal generator configured to have a first output terminal connected to the input terminal of a voltage selector, a second output terminal connected to a capacitor branch, a third output terminal connected to a first terminal of a first switching unit and a fourth terminal of a second switching unit, and a fourth output terminal connected to a fourth terminal of the first switching unit and a first terminal of the second switching unit, for providing a drive signal.
[0033] Another aspect of this application provides a memory, including: a memory array comprising a plurality of memory cells arranged in multiple rows and columns;
[0034] Several bit lines, each of which is electrically connected to a memory cell located in the same column;
[0035] Several sensitive amplifiers are connected one-to-one with each bit line;
[0036] Several readout auxiliary circuits as described in any of the above embodiments are connected one-to-one with the sensitive amplifier and each bit line.
[0037] Another aspect of this application provides an electronic device, including a read-aid circuit as in any of the above embodiments; or a memory as in the above embodiments.
[0038] The reading auxiliary circuit, memory, and electronic device provided in this application have the following unexpected technical effects:
[0039] In the read auxiliary circuit, the voltage selector, the first switching unit, and the second switching unit each include two selection transistors with opposite conduction channel types, forming a complementary dual-selection structure. This effectively reduces voltage fluctuations and achieves complementary control of the bit line and the reverse bit line. By designing the circuit to increase the gate voltage of the SRAM pull-down transistor, the driving capability of the SRAM pull-down transistor is improved, the beta ratio is increased, and the write static noise margin is enhanced. Furthermore, by pulling up the voltage of the bit line or the reverse bit line, a larger voltage margin is ensured, thereby effectively improving the accuracy and stability of data during the read process while reducing the power consumption of the read auxiliary circuit.
[0040] In addition, when the threshold voltage of the MOSFET increases due to factors such as process disturbances, the read auxiliary circuit provided in this application can improve the stability of the SRAM read process by benefiting from the higher read current and bit line voltage difference, ensuring the amplification efficiency of the sensitive amplifier and the accuracy of the read data, thereby significantly improving the performance of the memory and its electronic devices. Attached Figure Description
[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.
[0042] Figure 1 This is a schematic diagram of the circuit principle of a 6T structure sensitive amplifier in one embodiment;
[0043] Figure 2 This is one of the structural block diagrams of the reading auxiliary circuit provided in one embodiment of this application;
[0044] Figure 3 This is a second structural block diagram of the reading auxiliary circuit provided in one embodiment of this application;
[0045] Figure 4 This is a schematic diagram of the circuit principle of a voltage selector provided in one embodiment of this application;
[0046] Figure 5 This is a schematic diagram of the circuit principle of the first switching unit and the second switching unit provided in one embodiment of this application;
[0047] Figure 6 This is a schematic diagram comparing the bit line voltage difference before and after using the reading auxiliary circuit provided in this application;
[0048] Figure 7 This is a schematic diagram of the reading auxiliary circuit and the sensitive amplifier provided in one embodiment of this application.
[0049] Explanation of reference numerals in the attached figures:
[0050] 10. Voltage selector; 11. First selector transistor; 12. Second selector transistor; 20. Capacitor branch; 21. Capacitor; 30. First switching unit; 31. Third selector transistor; 32. Fourth selector transistor; 40. Second switching unit; 41. Fifth selector transistor; 42. Sixth selector transistor; 50. Driver; 60. Sensitive amplifier. Detailed Implementation
[0051] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.
[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0053] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.
[0054] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0055] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or the internal connection of two components or the interaction between two components. For those skilled in the art, if the connected circuits, modules, units, etc., transmit electrical signals or data to each other, they should be understood as "electrical connection," "communication connection," etc.
[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0057] Figure 1 This is a circuit diagram of a 6T sensitive amplifier. The 6T sensitive amplifier includes six transistors. Pull-down transistors (PD) PD1 and PD2 are cross-coupled with pull-up transistors (PU) PU1 and PU2 to form a latch structure, which latches data at the internal storage nodes SNL and SNR of the sensitive amplifier. Pass gate transistors (PG) PG1 and PG2 have their gates connected to the word line WL, and their sources and drains are connected to the bit line BL and the internal storage node, respectively, for reading and writing data.
[0058] When a memory cell performs a read operation, the word line WL voltage is high, and the transmission transistor transmits the data of the internal memory node to the bit line BL (or BLB). The output signal on the bit line is then amplified by a differential amplifier, and different data information is output depending on the direction of the current.
[0059] When process disturbances cause a significant increase in the MOSFET threshold voltage (Vth), the conventional WLUD circuit will further weaken the gate-source drive voltage (VGS) of the PG transistor, resulting in a decrease in the read current (I). read The decrease in ) ultimately leads to data reading errors.
[0060] Based on this, please refer to Figure 2 , Figure 2 This is one of the structural block diagrams of a readout auxiliary circuit provided in one embodiment of this application. The readout auxiliary circuit provided in this embodiment is applied to a sensitive amplifier and includes: a voltage selector 10, configured such that: its input terminal is connected to a first driving signal, and its output terminal is used to provide different driving voltages to the bit line and the inverted bit line connected to the sensitive amplifier;
[0061] First switching unit 30;
[0062] The second switch unit 40 is connected to the first switch unit 30;
[0063] The driver 50 is configured such that: a first input terminal is connected to the output terminal of the voltage selector via a first switching unit 30, and a second input terminal is connected to the output terminal of the voltage selector 10 via a second switching unit 40;
[0064] The first switching unit 30 is used to transmit the driving voltage on the bit line to the first input terminal of the driver 50 when the second driving signal is received; the second switching unit 40 is used to transmit the driving voltage on the reverse bit line to the second input terminal of the driver 50 when the third driving signal is received.
[0065] For example, in the embodiments of this application, in order to facilitate the distinction of each driving signal, Vin is used to define the first driving signal, denoted as the first driving signal Vin; NSEL is used to define the second driving signal, denoted as the second driving signal NSEL; and NSELB is used to define the third driving signal, denoted as the third driving signal NSELB.
[0066] For example, different drive voltages include a first voltage VDD and a second voltage VDDOD (VVD Over drive, VDDOD), that is, the second voltage VDDOD is greater than the first voltage VDD.
[0067] Specifically, for abnormal operating states of MOSFETs caused by factors such as process disturbances, such as when the threshold of the MOSFET (transmission transistor PG or pull-down transistor PD) is large and the driving capability is weak, the second driving signal NSEL and the third driving signal NSELB can control the selection of the bit line that needs to be pulled high to VDDOD, so that the voltage difference between the bit line BL and the inverted bit line BLB increases during the reading process, making it easier for the driver 50 to read data and transmit the stored data DATA_OUT through the output terminal.
[0068] Please see Figure 3 , Figure 3 This is a second structural block diagram of the reading auxiliary circuit provided in one embodiment of this application. The reading auxiliary circuit provided in this embodiment further includes:
[0069] Capacitor branch 20 receives the fourth drive signal at its input and is grounded at its output and connected to the ground terminal of the sensitive amplifier to reduce the potential of the ground terminal.
[0070] The capacitor branch 20 includes a capacitor 21, configured such that the anode forms the input terminal of the capacitor branch 20 and receives the fourth drive signal, and the cathode forms the output terminal of the capacitor branch 20 and is grounded, and connected to the ground terminal of the sensitive amplifier.
[0071] For example, using V S_EN Define the fourth driving signal, which is the fourth driving signal V. S_EN C Boost Define capacitor 21, which is capacitor C. Boost There is no restriction on the capacitance value of capacitor 21 here.
[0072] In the above embodiment, when the fourth driving signal V S_EN When it is high, capacitor C Boost When the anode is charged, the common-source voltage of the pull-down transistor in the sensitive amplifier is ground voltage VSS; when the fourth drive signal V... S_EN When it is low level, capacitor C Boost When the anode potential is pulled down, since the potentials at both ends do not change abruptly, the cathode voltage is <0V, forming a negative voltage. This increases the gate-drain voltage of the pull-down transistor, enhancing its driving capability. Based on the read current I... read From the formula, we can see that:
[0073]
[0074] Read current I read With the current I of the pull-down transistor PD As the size increases, the reliability of reading is improved.
[0075] Further, in an optional embodiment, the reading auxiliary circuit includes a signal generator configured to: have a first output terminal connected to the input terminal of the voltage selector 10, a second output terminal connected to the capacitor branch 20, a third output terminal connected to the first terminal of the first switching unit 30 and the fourth terminal of the second switching unit 40, and a fourth output terminal connected to the fourth terminal of the first switching unit 30 and the first terminal of the second switching unit 40, for providing a drive signal.
[0076] In the above embodiments, the signal generator provides corresponding drive signals to the voltage selector 10, capacitor branch 20, first switching unit 30 and second switching unit 40, so that the read auxiliary circuit provided in this embodiment can improve the read stability of SRAM by combining the reduction of the common source voltage of the PD MOS transistor and the pull-up of the bit line voltage.
[0077] The following is combined Figures 4 to 7 The writing auxiliary circuit provided in this embodiment is described in detail.
[0078] Please see Figure 4 In an optional embodiment, the voltage selector 10 includes:
[0079] The first selection transistor 11 is configured such that: its first terminal is connected to the first voltage VDD, its gate-controlled terminal forms the input terminal of the voltage selector 10 and is connected to the first driving signal Vin, and its second terminal forms the output terminal of the voltage selector 10 and is connected to the bit line BL and the inverted bit line BLB, and is used to be in the conducting state when the first driving signal Vin is the first electrical signal.
[0080] The second gating transistor 12 is configured such that: its first terminal is connected to the second voltage VDDOD, its gate control terminal is connected to the gate control terminal of the first gating transistor 11, and its second terminal is connected to the second terminal of the first gating transistor 11, and is used to be in the on state when the first driving signal Vin is the second electrical signal.
[0081] Specifically, the channel conductivity types of the first selection transistor 11 and the second selection transistor 12 are opposite; the logic states of the first electrical signal and the second electrical signal are opposite.
[0082] In the above embodiment, when the first driving signal Vin is a first electrical signal, the first gating transistor is turned on and connected to the first voltage VDD; when the first driving signal Vin is a second electrical signal, the second gating transistor is turned on and connected to the second voltage (possibly VDD or lower), forming a complementary dual-voltage source gating structure. During the read operation, the driving voltage applied to the bit line or the inverted bit line is quickly switched by the first driving signal Vin, increasing the voltage difference between the two and improving the read success rate and accuracy of the sensitive amplifier. At the same time, the complementary gating structure can avoid unnecessary voltage fluctuations, simplify its control logic, and reduce wiring complexity and signal delay.
[0083] Please continue reading. Figure 2 In an optional embodiment, the first switching unit 30 is configured such that: a first terminal is connected to the second driving signal NSEL, a second terminal is connected to the output terminal of the voltage selector 10 and the bit line BL, a third terminal is connected to the first input terminal of the driver 50, and a fourth terminal receives the third driving signal NSELB;
[0084] The second switching unit 40 is configured such that: its first end is connected to the fourth end of the first switching unit 30, its second end is connected to the output end of the voltage selector 10 and the inverted bit line BLB, its third end is connected to the second input end of the driver 50, and its fourth end is connected to the first end of the first switching unit 30.
[0085] Further, please refer to Figure 5 In some embodiments, the first switching unit 30 includes:
[0086] The third gate transistor 31 is configured such that: the gate control terminal forms the first terminal of the first switching unit 30, the first terminal forms the second terminal of the first switching unit 30 and is connected to the output terminal of the voltage selector 10 and the bit line BL, and the second terminal forms the third terminal of the first switching unit 30 and is connected to the first input terminal of the driver 50, and is used to be in the on state when receiving the second drive signal NSEL.
[0087] The fourth gating transistor 32 is configured such that its gate-controlled terminal forms the fourth terminal of the first switching unit 30, its first terminal is connected to the first terminal of the third gating transistor 31, and its second terminal is connected to the second terminal of the third gating transistor 31, and is in the off state when receiving the third drive signal NSELB.
[0088] For further information, please refer to [link / reference]. Figure 5 In some embodiments, the second switching unit 40 includes:
[0089] The fifth selector transistor 41 is configured such that: its gate-controlled terminal forms the first terminal of the second switch unit 40 and is connected to the fourth terminal of the first switch unit 30; its first terminal forms the second terminal of the second switch unit 40 and is connected to the output terminal of the voltage selector 10 and the inverted bit line BLB; and its second terminal forms the third terminal of the second switch unit 40 and is connected to the second input terminal of the driver 50, and is used to be in the on state when receiving the third drive signal NSELB.
[0090] The sixth gating transistor 42 is configured such that its gate-controlled terminal forms the fourth terminal of the second switching unit 40 and is connected to the first terminal of the first switching unit 30, its first terminal is connected to the first terminal of the fifth gating transistor 41, and its second terminal is connected to the second terminal of the fifth gating transistor 41, and is used to be in the off state when receiving the second drive signal NSEL.
[0091] For example, the channel conductivity types of the third gate transistor 31 and the fourth gate transistor 32 are opposite; the channel conductivity types of the fifth gate transistor 41 and the sixth gate transistor 42 are opposite; and the channel conductivity types of the third gate transistor 31 and the fifth gate transistor 41 are the same.
[0092] Furthermore, in some embodiments, the first gate transistor 11, the third gate transistor 31, and the fifth gate transistor 41 are NMOS transistors;
[0093] The second gate transistor 12, the fourth gate transistor 32, and the sixth gate transistor 42 are PMOS transistors.
[0094] Specifically, the first switching unit 30 and the second switching unit 40 simultaneously receive either the second driving signal NSEL or the third driving signal NSELB. When the second driving signal NSEL (high level) is received, the third gating transistor 31 is in the on state, the sixth gating transistor 42 is in the off state, and the second voltage VDDOD provided by the voltage selector 10 is connected to the bit line BL, while the voltage of the bit line BLB remains VDD. When the third driving signal NSELB (high level) is received, the fifth gating transistor 41 is in the on state, the fourth gating transistor 32 is in the off state, and the second voltage VDDOD provided by the voltage selector 10 is connected to the bit line BLB, while the voltage of the bit line BL remains VDD, ultimately resulting in the following... Figure 6 The diagram showing the voltage difference between the bit lines is shown. Figure 6 In (a), ΔV1 represents the bit line voltage difference when the read auxiliary circuit provided in this application is not used; where Figure 6 In (b), ΔV2 represents the bit line voltage difference when the reading auxiliary circuit provided in this application is not used, and the bit line voltage difference increases significantly.
[0095] In the above embodiments, the selection transistors with different channel conductivity types within the same switching unit can achieve signal interlocking, avoid conflicts caused by simultaneous conduction, improve signal stability, and reduce false triggering.
[0096] Please see Figure 7 Another aspect of this application provides a memory, including: a memory array comprising a plurality of memory cells arranged in multiple rows and columns;
[0097] Several bit lines, each of which is electrically connected to a memory cell located in the same column;
[0098] Several sensitive amplifiers are connected one-to-one with each bit line;
[0099] Several readout auxiliary circuits as described in any of the above embodiments are connected one-to-one with the sensitive amplifier and each bit line.
[0100] The memory read process in the above embodiments features higher read current and bit line voltage drop. The higher read current accelerates the bit line discharge speed, shortens read time, and increases speed. Simultaneously, the enhanced drive capability of the pull-down transistor or transmission transistor minimizes the impact of process disturbances and other factors on the operating state of the MOSFET in the sensitive amplifier.
[0101] Secondly, increasing the bit line voltage and thus the bit line voltage difference effectively improves the accuracy and stability of the reading, especially in low voltage or high noise environments. This reduces the high requirements for the sensitivity of the sensitive amplifier, thereby simplifying its design or allowing the use of a more efficient amplifier structure.
[0102] Another aspect of this application provides an electronic device, including a read-aid circuit as in any of the above embodiments; or a memory as in the above embodiments.
[0103] Since the electronic devices described above and the read-aid circuit for memory provided by this utility model belong to the same inventive concept, the electronic devices using such circuits or memory have all the advantages of the read-aid circuit for memory provided by this utility model, which will not be described in detail here.
[0104] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.
[0105] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0107] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A read assist circuit, comprising: Applications in sensitive amplifiers, including: A voltage selector is configured such that its input is connected to a first drive signal and its output is used to provide different drive voltages to the bit line and the inverted bit line connected to the sensitive amplifier. First switching unit; The second switching unit is connected to the first switching unit; The driver is configured such that a first input terminal is connected to the output terminal of the voltage selector via the first switching unit, and a second input terminal is connected to the output terminal of the voltage selector via the second switching unit; The first switching unit is used to transmit the driving voltage on the bit line to the first input terminal of the driver when a second driving signal is received; the second switching unit is used to transmit the driving voltage on the reverse bit line to the second input terminal of the driver when a third driving signal is received.
2. The read assist circuit of claim 1, wherein, The reading auxiliary circuit also includes: The capacitor branch is configured such that its input terminal receives a fourth drive signal, and its output terminal is grounded and connected to the ground terminal of the sensitive amplifier, in order to reduce the potential of the ground terminal.
3. The read assist circuit of claim 2, wherein, The voltage selector includes: The first selection transistor is configured such that: a first terminal is connected to a first voltage, a gate-controlled terminal forms the input terminal of the voltage selector and is connected to a first driving signal, and a second terminal forms the output terminal of the voltage selector and is connected to the bit line and the inverted bit line, for being in the on state when the first driving signal is a first electrical signal; The second gate transistor is configured such that: its first terminal is connected to a second voltage, its gate control terminal is connected to the gate control terminal of the first gate transistor, and its second terminal is connected to the second terminal of the first gate transistor, and is used to be in an on state when the first driving signal is the second electrical signal.
4. The read assist circuit of claim 2, wherein, The first switching unit is configured such that: a first terminal is connected to the second driving signal, a second terminal is connected to the output terminal of the voltage selector and the bit line, a third terminal is connected to the first input terminal of the driver, and a fourth terminal is connected to the third driving signal; The second switching unit is configured such that: a first end is connected to the fourth end of the first switching unit, a second end is connected to the output end of the voltage selector and the inverting bit line, a third end is connected to the second input end of the driver, and a fourth end is connected to the first end of the first switching unit.
5. The read assist circuit of claim 4, wherein, The first switching unit includes: The third gating transistor is configured such that: the gate-controlled terminal forms the first terminal of the first switching unit, the first terminal forms the second terminal of the first switching unit and is connected to the output terminal of the voltage selector and the bit line, and the second terminal forms the third terminal of the first switching unit and is connected to the first input terminal of the driver, for being in the on state when receiving the second driving signal; The fourth gating transistor is configured such that its gate-controlled terminal forms the fourth terminal of the first switching unit, its first terminal is connected to the first terminal of the third gating transistor, and its second terminal is connected to the second terminal of the third gating transistor, and is in the off state when receiving a third driving signal.
6. The read assist circuit of claim 4, wherein, The second switching unit includes: The fifth selector transistor is configured such that: its gate-controlled terminal forms the first terminal of the second switching unit and is connected to the fourth terminal of the first switching unit; its first terminal forms the second terminal of the second switching unit and is connected to the output terminal of the voltage selector and the inverted bit line; and its second terminal forms the third terminal of the second switching unit and is connected to the second input terminal of the driver, for being in the on state when receiving a third drive signal. The sixth gating transistor is configured such that its gate-controlled terminal forms the fourth terminal of the second switching unit and is connected to the first terminal of the first switching unit, its first terminal is connected to the first terminal of the fifth gating transistor, and its second terminal is connected to the second terminal of the fifth gating transistor, and is used to be in the off state when receiving the second driving signal.
7. The reading auxiliary circuit according to any one of claims 1-6, characterized in that, include: The first, third, and fifth gate transistors are NMOS transistors; The second, fourth, and sixth gate transistors are PMOS transistors.
8. The reading auxiliary circuit according to any one of claims 1-6, characterized in that, include: A signal generator is configured such that: a first output terminal is connected to the input terminal of the voltage selector; a second output terminal is connected to the capacitor branch; a third output terminal is connected to the first terminal of the first switching unit and the fourth terminal of the second switching unit; and a fourth output terminal is connected to the fourth terminal of the first switching unit and the first terminal of the second switching unit, for providing the drive signal.
9. A memory, characterized in that, include: A storage array comprises several storage cells arranged in multiple rows and columns; A plurality of bit lines, wherein each bit line is electrically connected to a memory cell located in the same column; Several sensitive amplifiers are connected one-to-one with each of the aforementioned bit lines; and Several readout auxiliary circuits as described in any one of claims 1-8 are connected one-to-one with the sensitive amplifier and each of the bit lines.
10. An electronic device, characterized in that, Includes the readout auxiliary circuit as described in any one of claims 1-8; or The memory as described in claim 9.