Substation emergency standby power supply system and substation power failure control system

Abstract

This utility model discloses a substation emergency backup power supply system and a substation power outage control system. The substation emergency backup power supply system includes: a main control circuit, an AC-to-DC circuit, an auxiliary power supply, a battery module, a constant current charging circuit, a battery voltage acquisition circuit, a battery switching circuit, and a motor control circuit. The output terminal of the main control circuit is connected to the input terminal of the motor control circuit, enabling it to send control signals to the motor control circuit. The motor control circuit is connected to a drive mechanism, which is connected to the substation high-voltage switch, enabling it to control the switching action of the substation high-voltage switch. The substation emergency backup power supply system and substation power outage control system proposed in this utility model can improve the safety and intelligence of substation power outage shutdown.

Description

Technical Field

[0001] This utility model belongs to the field of backup power technology, and relates to a backup power system, and more particularly to a substation emergency backup power system and a substation power outage control system. Background Technology

[0002] With the development of global technology, the demand for electricity is increasing daily. To ensure that electrical equipment continues to operate during grid failures, emergency backup power systems have emerged. However, the structure of existing emergency backup power systems cannot meet today's requirements for power system automation and high reliability.

[0003] In view of this, there is an urgent need to design a new backup power system in order to overcome at least some of the aforementioned shortcomings of existing backup power systems. Summary of the Invention

[0004] This utility model provides a substation emergency backup power supply system and a substation power outage control system, which can improve the safety and intelligence of substation power outage shutdown.

[0005] To solve the above-mentioned technical problems, according to one aspect of this utility model, the following technical solution is adopted:

[0006] A substation emergency backup power system includes: a main control circuit, an AC-to-DC circuit, an auxiliary power supply, a battery module, a constant current charging circuit, a battery voltage acquisition circuit, a battery switching circuit, and a motor control circuit.

[0007] The main control circuit is connected to the AC to DC circuit, auxiliary power supply, constant current charging circuit, battery voltage acquisition circuit, battery switching circuit and motor control circuit respectively.

[0008] The AC-to-DC circuit is used to convert AC power into DC power; the AC-to-DC circuit is connected to the auxiliary power supply and the constant current charging circuit respectively, providing DC power to the auxiliary power supply and the constant current charging circuit; the auxiliary power supply provides DC power to auxiliary equipment (such as remote terminal unit RTU, etc.);

[0009] The battery voltage acquisition circuit is used to acquire the voltage data of the battery module. The output terminal of the battery voltage acquisition circuit is connected to the input terminal of the main control circuit, and the acquired voltage data is sent to the main control circuit.

[0010] The output terminal of the main control circuit is connected to the input terminal of the battery switching circuit, and can send a power switching control signal to the battery switching circuit.

[0011] The battery switching circuit is connected to the battery module and can control the battery module to start supplying power; the constant current charging circuit is connected to the battery module and can charge the battery module.

[0012] The output terminal of the main control circuit is connected to the input terminal of the motor control circuit, and can send control signals to the motor control circuit; the motor control circuit is connected to a drive mechanism, which is connected to the substation high-voltage switch, and can control the switching action of the substation high-voltage switch.

[0013] As one embodiment of the present invention, the substation emergency backup power supply system further includes an AC detection circuit, which is used to detect the presence of AC power.

[0014] The output of the AC detection circuit is connected to the input of the main control circuit, and the detected signal is sent to the main control circuit.

[0015] As one embodiment of this utility model, the substation emergency backup power system further includes at least one control button, and each control button is connected to the main control circuit.

[0016] In one embodiment of this utility model, the substation emergency backup power system further includes a display module, which is used to display setting information; the display module is connected to the main control circuit.

[0017] In one embodiment of this utility model, the constant current charging circuit includes a third chip U3, a sixth chip U3, a second MOSFET M2, a second AC contactor CJ2, a second inductor L2, a third inductor L3, a first diode D11, a first second Schottky diode D12, a first third Schottky diode D13, a first fourth diode D14, a first capacitor C1, a second sixth capacitor C26, a second seventh capacitor C27, a second eighth capacitor C28, a second ninth capacitor C29, a third zero capacitor C30, a third first capacitor C31, a third second capacitor C32, a second fourth resistor R24, a second fifth resistor R25, a second sixth resistor R26, a second seventh resistor R27, a second eighth resistor R28, a second ninth resistor R29, a third zero resistor R30, a first fourth resistor R114, a first fifth resistor R115, a first sixth resistor R116, a first seventh resistor R117, a first eighth resistor R118, and a first ninth resistor R119.

[0018] The first terminal of the second AC contactor CJ2 is connected to the first terminal of the second four resistor R24. The second terminal of the second four resistor R24 ​​is connected to the third terminal of the second AC contactor CJ2, the first terminal of the second six capacitor C26, the first terminal of the second seven capacitor C27, the first terminal of the second seven resistor R27, and the first terminal of the third inductor L3.

[0019] The fourth terminal of the second AC contactor CJ2 is connected to the positive terminal of the first four diode D14 and the drain of the second MOSFET M2. The gate of the second MOSFET M2 is connected to the second terminal of the second six resistor R26 and the first terminal of the second nine capacitor C29. The second terminal of the second nine capacitor C29 is grounded, and the source of the second MOSFET M2 is grounded.

[0020] The second terminal of the second sixth capacitor C26 is connected to the second terminal of the second seventh capacitor C27, and the second terminal of the third inductor L3 is connected to the third pin of the third chip U3 and the first terminal of the third second capacitor C32, respectively.

[0021] The second end of the second seven resistor R27 is connected to the fourth pin of the third chip U3, the first end of the second eight capacitor C28, and the first end of the second eight resistor R28. The second end of the second eight resistor R28 is connected to the second pin of the third chip U3 and the first end of the third zero resistor R30.

[0022] The second terminal of the third capacitor C32 is connected to the first terminal of the second inductor L2, the first terminal of the first Schottky diode D12, and the third terminal of the first Schottky diode D12, respectively; the second terminal of the first Schottky diode D12 is connected to the first terminal of the second resistor R25, the first terminal of the third zero capacitor C30, the first terminal of the third one capacitor C31, the first terminal of the first three Schottky diode D13, and the third terminal of the first three Schottky diode D13, respectively; the second terminal of the first three Schottky diode D13 is connected to the battery module.

[0023] The fifth pin of the third chip U3 is connected to the second terminal of the second five resistor R25, the first terminal of the second nine resistor R29, and the negative terminal of the first one diode D11; the second terminal of the second nine resistor R29 is connected to the second terminal of the third zero capacitor C30 and the second terminal of the third one capacitor C31.

[0024] The first pin of the sixth chip U6 is connected to the second terminal of the first 115 resistor R115, and the third pin of the sixth chip U6 is connected to the second terminal of the first 18 resistor R118, the second terminal of the first 17 resistor R117, and the first terminal of the first 19 resistor R119, respectively; the first terminal of the first 18 resistor R118 is grounded, the second terminal of the first 19 resistor R119 is grounded, and the second pin of the sixth chip U6 is grounded.

[0025] The fourth pin of the sixth chip U6 is connected to the first end of the first 117 resistor R117 and the first end of the first 116 resistor R116, and the second end of the first 116 resistor R116 is connected to the positive terminal of the first diode D11.

[0026] In one embodiment of this utility model, the auxiliary power supply includes a first chip U1, a second chip U2, a first transistor V1, a second transistor V2, a third transistor V3, a fourth transistor V4, a fifth transistor V5, a first MOSFET M1, a first AC contactor CJ1, a first inductor L1, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a ninth diode D9, a first zero diode D10, a second capacitor C2, a third capacitor C3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a first zero capacitor C10, a first first capacitor C11, a first second capacitor C12, a first third capacitor C13, and a first fourth capacitor. C14, First 5th capacitor; C15, First 8th capacitor; C18, First 9th capacitor; C19, Second 0th capacitor; C20, Second 1st capacitor; C21, Second 2nd capacitor; C22, Second 3rd capacitor; C23, Second 4th capacitor; C24, Second 5th capacitor; C25, First resistor; R1, Second resistor; R2, Third resistor; R3, Fourth resistor; R4, Fifth resistor; R5, Sixth resistor; R6, Seventh resistor; R7, Eighth resistor; R8, Ninth resistor; R9, First 0th resistor; R10, First 1st resistor; R11, First 2nd resistor; R12, First 3rd resistor; R13, First 4th resistor; R14, First 5th resistor; R15, First 6th resistor; R16, First 7th resistor; R17, First 8th resistor; R18, First 9th resistor; R19, Second 0th resistor; R20, Second 1st resistor; R21, First negative temperature coefficient resistor; NTR1, First fuse; F1;

[0027] The first terminal of the first fuse device F1 is connected to the first power supply voltage, the second terminal of the first fuse device F1 is connected to the first terminal of the first AC contactor CJ1, and the third terminal of the first AC contactor CJ1 is connected to the first terminal of the first zero capacitor C10, the first terminal of the first capacitor C11, the first terminal of the second capacitor C2, the second power supply voltage, and the collector of the first transistor V1, respectively; the second terminals of the first zero capacitor C10, the first capacitor C11, and the second capacitor C2 are respectively grounded.

[0028] The fourth terminal of the first AC contactor CJ1 is connected to the positive terminal of the fourth diode D4 and the drain of the first MOSFET M1, respectively. The gate of the first MOSFET M1 is connected to the second terminal of the seventh resistor R7 and the first terminal of the ninth capacitor C9, respectively. The second terminal of the ninth capacitor C9 is grounded, and the source of the first MOSFET M1 is grounded.

[0029] The gate of the first transistor V1 is connected to the negative terminal of the first diode D1 and the second terminal of the third resistor R3, respectively. The positive terminal of the first diode D1 is connected to the second terminal of the first resistor R1. The first terminal of the first resistor R1 is connected to the first terminal of the third resistor R3 and the third pin HO1 of the first chip U1.

[0030] The emitter of the first transistor V1 is connected to the collector of the second transistor V2, the VS1 pin of the first chip U1, the first terminal of the first capacitor C12, the first terminal of the seventh capacitor C7, and the first terminal of the first inductor L1.

[0031] The base of the second transistor V2 is connected to the cathode of the third diode D3 and the second terminal of the ninth resistor R9. The anode of the third diode D3 is connected to the second terminal of the fifth resistor R5. The first terminal of the fifth resistor R5 is connected to the first terminal of the ninth resistor R9 and the second and third pins LO1 of the first chip U1. The emitter of the second transistor V2 is grounded.

[0032] The second terminals of the first two capacitors C12 are respectively connected to the negative terminal of the seventh diode D7 and the third pin VB1 of the first chip U1; the positive terminal of the seventh diode D7 is connected to the third power supply voltage; the second terminal of the seventh capacitor C7 is connected to the first terminal of the first resistor R11, and the second terminal of the first resistor R11 is grounded.

[0033] The second end of the first inductor L1 is connected to the first end of the eighth capacitor C8, the second seventh pin VS2 of the first chip U1, the second end of the first triple capacitor C13, the emitter of the third transistor V3, and the collector of the fourth transistor V4.

[0034] The second terminal of the eighth capacitor C8 is connected to the first terminal of the first three resistors R13, and the second terminal of the first three resistors R13 is grounded; the second nine-pin VB2 of the first chip U1 is connected to the first terminal of the first three capacitors C13 and the negative terminal of the sixth diode D6, respectively, and the positive terminal of the sixth diode D6 is connected to the third power supply voltage.

[0035] The collector of the third transistor V3 is connected to the fourth power supply voltage, the first terminal of the fifth capacitor C5, the first terminal of the third capacitor C3, and the first terminal of the sixth capacitor C6, respectively; the second terminals of the fifth capacitor C5 and the second terminals of the third capacitor C3 are grounded; the second terminal of the sixth capacitor C6 is connected to the first terminal of the eighth resistor R8, and the second terminal of the eighth resistor R8 is grounded.

[0036] The base of the third transistor V3 is connected to the positive terminal of the second diode D2 and the first terminal of the fourth resistor R4, respectively. The negative terminal of the second diode D2 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the second terminal of the fourth resistor R4 and the second octet HO2 of the first chip U1.

[0037] The base of the fourth transistor V4 is connected to the positive terminal of the fifth diode D5 and the first terminal of the first zero resistor R10. The negative terminal of the fifth diode D5 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the second terminal of the first zero resistor R10 and the LO2 pin of the first chip U1. The emitter of the fourth transistor V4 is grounded.

[0038] The first pin VDD1 of the first chip U1 is connected to the third power supply voltage and the second terminal of the first four capacitors C14, and the first terminal of the first four capacitors C14 is grounded.

[0039] The second pin IFB+ of the first chip U1 is connected to the second terminal of the first five capacitor C15 and the second terminal of the first five resistor R15 respectively; the first terminal of the first five resistor R15 is connected to the second terminal of the first two resistor R12, and the first terminal of the first two resistor R12 is grounded.

[0040] The third pin IFB- of the first chip U1 is connected to the first terminal of the first five capacitor C15 and the second terminal of the first four resistor R14, respectively. The first terminal of the first four resistor R14 is grounded.

[0041] The eighth pin VINFB of the first chip U1 is connected to the second end of the first six resistor R16, the first end of the first six capacitor C16, and the first end of the first seven resistor R17, respectively; the first end of the first six resistor R16 is connected to the second power supply voltage, and the second ends of the first six capacitor C16 and the second ends of the first seven resistor R17 are grounded, respectively.

[0042] The ninth pin RSTN of the first chip U1 is connected to the first terminal of the first capacitor C17, and the second terminal of the first capacitor C17 is grounded; the first zero pin AVSS of the first chip U1 is grounded.

[0043] The first pin AVDD of the first chip U1 is connected to the fifth power supply voltage and the first terminal of the first capacitor C19, and the second terminal of the first capacitor C19 is grounded.

[0044] The first two pins of the first chip U1, LDO15, are connected to the first terminal of the second capacitor C21, and the second terminal of the second capacitor C21 is grounded.

[0045] The first three pins of the first chip U1, VOUTFB, are respectively connected to the first end of the second three resistor R23, the first end of the second two capacitor C22, and the first end of the second zero resistor R20. The second end of the second three resistor R23 and the second end of the second two capacitor C22 are respectively grounded.

[0046] The first four pins of the first chip U1, TFB pin, are respectively connected to the first terminal of the first negative temperature coefficient resistor NTR1, the first terminal of the second three capacitors C23, and the first terminal of the second one resistor R21. The second terminals of the first negative temperature coefficient resistor NTR1 and the second three capacitors C23 are respectively grounded.

[0047] The collector of the fifth transistor V5 is connected to the second power supply voltage and the first terminal of the first eight resistor R18, respectively. The base of the fifth transistor V5 is connected to the second terminal of the first eight resistor R18, the first terminal of the first eight capacitor C18, and the negative terminal of the eighth diode D8, respectively. The second terminal of the first eight capacitor C18 and the positive terminal of the eighth diode D8 are grounded.

[0048] The emitter of the fifth transistor V5 is connected to the positive terminal of the ninth diode D9, and the negative terminal of the ninth diode D9 is connected to the negative terminal of the first diode D10 and the first terminal of the second resistor R22.

[0049] The first pin VIN of the second chip U2 is connected to the second terminal of the second resistor R22 and the second terminal of the second zero capacitor C20, respectively, and the first terminal of the second zero capacitor C20 is grounded.

[0050] The second pin VO1 of the second chip U2 is connected to the fifth power supply voltage and the first terminal of the second capacitor C25, and the second terminal of the second capacitor C25 is grounded.

[0051] The eighth pin VO2 of the second chip U2 is connected to the third power supply voltage and the first terminal of the second fourth capacitor C24, and the second terminal of the second fourth capacitor C24 is grounded.

[0052] In one embodiment of this utility model, the battery voltage acquisition circuit includes a fourth chip U4, a third eighth capacitor C38, a third ninth capacitor C39, a first first Zener diode Z11, a first second Zener diode Z12, a first sixth Zener diode Z16, a third first resistor R31, a third second resistor R32, a third third resistor R33, a third fourth resistor R34, a third fifth resistor R35, a third sixth resistor R36, a third seventh resistor R37, a third eighth resistor R38, a fourth third resistor R43, and a fourth fourth resistor R44.

[0053] The first pin of the fourth chip U4 is connected to the first end of the third resistor R34, the third pin of the fourth chip U4 is connected to the first end of the third resistor R32, and the second end of the third resistor R34 is connected to the second end of the third resistor R32.

[0054] The fifth pin of the fourth chip U4 is connected to the battery voltage through the third resistor R31; the seventh pin of the fourth chip U4 is connected to the third resistor R33.

[0055] The sixth pin of the fourth chip U4 is connected to the first end of the third six resistor R36, and the eighth pin of the fourth chip U4 is connected to the first end of the third seven resistor R37; the second end of the third six resistor R36 is connected to the first end of the third eight resistor R38.

[0056] The second terminal of the third resistor R37 is connected to the first terminal of the third capacitor C38, the first terminal of the fourth resistor R43, and the negative terminal of the first Zener diode Z12; the positive terminal of the first Zener diode Z12 is grounded.

[0057] The second terminal of the third resistor R38 is connected to the first terminal of the third capacitor C39, the first terminal of the fourth resistor R44, and the negative terminal of the first Zener diode Z11; the positive terminal of the first Zener diode Z11 is grounded.

[0058] The second terminal of the third eight capacitor C38 is connected to the second terminal of the fourth three resistor R43, the second terminal of the third nine capacitor C39, the second terminal of the fourth four resistor R44, and the first terminal of the third five resistor R35. The second terminal of the third five resistor R35 is connected to the negative terminal of the first six Zener diode Z16, and the positive terminal of the first six Zener diode Z16 is grounded.

[0059] In one embodiment of this utility model, the battery switching circuit includes a fifth chip U5, a first transistor MD1, a second transistor MD2, a third transistor MD3, a fourth transistor MD4, a seventh MOSFET M7, a third capacitor C33, a third capacitor C34, a third capacitor C35, a third capacitor C36, a third capacitor C37, an eighth capacitor C85, an eighth capacitor C86, a third resistor R39, a fourth resistor R40, and a fourth resistor R... 41. Resistor R42, Resistor R99, Resistor R100, Resistor R101, Resistor R102, Resistor R103, Resistor R104, Resistor R105, Resistor R106, Resistor R107, Resistor R108, Resistor R109, Resistor R110, Resistor R111, and Resistor R113;

[0060] The first pin of the fifth chip U5 is connected to the second terminal of the third six capacitor C36. The first terminal of the third six capacitor C36 is connected to the second terminal of the first zero resistor R110, the second terminal of the third seven capacitor C37, and the second pin of the fifth chip U5.

[0061] The first zero pin of the fifth chip U5 is connected to the first end of the first resistor R111, the second end of the first resistor R111 is connected to the first end of the first resistor R113, and the second end of the first resistor R113 is grounded.

[0062] The pins of the fifth chip U5 are respectively connected to the second end of the first zero-eight resistor R108 and the first end of the eighth six capacitor C86, and the second end of the eighth six capacitor C86 is grounded.

[0063] The first and second pins of the fifth chip U5 are respectively connected to the second terminals of the first zero-two resistor R102, the second terminals of the fourth two resistor R42, and the second terminals of the ninth nine resistor R99; the fourth pin of the fifth chip U5 is connected to the second terminal of the first zero-one resistor R101.

[0064] The first and sixth pins of the fifth chip U5 are respectively connected to the second end of the fourth resistor R41, the second end of the first zero-nine resistor R109, and the second end of the first zero-zero resistor R100.

[0065] The first terminal of the first zero resistor R110 is connected to the battery voltage, the first terminal of the third capacitor C33, the first terminal of the third resistor R39, the emitter of the first transistor MD1, the emitter of the third transistor MD3, and the first terminal of the fourth resistor R41.

[0066] The second end of the third capacitor C33 is connected to the first end of the third capacitor C34. The second end of the third capacitor C34 is connected to the first end of the third capacitor C35, the first end of the first resistor R108, the first end of the ninth resistor R99, the emitter of the fourth transistor MD4, and the emitter of the second transistor MD2.

[0067] The collector of the fourth transistor MD4 is grounded, and the base of the fourth transistor MD4 is connected to the first terminal of the fourth resistor R42; the collector of the second transistor MD2 is grounded, and the base of the second transistor MD2 is connected to the first terminal of the first resistor R102.

[0068] The second end of the third nine resistor R39 is connected to the drain of the seventh MOS transistor M7, and the gate of the seventh MOS transistor M7 is connected to the first end of the first zero-one resistor R101 and the first end of the fourth zero resistor R40; the source of the seventh MOS transistor M7 and the second end of the fourth zero resistor R40 are respectively grounded.

[0069] The collector of the first transistor MD1 is grounded, and the base of the first transistor MD1 is connected to the first terminal of the first zero-zero resistor R100; the collector of the third transistor MD3 is grounded, and the base of the third transistor MD3 is connected to the first terminal of the first zero-nine resistor R109.

[0070] According to another aspect of this utility model, the following technical solution is adopted: a substation power outage control system, wherein the substation power outage control system includes the above-mentioned substation emergency backup power supply system.

[0071] In one embodiment of the present invention, the substation power outage control system further includes a drive mechanism and a substation high-voltage switch, wherein the drive mechanism is connected to the substation high-voltage switch.

[0072] The beneficial effects of this utility model are as follows: the substation emergency backup power supply system and substation power outage control system proposed in this utility model can improve the safety and intelligence of substation power outage shutdown.

[0073] This system primarily addresses the need to maintain control of power structures and ensure power supply to network equipment even in abnormal power plant conditions. It enables remote data exchange when equipment is functioning normally and sends abnormal data to the backend management center when equipment malfunctions. To achieve this, the equipment must have its own battery, requiring battery management; it must also have its own AC-DC power supply with power allocation capabilities; and the equipment must be capable of manual operation and provide alarms for any abnormalities.

[0074] This system ensures the integrity of power plant equipment data reporting, allowing the back-end control center to be aware of abnormal data immediately. Secondly, the use of this equipment eliminates the need for maintenance personnel to carry external power supplies, reducing their workload. Finally, the use of this equipment reduces the operation time for equipment maintenance and repair, which is of positive significance for ensuring power supply and for social production. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of the composition of a substation emergency backup power supply system in one embodiment of the present invention.

[0076] Figure 2 This is a circuit diagram of a constant current charging control circuit in one embodiment of the present invention.

[0077] Figure 3a , Figure 3b This is a circuit diagram of the auxiliary power supply in one embodiment of the present invention.

[0078] Figure 4 This is a circuit diagram of the battery voltage acquisition circuit in one embodiment of the present invention.

[0079] Figure 5a , Figure 5b This is a circuit diagram of the battery switching circuit in one embodiment of the present invention.

[0080] Figure 6 This is a circuit diagram of the AC detection circuit in one embodiment of the present invention.

[0081] Figure 7a , Figure 7b This is a circuit diagram of the motor control circuit in one embodiment of the present invention.

[0082] Figure 8 This is a circuit diagram of the communication interface circuit in one embodiment of the present invention.

[0083] Figures 9a to 9m This is a circuit diagram of the main control circuit (including the current acquisition circuit) in one embodiment of the present invention. Detailed Implementation

[0084] The preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings.

[0085] To further understand this utility model, preferred embodiments of this utility model are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of this utility model, and not for limiting the scope of the claims of this utility model.

[0086] The description in this section pertains to only a few typical embodiments, and this utility model is not limited to the scope of the embodiments described. Substitution of identical or similar prior art methods with some technical features in the embodiments is also within the scope of this utility model's description and protection.

[0087] The term "connection" in the specification includes both direct and indirect connections, such as connections made through active devices, passive devices, or electrical conduction media; it may also include connections made by other active or passive devices that are known to those skilled in the art and can achieve the same or similar functional purpose, such as connections made through circuits or components such as switches or follower circuits.

[0088] This utility model discloses an emergency backup power supply system for substations. Figure 1 This is a schematic diagram of the composition of a substation emergency backup power supply system according to one embodiment of the present invention; please refer to [link / reference]. Figure 1 The substation emergency backup power system includes: a main control circuit 6, an AC / DC converter 1, an auxiliary power supply 3, a battery module, a constant current charging circuit 2, a battery voltage acquisition circuit, a battery switching circuit 4, and a motor control circuit 5.

[0089] The main control circuit 6 is connected to the AC to DC circuit 1, the auxiliary power supply 3, the constant current charging circuit 2, the battery voltage acquisition circuit, the battery switching circuit 4, and the motor control circuit 5.

[0090] The AC-to-DC circuit 1 is used to convert AC power into DC power; the AC-to-DC circuit 1 is connected to the auxiliary power supply 3 and the constant current charging circuit 2 respectively, providing DC power to the auxiliary power supply 3 and the constant current charging circuit 2; the auxiliary power supply 3 provides DC power to auxiliary equipment (such as remote terminal unit RTU, and may also include other auxiliary equipment).

[0091] The battery voltage acquisition circuit is used to acquire voltage data from the battery module. The output of the battery voltage acquisition circuit is connected to the input of the main control circuit 6, sending the acquired voltage data to the main control circuit 6. The output of the main control circuit 6 is connected to the input of the battery switching circuit 4, sending a power switching control signal to the battery switching circuit 4. The battery switching circuit 4 is connected to the battery module and controls the battery module to start supplying power. The constant current charging circuit 2 is connected to the battery module and charges the battery module.

[0092] The output terminal of the main control circuit 6 is connected to the input terminal of the motor control circuit 5, and can send control signals to the motor control circuit 5; the motor control circuit 5 is connected to a drive mechanism, which is connected to the substation high-voltage switch, and can control the switching action of the substation high-voltage switch.

[0093] In one embodiment of this utility model, the substation emergency backup power system further includes an AC detection circuit, which is used to detect the presence of AC power; the output terminal of the AC detection circuit is connected to the input terminal of the main control circuit, and sends the detected signal to the main control circuit.

[0094] Furthermore, the substation emergency backup power system may further include at least one control button 7 and a display module 8, with each control button 7 connected to the main control circuit 6. The display module 8 is used to display setting information; the display module 8 is connected to the main control circuit 6.

[0095] In one application scenario of this utility model, when the substation emergency backup power system is idle, the equipment automatically charges the battery module to maintain it at full charge. When the battery module is relatively full (e.g., the charge level exceeds a first threshold), the charging logic directly connects the battery module to the power supply, and the battery module participates in power supply. When the voltage difference between the battery module and the power supply is large (e.g., exceeding a second threshold), the power supply is connected to the battery module via a DC-DC converter, and the circuit switch controls the discharge side to open and the charging side to close. The DC-DC converter and auxiliary circuits achieve constant current and constant voltage charging, protecting the battery module from damage due to excessive charging current and preventing the battery module from pulling down the power supply voltage, thus ensuring readiness for operation. The AC detection circuit can detect the presence of AC power. When AC power is interrupted and no human intervention is performed, the substation emergency backup power system enters a low-power sleep state.

[0096] When needed, the operator presses the panel button, and the equipment load control provides output to the load. The battery module and power supply simultaneously provide output capability to the load. When the power supply output exceeds 15A or the battery output exceeds 40A, or the total output from both exceeds 60A, the output will be cut off to protect the equipment.

[0097] The substation emergency backup power system also provides a separate 24V constant voltage auxiliary power supply to power other equipment and RTUs. When AC power is available, the auxiliary power supply is stable. When AC power fails, the equipment automatically shuts off the load first, and then shuts off the auxiliary power supply after a 10-second delay to prevent the battery from being completely discharged.

[0098] The device's alarm display module includes six LEDs: three green and three red. When the device is connected to AC power, the AC status LED is green; when AC power is disconnected, it is red. When there is an internal AC / DC malfunction or an abnormal load output, the DC status LED is red, and vice versa. When the battery voltage is low, the battery status LED is red, and vice versa. This alerts the operator to the operational status. All control logic of the device can be implemented by its own MCU software, which, in addition to control logic, also provides RS-485 communication protocol logic, OTA upgrade logic, and other functions.

[0099] Figure 2 This is a circuit diagram of the constant current charging control circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 2In one embodiment of this utility model, the constant current charging circuit includes a third chip U3, a sixth chip U3, a second MOSFET M2, a second AC contactor CJ2, a second inductor L2, a third inductor L3, a first diode D11, a first second Schottky diode D12, a first third Schottky diode D13, a first fourth diode D14, a first capacitor C1, a second sixth capacitor C26, a second seventh capacitor C27, a second eighth capacitor C28, a second ninth capacitor C29, a third zero capacitor C30, a third first capacitor C31, a third second capacitor C32, a second fourth resistor R24, a second fifth resistor R25, a second sixth resistor R26, a second seventh resistor R27, a second eighth resistor R28, a second ninth resistor R29, a third zero resistor R30, a first fourth resistor R114, a first fifth resistor R115, a first sixth resistor R116, a first seventh resistor R117, a first eighth resistor R118, and a first ninth resistor R119.

[0100] The first terminal of the second AC contactor CJ2 is connected to the first terminal of the second fourth resistor R24. The second terminal of the second fourth resistor R24 ​​is connected to the third terminal of the second AC contactor CJ2, the first terminal of the second sixth capacitor C26, the first terminal of the second seventh capacitor C27, the first terminal of the second seventh resistor R27, and the first terminal of the third inductor L3.

[0101] The fourth terminal of the second AC contactor CJ2 is connected to the positive terminal of the first four diode D14 and the drain of the second MOSFET M2. The gate of the second MOSFET M2 is connected to the second terminal of the second six resistor R26 and the first terminal of the second nine capacitor C29. The second terminal of the second nine capacitor C29 is grounded, and the source of the second MOSFET M2 is grounded. The second terminal of the second six capacitor C26 is connected to the second terminal of the second seven capacitor C27. The second terminal of the third inductor L3 is connected to the third pin of the third chip U3 and the first terminal of the third two capacitor C32. The second terminal of the second seven resistor R27 is connected to the fourth pin of the third chip U3, the first terminal of the second eight capacitor C28, and the first terminal of the second eight resistor R28. The second terminal of the second eight resistor R28 is connected to the second pin of the third chip U3 and the first terminal of the third zero resistor R30.

[0102] The second terminal of the third capacitor C32 is connected to the first terminal of the second inductor L2, the first terminal of the first Schottky diode D12, and the third terminal of the first Schottky diode D12, respectively; the second terminal of the first Schottky diode D12 is connected to the first terminal of the second resistor R25, the first terminal of the third zero capacitor C30, the first terminal of the third one capacitor C31, the first terminal of the first three Schottky diode D13, and the third terminal of the first three Schottky diode D13, respectively; the second terminal of the first three Schottky diode D13 is connected to the battery module.

[0103] The fifth pin of the third chip U3 is connected to the second terminal of the second five resistor R25, the first terminal of the second nine resistor R29, and the negative terminal of the first one diode D11; the second terminal of the second nine resistor R29 is connected to the second terminal of the third zero capacitor C30 and the second terminal of the third one capacitor C31.

[0104] The first pin of the sixth chip U6 is connected to the second end of the first 115 resistor R115, and the third pin of the sixth chip U6 is connected to the second end of the first 18 resistor R118, the second end of the first 17 resistor R117, and the first end of the first 19 resistor R119 respectively; the first end of the first 18 resistor R118 is grounded, the second end of the first 19 resistor R119 is grounded, and the second pin of the sixth chip U6 is grounded.

[0105] The fourth pin of the sixth chip U6 is connected to the first end of the first 117 resistor R117 and the first end of the first 116 resistor R116, and the second end of the first 116 resistor R116 is connected to the positive terminal of the first diode D11.

[0106] Figure 3a , Figure 3b This is a circuit diagram of the auxiliary power supply in one embodiment of the present invention; please refer to... Figure 3a , Figure 3bIn one embodiment of this utility model, the auxiliary power supply includes a first chip U1, a second chip U2, a first transistor V1, a second transistor V2, a third transistor V3, a fourth transistor V4, a fifth transistor V5, a first MOSFET M1, a first AC contactor CJ1, a first inductor L1, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a ninth diode D9, a first zero diode D10, a second capacitor C2, a third capacitor C3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a first zero capacitor C10, a first first capacitor C11, a first second capacitor C12, a first third capacitor C13, and a first fourth capacitor C14. 14. First 5th capacitor C15, First 8th capacitor C18, First 9th capacitor C19, Second 0th capacitor C20, Second 1st capacitor C21, Second 2nd capacitor C22, Second 3rd capacitor C23, Second 4th capacitor C24, Second 5th capacitor C25, First resistor R1, Second resistor R2, Third resistor R3, Fourth resistor R4, Fifth resistor R5, Sixth resistor R6, Seventh resistor R7, Eighth resistor R8, Ninth resistor R9, First 0th resistor R10, First 1st resistor R11, First 2nd resistor R12, First 3rd resistor R13, First 4th resistor R14, First 5th resistor R15, First 6th resistor R16, First 7th resistor R17, First 8th resistor R18, First 9th resistor R19, Second 0th resistor R20, Second 1st resistor R21, First negative temperature coefficient resistor NTR1, First fuse F1.

[0107] The first terminal of the first fuse device F1 is connected to the first power supply voltage, the second terminal of the first fuse device F1 is connected to the first terminal of the first AC contactor CJ1, and the third terminal of the first AC contactor CJ1 is connected to the first terminal of the first zero capacitor C10, the first terminal of the first capacitor C11, the first terminal of the second capacitor C2, the second power supply voltage, and the collector of the first transistor V1, respectively. The second terminals of the first zero capacitor C10, the first capacitor C11, and the second capacitor C2 are grounded, respectively.

[0108] The fourth terminal of the first AC contactor CJ1 is connected to the positive terminal of the fourth diode D4 and the drain of the first MOSFET M1. The gate of the first MOSFET M1 is connected to the second terminal of the seventh resistor R7 and the first terminal of the ninth capacitor C9. The second terminal of the ninth capacitor C9 is grounded, and the source of the first MOSFET M1 is grounded.

[0109] The gate of the first transistor V1 is connected to the negative terminal of the first diode D1 and the second terminal of the third resistor R3, respectively. The positive terminal of the first diode D1 is connected to the second terminal of the first resistor R1. The first terminal of the first resistor R1 is connected to the first terminal of the third resistor R3 and the third pin HO1 of the first chip U1.

[0110] The emitter of the first transistor V1 is connected to the collector of the second transistor V2, the VS1 pin of the first chip U1, the first terminal of the first capacitor C12, the first terminal of the seventh capacitor C7, and the first terminal of the first inductor L1. The base of the second transistor V2 is connected to the cathode of the third diode D3 and the second terminal of the ninth resistor R9. The anode of the third diode D3 is connected to the second terminal of the fifth resistor R5. The first terminal of the fifth resistor R5 is connected to the first terminal of the ninth resistor R9 and the LO1 pin of the first chip U1. The emitter of the second transistor V2 is grounded.

[0111] The second terminals of the first two capacitors C12 are respectively connected to the negative terminal of the seventh diode D7 and the third pin VB1 of the first chip U1; the positive terminal of the seventh diode D7 is connected to the third power supply voltage; the second terminal of the seventh capacitor C7 is connected to the first terminal of the first resistor R11, and the second terminal of the first resistor R11 is grounded.

[0112] The second terminal of the first inductor L1 is connected to the first terminal of the eighth capacitor C8, the second seventh pin VS2 of the first chip U1, the second terminal of the first triple capacitor C13, the emitter of the third transistor V3, and the collector of the fourth transistor V4. The second terminal of the eighth capacitor C8 is connected to the first terminal of the first triple resistor R13, and the second terminal of the first triple resistor R13 is grounded. The second ninth pin VB2 of the first chip U1 is connected to the first terminal of the first triple capacitor C13 and the cathode of the sixth diode D6, and the anode of the sixth diode D6 is connected to the third power supply voltage.

[0113] The collector of the third transistor V3 is connected to the fourth power supply voltage, the first terminal of the fifth capacitor C5, the first terminal of the third capacitor C3, and the first terminal of the sixth capacitor C6, respectively; the second terminals of the fifth capacitor C5 and the third capacitor C3 are grounded, respectively; the second terminal of the sixth capacitor C6 is connected to the first terminal of the eighth resistor R8, and the second terminal of the eighth resistor R8 is grounded.

[0114] The base of the third transistor V3 is connected to the positive terminal of the second diode D2 and the first terminal of the fourth resistor R4. The negative terminal of the second diode D2 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the second terminal of the fourth resistor R4 and the second octet HO2 of the first chip U1.

[0115] The base of the fourth transistor V4 is connected to the positive terminal of the fifth diode D5 and the first terminal of the first zero resistor R10. The negative terminal of the fifth diode D5 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the second terminal of the first zero resistor R10 and the LO2 pin of the first chip U1. The emitter of the fourth transistor V4 is grounded.

[0116] The first pin VDD1 of the first chip U1 is connected to the third power supply voltage and the second terminal of the first fourth capacitor C14, with the first terminal of the first fourth capacitor C14 grounded. The second pin IFB+ of the first chip U1 is connected to the second terminal of the first fifth capacitor C15 and the second terminal of the first fifth resistor R15; the first terminal of the first fifth resistor R15 is connected to the second terminal of the first second resistor R12, with the first terminal of the first second resistor R12 grounded. The third pin IFB- of the first chip U1 is connected to the first terminal of the first fifth capacitor C15 and the second terminal of the first fourth resistor R14, with the first terminal of the first fourth resistor R14 grounded. The eighth pin VINFB of the first chip U1 is connected to the second terminal of the first sixth resistor R16, the first terminal of the first sixth capacitor C16, and the first terminal of the first seventh resistor R17; the first terminal of the first sixth resistor R16 is connected to the second power supply voltage, and the second terminals of the first sixth capacitor C16 and the second terminals of the first seventh resistor R17 are grounded.

[0117] The ninth pin (RSTN) of the first chip U1 is connected to the first terminal of the first capacitor C17, and the second terminal of the first capacitor C17 is grounded. The first zero pin (AVSS) of the first chip U1 is grounded. The first pin (AVDD) of the first chip U1 is connected to the fifth power supply voltage and the first terminal of the first capacitor C19, and the second terminal of the first capacitor C19 is grounded. The first second pin (LDO15) of the first chip U1 is connected to the first terminal of the second capacitor C21, and the second terminal of the second capacitor C21 is grounded. The first third pin (VOUTFB) of the first chip U1 is connected to the first terminal of the second resistor R23, the first terminal of the second capacitor C22, and the first terminal of the second zero resistor R20, respectively. The second terminals of the second resistor R23 and the second terminal of the second capacitor C22 are grounded. The first four pins of the first chip U1, TFB pin, are respectively connected to the first terminal of the first negative temperature coefficient resistor NTR1, the first terminal of the second three capacitors C23, and the first terminal of the second one resistor R21. The second terminals of the first negative temperature coefficient resistor NTR1 and the second three capacitors C23 are respectively grounded.

[0118] The collector of the fifth transistor V5 is connected to the second power supply voltage and the first terminal of the first eight-resistor R18. The base of the fifth transistor V5 is connected to the second terminal of the first eight-resistor R18, the first terminal of the first eight-capacitor C18, and the cathode of the eighth diode D8. The second terminal of the first eight-capacitor C18 and the anode of the eighth diode D8 are grounded. The emitter of the fifth transistor V5 is connected to the anode of the ninth diode D9. The cathode of the ninth diode D9 is connected to the cathode of the first zero-diode D10 and the first terminal of the second two-resistor R22.

[0119] The first pin (VIN) of the second chip U2 is connected to the second terminal of the second resistor R22 and the second terminal of the second zero capacitor C20, with the first terminal of the second zero capacitor C20 grounded. The second pin (VO1) of the second chip U2 is connected to the fifth power supply voltage and the first terminal of the second five capacitor C25, with the second terminal of the second five capacitor C25 grounded. The eighth pin (VO2) of the second chip U2 is connected to the third power supply voltage and the first terminal of the second four capacitor C24, with the second terminal of the second four capacitor C24 grounded.

[0120] Figure 4 This is a circuit diagram of the battery voltage acquisition circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 4 In one embodiment of this utility model, the battery voltage acquisition circuit includes a fourth chip U4, a third eighth capacitor C38, a third ninth capacitor C39, a first first Zener diode Z11, a first second Zener diode Z12, a first sixth Zener diode Z16, a third first resistor R31, a third second resistor R32, a third third resistor R33, a third fourth resistor R34, a third fifth resistor R35, a third sixth resistor R36, a third seventh resistor R37, a third eighth resistor R38, a fourth third resistor R43, and a fourth fourth resistor R44.

[0121] The first pin of the fourth chip U4 is connected to the first terminal of the third-fourth resistor R34; the third pin of the fourth chip U4 is connected to the first terminal of the third-second resistor R32; and the second terminal of the third-fourth resistor R34 is connected to the second terminal of the third-second resistor R32. The fifth pin of the fourth chip U4 is connected to the battery voltage through the third-first resistor R31; the seventh pin of the fourth chip U4 is connected to the third-third resistor R33; the sixth pin of the fourth chip U4 is connected to the first terminal of the third-sixth resistor R36; the eighth pin of the fourth chip U4 is connected to the first terminal of the third-seventh resistor R37; and the second terminal of the third-sixth resistor R36 is connected to the first terminal of the third-eighth resistor R38.

[0122] The second terminal of the third-seventh resistor R37 is connected to the first terminal of the third-eighth capacitor C38, the first terminal of the fourth-third resistor R43, and the negative terminal of the first-second Zener diode Z12; the positive terminal of the first-second Zener diode Z12 is grounded. The second terminal of the third-eighth resistor R38 is connected to the first terminal of the third-ninth capacitor C39, the first terminal of the fourth-fourth resistor R44, and the negative terminal of the first-first Zener diode Z11; the positive terminal of the first-first Zener diode Z11 is grounded. The second terminal of the third-eighth capacitor C38 is connected to the second terminal of the fourth-third resistor R43, the second terminal of the third-ninth capacitor C39, the second terminal of the fourth-fourth resistor R44, and the first terminal of the third-fifth resistor R35; the second terminal of the third-fifth resistor R35 is connected to the negative terminal of the first-hexa Zener diode Z16; the positive terminal of the first-hexa Zener diode Z16 is grounded.

[0123] Figure 5a , Figure 5b This is a circuit diagram of the battery switching circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 5a , Figure 5b In one embodiment of this utility model, the battery switching circuit includes a fifth chip U5, a first transistor MD1, a second transistor MD2, a third transistor MD3, a fourth transistor MD4, a seventh MOSFET M7, a third capacitor C33, a third capacitor C34, a third capacitor C35, a third capacitor C36, a third capacitor C37, an eighth capacitor C85, an eighth capacitor C86, a third resistor R39, a fourth resistor R40, a fourth resistor R41, a fourth resistor R42, a ninth resistor R99, a first zero resistor R100, a first zero resistor R101, a first zero resistor R102, a first zero resistor R108, a first zero resistor R109, a first zero resistor R110, a first one resistor R111, and a first one three resistor R113.

[0124] The first pin of the fifth chip U5 is connected to the second terminal of the third capacitor C36. The first terminal of the third capacitor C36 is connected to the second terminal of the first resistor R110, the second terminal of the third capacitor C37, and the second pin of the fifth chip U5. The first zero pin of the fifth chip U5 is connected to the first terminal of the first resistor R111. The second terminal of the first resistor R111 is connected to the first terminal of the first resistor R113, and the second terminal of the first resistor R113 is grounded. The first pin of the fifth chip U5 is connected to the second terminal of the first resistor R108 and the first terminal of the eighth capacitor C86, and the second terminal of the eighth capacitor C86 is grounded. The first two pins of the fifth chip U5 are connected to the second terminals of the first resistor R102, the second terminal of the fourth resistor R42, and the second terminal of the ninth resistor R99; the fourth pin of the fifth chip U5 is connected to the second terminal of the first resistor R101. The first and sixth pins of the fifth chip U5 are respectively connected to the second end of the fourth resistor R41, the second end of the first zero-nine resistor R109, and the second end of the first zero-zero resistor R100.

[0125] The first terminal of the first zero-resistance R110 is connected to the battery voltage, the first terminal of the third three-capacitor C33, the first terminal of the third nine-resistance R39, the emitter of the first transistor MD1, the emitter of the third transistor MD3, and the first terminal of the fourth resistor R41. The second terminal of the third three-capacitor C33 is connected to the first terminal of the third four-capacitor C34. The second terminal of the third four-capacitor C34 is connected to the first terminal of the third five-capacitor C35, the first terminal of the first zero-eight resistor R108, the first terminal of the ninth nine-resistance R99, the emitter of the fourth transistor MD4, and the emitter of the second transistor MD2. The collector of the fourth transistor MD4 is grounded, and the base of the fourth transistor MD4 is connected to the first terminal of the fourth two resistor R42. The collector of the second transistor MD2 is grounded, and the base of the second transistor MD2 is connected to the first terminal of the first zero-two resistor R102. The second terminal of the third nine-resistor R39 is connected to the drain of the seventh MOSFET M7. The gate of the seventh MOSFET M7 is connected to the first terminal of the first zero-one resistor R101 and the first terminal of the fourth zero resistor R40. The source of the seventh MOSFET M7 and the second terminal of the fourth zero resistor R40 are grounded. The collector of the first transistor MD1 is grounded, and the base of the first transistor MD1 is connected to the first terminal of the first zero-zero resistor R100. The collector of the third transistor MD3 is grounded, and the base of the third transistor MD3 is connected to the first terminal of the first zero-nine resistor R109.

[0126] Figure 6 This is a circuit diagram of the AC detection circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 6In one embodiment of this utility model, the AC detection circuit includes a first operational amplifier OP1, a first seven diode D17, a first zero three resistor R103, a first zero four resistor R104, a first zero five resistor R105, a first zero six resistor R106, and a first zero seven resistor R107.

[0127] The fourth terminal of the first operational amplifier OP1 is connected to the second terminal of the first zero-three resistor R103, and the third terminal of the first operational amplifier OP1 is grounded. The first terminal of the first operational amplifier OP1 is connected to the cathode of the first seven diode D17 and the first terminal of the first zero-four resistor R104, and the second terminal of the first zero-four resistor R104 is connected to the first terminal of the first zero-five resistor R105. The second terminal of the first operational amplifier OP1 is connected to the anode of the first seven diode D17 and the first terminal of the first zero-six resistor R106, and the second terminal of the first zero-six resistor R106 is connected to the first terminal of the first zero-seven resistor R107.

[0128] Figure 7a , Figure 7b This is a circuit diagram of the motor control circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 7a , Figure 7b In one embodiment of this utility model, the motor control circuit includes a third AC contactor CJ3, a sixth MOSFET M6, a first 8-diode D18, an eighth 9-capacitor C89, and a first 1 / 2 resistor R112. The first terminal of the third AC contactor CJ3 is connected to the negative terminal of the first 8-diode D18, and the second terminal of the third AC contactor CJ3 is connected to the positive terminal of the first 8-diode D18 and the drain of the sixth MOSFET M6. The source of the sixth MOSFET M6 is grounded. The gate of the sixth MOSFET M6 is connected to the second terminal of the first 1 / 2 resistor R112 and the first terminal of the eighth 9-capacitor C89. The second terminal of the eighth 9-capacitor C89 is grounded.

[0129] The substation emergency backup power system may include a communication interface circuit 9. Figure 8 This is a circuit diagram of the communication interface circuit in one embodiment of the present invention; please refer to [link / reference]. Figure 8 In one embodiment of this utility model, the communication interface circuit includes a first fifth chip U15, a fifth transistor Q5, a first third TVS diode Z13, a first fourth varistor Z14, a first fifth varistor Z15, a ninth sixth capacitor C96, a ninth seventh capacitor C97, a ninth eighth capacitor C98, and several resistors. The connection relationship of each component is as follows: Figure 8 As shown.

[0130] Figures 9a to 9m This is a circuit diagram of the main control circuit (including the current acquisition circuit) in one embodiment of the present invention; please refer to [link / reference]. Figures 9a to 9mIn one embodiment of this utility model, the main control circuit (including a current acquisition circuit) includes an eighth chip U8, a ninth chip U9, a first zero chip U10, a first one chip U11, a first two chip U12, a first three chip U13, a first four chip U14, a first six chip U16, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a first TVS diode Z1, a third TVS diode Z3, a sixth TVS diode Z6, several varistors, several capacitors, and several resistors. The connection relationship of each component is as follows: Figures 9a to 9m As shown.

[0131] This utility model further discloses a substation power outage control system, which includes the aforementioned substation emergency backup power supply system.

[0132] In one embodiment of the present invention, the substation power outage control system further includes a drive mechanism and a substation high-voltage switch, wherein the drive mechanism is connected to the substation high-voltage switch.

[0133] In summary, the substation emergency backup power supply system and substation power outage control system proposed in this utility model can improve the safety and intelligence of substation power outage shutdown.

[0134] This system primarily addresses the need to maintain control of power structures and ensure power supply to network equipment even in abnormal power plant conditions. It enables remote data exchange when equipment is functioning normally and sends abnormal data to the backend management center when equipment malfunctions. To achieve this, the equipment must have its own battery, requiring battery management; it must also have its own AC-DC power supply with power allocation capabilities; and the equipment must be capable of manual operation and provide alarms for any abnormalities.

[0135] This system ensures the integrity of power plant equipment data reporting, allowing the back-end control center to be aware of abnormal data immediately. Secondly, the use of this equipment eliminates the need for maintenance personnel to carry external power supplies, reducing their workload. Finally, the use of this equipment reduces the operation time for equipment maintenance and repair, which is of positive significance for ensuring power supply and for social production.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The description and application of this utility model herein are illustrative and not intended to limit the scope of the utility model to the above embodiments. The effects or advantages involved in the embodiments may not be manifested in the embodiments due to various factors, and the description of effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be clear to those skilled in the art that this utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of this utility model. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of this utility model.

Claims

1. A substation emergency backup power system, characterized by, The substation emergency backup power system includes: a main control circuit, an AC-to-DC circuit, an auxiliary power supply, a battery module, a constant current charging circuit, a battery voltage acquisition circuit, a battery switching circuit, and a motor control circuit. The main control circuit is connected to the AC to DC circuit, auxiliary power supply, constant current charging circuit, battery voltage acquisition circuit, battery switching circuit and motor control circuit respectively. The AC-to-DC circuit is used to convert AC power into DC power; the AC-to-DC circuit is connected to the auxiliary power supply and the constant current charging circuit respectively, providing DC power to the auxiliary power supply and the constant current charging circuit; the auxiliary power supply provides DC power to the auxiliary equipment; The battery voltage acquisition circuit is used to acquire the voltage data of the battery module. The output terminal of the battery voltage acquisition circuit is connected to the input terminal of the main control circuit, and the acquired voltage data is sent to the main control circuit. The output terminal of the main control circuit is connected to the input terminal of the battery switching circuit, and can send a power switching control signal to the battery switching circuit. The battery switching circuit is connected to the battery module and can control the battery module to start supplying power; the constant current charging circuit is connected to the battery module and can charge the battery module. The output terminal of the main control circuit is connected to the input terminal of the motor control circuit, and can send control signals to the motor control circuit; the motor control circuit is connected to a drive mechanism, which is connected to the substation high-voltage switch, and can control the switching action of the substation high-voltage switch.

2. The substation emergency backup power supply system according to claim 1, characterized in that: The substation emergency backup power system further includes an AC detection circuit, which is used to detect the presence of AC power. The output of the AC detection circuit is connected to the input of the main control circuit, and the detected signal is sent to the main control circuit.

3. The substation emergency backup power supply system according to claim 1, characterized in that: The substation emergency backup power system further includes at least one control button, and each control button is connected to the main control circuit.

4. The substation emergency backup power supply system according to claim 1, characterized in that: The substation emergency backup power system further includes a display module, which is used to display setting information; The display module is connected to the main control circuit.

5. The substation emergency backup power supply system according to claim 1, characterized in that: The constant current charging circuit includes a third chip U3, a sixth chip U3, a second MOSFET M2, a second AC contactor CJ2, a second inductor L2, a third inductor L3, a first diode D11, a first second Schottky diode D12, a first third Schottky diode D13, a first fourth diode D14, a first capacitor C1, a second sixth capacitor C26, a second seventh capacitor C27, a second eighth capacitor C28, a second ninth capacitor C29, a third zero capacitor C30, a third first capacitor C31, a third second capacitor C32, a second fourth resistor R24, a second fifth resistor R25, a second sixth resistor R26, a second seventh resistor R27, a second eighth resistor R28, a second ninth resistor R29, a third zero resistor R30, a first 114 resistor R114, a first 115 resistor R115, a first 116 resistor R116, a first 117 resistor R117, a first 118 resistor R118, and a first 119 resistor R119. The first terminal of the second AC contactor CJ2 is connected to the first terminal of the second four resistor R24. The second terminal of the second four resistor R24 ​​is connected to the third terminal of the second AC contactor CJ2, the first terminal of the second six capacitor C26, the first terminal of the second seven capacitor C27, the first terminal of the second seven resistor R27, and the first terminal of the third inductor L3. The fourth terminal of the second AC contactor CJ2 is connected to the positive terminal of the first four diode D14 and the drain of the second MOSFET M2. The gate of the second MOSFET M2 is connected to the second terminal of the second six resistor R26 and the first terminal of the second nine capacitor C29. The second terminal of the second nine capacitor C29 is grounded, and the source of the second MOSFET M2 is grounded. The second terminal of the second sixth capacitor C26 is connected to the second terminal of the second seventh capacitor C27, and the second terminal of the third inductor L3 is connected to the third pin of the third chip U3 and the first terminal of the third second capacitor C32, respectively. The second end of the second seven resistor R27 is connected to the fourth pin of the third chip U3, the first end of the second eight capacitor C28, and the first end of the second eight resistor R28. The second end of the second eight resistor R28 is connected to the second pin of the third chip U3 and the first end of the third zero resistor R30. The second terminal of the third capacitor C32 is connected to the first terminal of the second inductor L2, the first terminal of the first Schottky diode D12, and the third terminal of the first Schottky diode D12, respectively; the second terminal of the first Schottky diode D12 is connected to the first terminal of the second resistor R25, the first terminal of the third zero capacitor C30, the first terminal of the third one capacitor C31, the first terminal of the first three Schottky diode D13, and the third terminal of the first three Schottky diode D13, respectively; the second terminal of the first three Schottky diode D13 is connected to the battery module. The fifth pin of the third chip U3 is connected to the second terminal of the second five resistor R25, the first terminal of the second nine resistor R29, and the negative terminal of the first one diode D11; the second terminal of the second nine resistor R29 is connected to the second terminal of the third zero capacitor C30 and the second terminal of the third one capacitor C31. The first pin of the sixth chip U6 is connected to the second terminal of the first 115 resistor R115, and the third pin of the sixth chip U6 is connected to the second terminal of the first 18 resistor R118, the second terminal of the first 17 resistor R117, and the first terminal of the first 19 resistor R119, respectively; the first terminal of the first 18 resistor R118 is grounded, the second terminal of the first 19 resistor R119 is grounded, and the second pin of the sixth chip U6 is grounded. The fourth pin of the sixth chip U6 is connected to the first end of the first 117 resistor R117 and the first end of the first 116 resistor R116, and the second end of the first 116 resistor R116 is connected to the positive terminal of the first diode D11.

6. The substation emergency backup power supply system according to claim 1, characterized in that: The auxiliary power supply includes a first chip U1, a second chip U2, a first transistor V1, a second transistor V2, a third transistor V3, a fourth transistor V4, a fifth transistor V5, a first MOSFET M1, a first AC contactor CJ1, a first inductor L1, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8, a ninth diode D9, a first zero diode D10, a second capacitor C2, a third capacitor C3, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a first zero capacitor C10, a first first capacitor C11, a first second capacitor C12, a first third capacitor C13, a first fourth capacitor C14, and a first fifth capacitor C15. Capacitor C15, First Eighth Capacitor C18, First Ninth Capacitor C19, Second Zero Capacitor C20, Second First Capacitor C21, Second Second Capacitor C22, Second Third Capacitor C23, Second Fourth Capacitor C24, Second Fifth Capacitor C25, First Resistor R1, Second Resistor R2, Third Resistor R3, Fourth Resistor R4, Fifth Resistor R5, Sixth Resistor R6, Seventh Resistor R7, Eighth Resistor R8, Ninth Resistor R9, First Zero Resistor R10, First First Resistor R11, First Second Resistor R12, First Third Resistor R13, First Fourth Resistor R14, First Fifth Resistor R15, First Sixth Resistor R16, First Seventh Resistor R17, First Eighth Resistor R18, First Ninth Resistor R19, Second Zero Resistor R20, Second First Resistor R21, First Negative Temperature Coefficient Resistor NTR1, First Fuse F1; The first terminal of the first fuse device F1 is connected to the first power supply voltage, the second terminal of the first fuse device F1 is connected to the first terminal of the first AC contactor CJ1, and the third terminal of the first AC contactor CJ1 is connected to the first terminal of the first zero capacitor C10, the first terminal of the first capacitor C11, the first terminal of the second capacitor C2, the second power supply voltage, and the collector of the first transistor V1, respectively; the second terminals of the first zero capacitor C10, the first capacitor C11, and the second capacitor C2 are respectively grounded. The fourth terminal of the first AC contactor CJ1 is connected to the positive terminal of the fourth diode D4 and the drain of the first MOSFET M1, respectively. The gate of the first MOSFET M1 is connected to the second terminal of the seventh resistor R7 and the first terminal of the ninth capacitor C9, respectively. The second terminal of the ninth capacitor C9 is grounded, and the source of the first MOSFET M1 is grounded. The gate of the first transistor V1 is connected to the negative terminal of the first diode D1 and the second terminal of the third resistor R3, respectively. The positive terminal of the first diode D1 is connected to the second terminal of the first resistor R1. The first terminal of the first resistor R1 is connected to the first terminal of the third resistor R3 and the third pin HO1 of the first chip U1. The emitter of the first transistor V1 is connected to the collector of the second transistor V2, the VS1 pin of the first chip U1, the first terminal of the first capacitor C12, the first terminal of the seventh capacitor C7, and the first terminal of the first inductor L1. The base of the second transistor V2 is connected to the cathode of the third diode D3 and the second terminal of the ninth resistor R9. The anode of the third diode D3 is connected to the second terminal of the fifth resistor R5. The first terminal of the fifth resistor R5 is connected to the first terminal of the ninth resistor R9 and the second and third pins LO1 of the first chip U1. The emitter of the second transistor V2 is grounded. The second terminals of the first two capacitors C12 are respectively connected to the negative terminal of the seventh diode D7 and the third pin VB1 of the first chip U1; the positive terminal of the seventh diode D7 is connected to the third power supply voltage; the second terminal of the seventh capacitor C7 is connected to the first terminal of the first resistor R11, and the second terminal of the first resistor R11 is grounded. The second end of the first inductor L1 is connected to the first end of the eighth capacitor C8, the second seventh pin VS2 of the first chip U1, the second end of the first triple capacitor C13, the emitter of the third transistor V3, and the collector of the fourth transistor V4. The second terminal of the eighth capacitor C8 is connected to the first terminal of the first three resistors R13, and the second terminal of the first three resistors R13 is grounded; the second nine-pin VB2 of the first chip U1 is connected to the first terminal of the first three capacitors C13 and the negative terminal of the sixth diode D6, respectively, and the positive terminal of the sixth diode D6 is connected to the third power supply voltage. The collector of the third transistor V3 is connected to the fourth power supply voltage, the first terminal of the fifth capacitor C5, the first terminal of the third capacitor C3, and the first terminal of the sixth capacitor C6, respectively; the second terminals of the fifth capacitor C5 and the second terminals of the third capacitor C3 are grounded; the second terminal of the sixth capacitor C6 is connected to the first terminal of the eighth resistor R8, and the second terminal of the eighth resistor R8 is grounded. The base of the third transistor V3 is connected to the positive terminal of the second diode D2 and the first terminal of the fourth resistor R4, respectively. The negative terminal of the second diode D2 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the second terminal of the fourth resistor R4 and the second octet HO2 of the first chip U1. The base of the fourth transistor V4 is connected to the positive terminal of the fifth diode D5 and the first terminal of the first zero resistor R10. The negative terminal of the fifth diode D5 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the second terminal of the first zero resistor R10 and the LO2 pin of the first chip U1. The emitter of the fourth transistor V4 is grounded. The first pin VDD1 of the first chip U1 is connected to the third power supply voltage and the second terminal of the first four capacitors C14, and the first terminal of the first four capacitors C14 is grounded. The second pin IFB+ of the first chip U1 is connected to the second terminal of the first five capacitor C15 and the second terminal of the first five resistor R15 respectively; the first terminal of the first five resistor R15 is connected to the second terminal of the first two resistor R12, and the first terminal of the first two resistor R12 is grounded. The third pin IFB- of the first chip U1 is connected to the first terminal of the first five capacitor C15 and the second terminal of the first four resistor R14, respectively. The first terminal of the first four resistor R14 is grounded. The eighth pin VINFB of the first chip U1 is connected to the second end of the first six resistor R16, the first end of the first six capacitor C16, and the first end of the first seven resistor R17, respectively; the first end of the first six resistor R16 is connected to the second power supply voltage, and the second ends of the first six capacitor C16 and the second ends of the first seven resistor R17 are grounded, respectively. The ninth pin RSTN of the first chip U1 is connected to the first terminal of the first capacitor C17, and the second terminal of the first capacitor C17 is grounded; the first zero pin AVSS of the first chip U1 is grounded. The first pin AVDD of the first chip U1 is connected to the fifth power supply voltage and the first terminal of the first capacitor C19, and the second terminal of the first capacitor C19 is grounded. The first two pins of the first chip U1, LDO15, are connected to the first terminal of the second capacitor C21, and the second terminal of the second capacitor C21 is grounded. The first three pins of the first chip U1, VOUTFB, are respectively connected to the first end of the second three resistor R23, the first end of the second two capacitor C22, and the first end of the second zero resistor R20. The second end of the second three resistor R23 and the second end of the second two capacitor C22 are respectively grounded. The first four pins of the first chip U1, TFB pin, are respectively connected to the first terminal of the first negative temperature coefficient resistor NTR1, the first terminal of the second three capacitors C23, and the first terminal of the second one resistor R21. The second terminals of the first negative temperature coefficient resistor NTR1 and the second three capacitors C23 are respectively grounded. The collector of the fifth transistor V5 is connected to the second power supply voltage and the first terminal of the first eight resistor R18, respectively. The base of the fifth transistor V5 is connected to the second terminal of the first eight resistor R18, the first terminal of the first eight capacitor C18, and the negative terminal of the eighth diode D8, respectively. The second terminal of the first eight capacitor C18 and the positive terminal of the eighth diode D8 are grounded. The emitter of the fifth transistor V5 is connected to the positive terminal of the ninth diode D9, and the negative terminal of the ninth diode D9 is connected to the negative terminal of the first diode D10 and the first terminal of the second resistor R22. The first pin VIN of the second chip U2 is connected to the second terminal of the second resistor R22 and the second terminal of the second zero capacitor C20, respectively, and the first terminal of the second zero capacitor C20 is grounded. The second pin VO1 of the second chip U2 is connected to the fifth power supply voltage and the first terminal of the second capacitor C25, and the second terminal of the second capacitor C25 is grounded. The eighth pin VO2 of the second chip U2 is connected to the third power supply voltage and the first terminal of the second fourth capacitor C24, and the second terminal of the second fourth capacitor C24 is grounded.

7. The substation emergency backup power supply system according to claim 1, characterized in that: The battery voltage acquisition circuit includes a fourth chip U4, a third eighth capacitor C38, a third ninth capacitor C39, a first first Zener diode Z11, a first second Zener diode Z12, a first sixth Zener diode Z16, a third first resistor R31, a third second resistor R32, a third third resistor R33, a third fourth resistor R34, a third fifth resistor R35, a third sixth resistor R36, a third seventh resistor R37, a third eighth resistor R38, a fourth third resistor R43, and a fourth fourth resistor R44. The first pin of the fourth chip U4 is connected to the first end of the third resistor R34, the third pin of the fourth chip U4 is connected to the first end of the third resistor R32, and the second end of the third resistor R34 is connected to the second end of the third resistor R32. The fifth pin of the fourth chip U4 is connected to the battery voltage through the third resistor R31; the seventh pin of the fourth chip U4 is connected to the third resistor R33. The sixth pin of the fourth chip U4 is connected to the first end of the third six resistor R36, and the eighth pin of the fourth chip U4 is connected to the first end of the third seven resistor R37; the second end of the third six resistor R36 is connected to the first end of the third eight resistor R38. The second terminal of the third resistor R37 is connected to the first terminal of the third capacitor C38, the first terminal of the fourth resistor R43, and the negative terminal of the first Zener diode Z12; the positive terminal of the first Zener diode Z12 is grounded. The second terminal of the third resistor R38 is connected to the first terminal of the third capacitor C39, the first terminal of the fourth resistor R44, and the negative terminal of the first Zener diode Z11; the positive terminal of the first Zener diode Z11 is grounded. The second terminal of the third eight capacitor C38 is connected to the second terminal of the fourth three resistor R43, the second terminal of the third nine capacitor C39, the second terminal of the fourth four resistor R44, and the first terminal of the third five resistor R35. The second terminal of the third five resistor R35 is connected to the negative terminal of the first six Zener diode Z16, and the positive terminal of the first six Zener diode Z16 is grounded.

8. The substation emergency backup power supply system according to claim 1, characterized in that: The battery switching circuit includes a fifth chip U5, a first transistor MD1, a second transistor MD2, a third transistor MD3, a fourth transistor MD4, a seventh MOSFET M7, a third capacitor C33, a third capacitor C34, a third capacitor C35, a third capacitor C36, a third capacitor C37, an eighth capacitor C85, an eighth capacitor C86, a third resistor R39, a fourth resistor R40, a fourth resistor R41, a fourth resistor R42, a ninth resistor R99, a first zero resistor R100, a first zero resistor R101, a first zero resistor R102, a first zero resistor R103, a first zero resistor R104, a first zero resistor R105, a first zero resistor R106, a first zero resistor R107, a first zero resistor R108, a first zero resistor R109, a first zero resistor R110, a first one-one resistor R111, and a first one-three resistor R113. The first pin of the fifth chip U5 is connected to the second terminal of the third six capacitor C36. The first terminal of the third six capacitor C36 is connected to the second terminal of the first zero resistor R110, the second terminal of the third seven capacitor C37, and the second pin of the fifth chip U5. The first zero pin of the fifth chip U5 is connected to the first end of the first resistor R111, the second end of the first resistor R111 is connected to the first end of the first resistor R113, and the second end of the first resistor R113 is grounded. The pins of the fifth chip U5 are respectively connected to the second end of the first zero-eight resistor R108 and the first end of the eighth six capacitor C86, and the second end of the eighth six capacitor C86 is grounded. The first and second pins of the fifth chip U5 are respectively connected to the second terminals of the first zero-two resistor R102, the second terminals of the fourth two resistor R42, and the second terminals of the ninth nine resistor R99; the fourth pin of the fifth chip U5 is connected to the second terminal of the first zero-one resistor R101. The first and sixth pins of the fifth chip U5 are respectively connected to the second end of the fourth resistor R41, the second end of the first zero-nine resistor R109, and the second end of the first zero-zero resistor R100. The first terminal of the first zero resistor R110 is connected to the battery voltage, the first terminal of the third capacitor C33, the first terminal of the third resistor R39, the emitter of the first transistor MD1, the emitter of the third transistor MD3, and the first terminal of the fourth resistor R41. The second end of the third capacitor C33 is connected to the first end of the third capacitor C34. The second end of the third capacitor C34 is connected to the first end of the third capacitor C35, the first end of the first resistor R108, the first end of the ninth resistor R99, the emitter of the fourth transistor MD4, and the emitter of the second transistor MD2. The collector of the fourth transistor MD4 is grounded, and the base of the fourth transistor MD4 is connected to the first terminal of the fourth resistor R42; the collector of the second transistor MD2 is grounded, and the base of the second transistor MD2 is connected to the first terminal of the first resistor R102. The second end of the third nine resistor R39 is connected to the drain of the seventh MOS transistor M7, and the gate of the seventh MOS transistor M7 is connected to the first end of the first zero-one resistor R101 and the first end of the fourth zero resistor R40; the source of the seventh MOS transistor M7 and the second end of the fourth zero resistor R40 are respectively grounded. The collector of the first transistor MD1 is grounded, and the base of the first transistor MD1 is connected to the first terminal of the first zero-zero resistor R100; the collector of the third transistor MD3 is grounded, and the base of the third transistor MD3 is connected to the first terminal of the first zero-nine resistor R109.

9. A substation power outage control system characterized by, The substation power outage control system includes the substation emergency backup power supply system as described in any one of claims 1 to 8.

10. The substation power outage control system according to claim 9, characterized in that: The substation power outage control system further includes a drive mechanism and a substation high-voltage switch, wherein the drive mechanism is connected to the substation high-voltage switch.

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