Electronic device and electronic apparatus

Abstract

The application discloses an electronic device and an electronic equipment. The electronic device comprises a carrier, a chip, at least one first wire and at least one second wire. The chip is arranged on the carrier. The first wire is connected with the chip and the carrier respectively. The two ends of the second wire are connected with the carrier respectively. The chip and the first wire are located between the second wire and the carrier. The cost of electromagnetic interference shielding can be reduced.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to electronic devices and electronic equipment. Background Technology

[0002] In existing technologies, when packaging chips, electromagnetic interference (EMI) shielding technology needs to be used in the packaging. For example, after the chip is placed on a carrier and the corresponding electrical connection is made, the chip is encapsulated to form an encapsulation layer. The encapsulation layer covers the chip to protect it and dissipate heat, forming a package. Finally, a metal layer is sputtered onto the surface of the package using specialized sputtering equipment to achieve EMI shielding and improve the stability of the chip during operation within the package.

[0003] The drawback of existing technologies is that while forming a metal layer through sputtering equipment can indeed achieve electromagnetic interference shielding, sputtering equipment is expensive and its use also complicates the packaging process, resulting in high costs for achieving electromagnetic interference shielding through existing technologies. Utility Model Content

[0004] The main technical problem addressed in this application is how to reduce the cost of electromagnetic interference shielding.

[0005] To solve the above-mentioned technical problems, the first technical solution adopted in this application is: an electronic device, comprising: a carrier; a chip disposed on the carrier; at least one first wire, the first wire connecting the chip and the carrier respectively; at least one second wire, the two ends of the second wire connecting the carrier respectively; the chip and the first wire are both located between the second wire and the carrier.

[0006] The carrier surface is the side of the carrier used to support the chip. The first region and the second region are regions respectively set on the carrier surface and located on both sides of the chip. One end of the second wire is set in the first region, and the other end of the second wire is set in the second region.

[0007] Among them, at least one second wire includes a first type wire and a second type wire, and the third region and the fourth region are regions respectively disposed on the carrier surface and located on both sides of the chip. The first region, the second region, the third region and the fourth region are arranged at intervals around the chip; one end of the first type wire is disposed in the first region and the other end of the first type wire is disposed in the second region; one end of the second type wire is disposed in the third region and the other end of the second type wire is disposed in the fourth region.

[0008] Among them, the line connecting one end of the first type of conductor to the other end of the first type of conductor is the first connecting line, and the line connecting one end of the second type of conductor to the other end of the second type of conductor is the second connecting line; all the first connecting lines are parallel to each other, all the second connecting lines are parallel to each other, and the first connecting lines and the second connecting lines intersect.

[0009] The first line is perpendicular to the second line.

[0010] The diameter of the second conductor is larger than that of the first conductor.

[0011] The electronic device also includes an encapsulating layer; the encapsulating layer is disposed on the side of the carrier facing the chip, and the encapsulating layer covers the chip, the first wire, and the second wire.

[0012] The supporting component is either a frame or a substrate.

[0013] Both ends of the second conductor are grounded.

[0014] To solve the above-mentioned technical problems, the second technical solution adopted in this application is: an electronic device, including the above-mentioned electronic components.

[0015] The beneficial effects of this application are as follows: Unlike the prior art, in the technical solution of this application, the electronic device includes a carrier, a chip, at least one first wire and at least one second wire. The chip is disposed on the carrier, the first wire connects the chip and the carrier respectively, and the two ends of the second wire are connected to the carrier respectively. The chip and the first wire are both located between the second wire and the carrier. Based on the above method, after the chip is placed on the carrier and electrically connected to at least one first wire, an electromagnetic interference (EMI) shielding layer is formed by setting at least one second wire. The chip and the first wire are both placed in the space between the EMI shielding layer and the carrier, so that the chip and its electrically connected first wire can be covered by the EMI shielding layer, thus achieving EMI shielding for the chip. Subsequently, only the chip and each wire need to be encapsulated to obtain an electronic device with EMI shielding capability. Since the wire bonding process of the second wire can be implemented in the same stage of the packaging process as the wire bonding process of the first wire, no additional equipment other than the equipment required for the packaging process is needed, nor is it necessary to use processes other than those required for the packaging process. This reduces the cost and complexity of EMI shielding in electronic devices, thereby reducing the cost of EMI shielding. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an embodiment of the electronic device of this application;

[0018] Figure 2 This is a schematic diagram of the structure of one embodiment of the carrier, chip, and first wire of this application;

[0019] Figure 3 This is one of the structural schematic diagrams of an embodiment of the carrier, chip, first wire, and second wire of this application;

[0020] Figure 4 This is a second schematic diagram of the structure of an embodiment of the carrier, chip, first wire, and second wire of this application;

[0021] Figure 5 This is a schematic diagram of the manufacturing process of an embodiment of the electronic device of this application;

[0022] Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of this application.

[0023] The attached figures are labeled as follows: 1, carrier; 11, solder ball; 2, chip; 3, first conductor; 4, second conductor; 5, encapsulation layer; 20, electronic device; 10, electronic component. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] This application discloses an electronic device, see [link to relevant documentation] Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the electronic device of this application, as shown below. Figure 1 As shown, the electronic device includes: a carrier 1, a chip 2, at least one first wire 3 and at least one second wire 4.

[0028] Chip 2 is mounted on carrier 1.

[0029] Specifically, the carrier 1 can be a guide wire frame, a substrate, or other components used to carry the chip. The specific type can be determined according to actual needs and is not limited here.

[0030] The first wire 3 connects the chip 2 and the carrier 1 respectively.

[0031] The chip 2 can be electrically connected to the carrier 1 via the first wire 3. Subsequently, electronic devices can be set up by placing the carrier 1 and electrically connecting it to the corresponding circuit board.

[0032] The two ends of the second conductor 4 are respectively connected to the carrier 1.

[0033] In this configuration, both chip 2 and the first wire 3 are located between the second wire 4 and the carrier 1.

[0034] Both ends of the second conductor 4 are grounded. In one example, the second conductor 4 can be electrically connected to the grounding pin on the carrier 1. One or more second conductors 4 with both ends grounded can be used in conjunction with the carrier 1 to cover the chip 2 and the first conductor 3 connected to it. That is, an electromagnetic interference shielding layer is formed based on the one or more second conductors 4 with both ends grounded, and electromagnetic interference shielding between the chip 2 outside and inside the electronic device is achieved based on the electromagnetic interference shielding layer.

[0035] Compared to traditional technologies that do not include a second wire 4, but instead use an encapsulation layer 5 to cover the chip 2, the first wire 3, and at least part of the carrier 1, and then sputter a metal layer on the outside of the encapsulation layer 5, the technical solution of this application allows for the wire bonding of the second wire 4 during the wire bonding process in the packaging process. This eliminates the need for an additional metal sputtering step in the packaging process, as well as the need for additional packaging equipment other than wire bonding. This reduces the complexity of the packaging process and the cost of equipment for electromagnetic interference shielding, thereby reducing the cost of electromagnetic interference shielding.

[0036] Unlike existing technologies, in the technical solution of this application, the electronic device includes a carrier, a chip, at least one first wire and at least one second wire. The chip is disposed on the carrier, the first wire connects the chip and the carrier respectively, and the two ends of the second wire are connected to the carrier respectively. The chip and the first wire are both located between the second wire and the carrier. Based on the above method, after the chip is placed on the carrier and electrically connected to at least one first wire, an electromagnetic interference (EMI) shielding layer is formed by setting at least one second wire. The chip and the first wire are both placed in the space between the EMI shielding layer and the carrier, so that the chip and its electrically connected first wire can be covered by the EMI shielding layer, thus achieving EMI shielding for the chip. Subsequently, only the chip and each wire need to be encapsulated to obtain an electronic device with EMI shielding capability. Since the wire bonding process of the second wire can be implemented in the same stage of the packaging process as the wire bonding process of the first wire, no additional equipment other than the equipment required for the packaging process is needed, nor is it necessary to use processes other than those required for the packaging process. This reduces the cost and complexity of EMI shielding in electronic devices, thereby reducing the cost of EMI shielding.

[0037] In one embodiment, see Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of one embodiment of the carrier, chip, and first wire of this application. Figure 3 This is a schematic diagram of one embodiment of the carrier, chip, first wire, and second wire of this application, as shown below. Figures 1 to 3 As shown, the bearing surface is the side of the bearing member 1 used to support the chip 2. The first region and the second region are regions respectively set on the bearing surface and located on both sides of the chip 2. One end of the second wire 4 is set in the first region, and the other end of the second wire 4 is set in the second region.

[0038] Specifically, such as Figure 1 and Figure 2 As shown, the first region can refer to region A, and the second region can refer to region B, in the case of... Figure 2 From the perspective shown, region A is located above chip 2, and region B is located below chip 2. That is, regions A and B are respectively located on both sides of chip 2, so that the electrical connection points of the two ends of the single second wire 4 to the carrier surface are respectively located on both sides of chip 2, so that chip 2 is located in the space between the second wire 4 and the carrier 1. The second wire 4 can protect chip 2 located in this space from electromagnetic interference shielding, thereby reducing the cost of electromagnetic interference shielding.

[0039] Optionally, see Figure 4 , Figure 4 This is a second schematic diagram of the structure of an embodiment of the carrier, chip, first wire, and second wire of this application, as shown below. Figure 4 As shown, at least one second conductor 4 includes a first type conductor and a second type conductor. The third region and the fourth region are regions respectively disposed on the bearing surface and located on both sides of the chip 2. The first region, the second region, the third region and the fourth region are arranged at intervals around the chip 2.

[0040] One end of the first type of conductor is located in the first region, and the other end of the first type of conductor is located in the second region.

[0041] One end of the second-class conductor is placed in the third region, and the other end of the second-class conductor is placed in the fourth region.

[0042] Specifically, such as Figure 3 As shown, the third region can refer to region C, and the fourth region can refer to region D, in the case of... Figure 3From the perspective shown, region A is located above chip 2, region B is located below chip 2, region C is located to the left of chip 2, and region D is located to the right of chip 2. That is, regions A and B are respectively located on both sides of chip 2, and regions C and D are also respectively located on both sides of chip 2. This allows the electrical connection points between the two ends of any second wire 4 and the carrier surface to be located on both sides of chip 2, so that chip 2 is located in the space between the second wire 4 and the carrier 1. The second wire 4 can protect chip 2 located in this space from electromagnetic interference shielding, reducing the cost of electromagnetic interference shielding.

[0043] Furthermore, such as Figure 3 As shown, the connection between one end of a Class I conductor and the other end of a Class I conductor is the first connection, and the connection between one end of a Class II conductor and the other end of a Class II conductor is the second connection.

[0044] The first connecting lines are parallel to each other, the second connecting lines are parallel to each other, and the first connecting lines intersect the second connecting lines.

[0045] Specifically, such as Figure 3 As shown, the first line is perpendicular to the second line.

[0046] By using intersecting or even perpendicular first and second lines, it is possible to form a structure based on multiple first and second lines, such as... Figure 3 The wire mesh shown is composed of various second conductors 4. This wire mesh can refer to the electromagnetic interference shielding layer formed by one or more second conductors 4 grounded at both ends, as mentioned above. It is used to protect the chip 2 between the wire mesh composed of various second conductors 4 and the carrier 1 from electromagnetic interference. Because the mesh structure of the wire mesh can better cover the chip, compared to... Figure 2 The electromagnetic interference shielding layer formed by the second conductor 4 shown can achieve a better electromagnetic interference shielding effect.

[0047] In one embodiment, the diameter of the second conductor 4 is larger than the diameter of the first conductor 3.

[0048] Specifically, by making the diameter of the second conductor 4 larger than that of the first conductor 3, the electromagnetic interference shielding effect of the electromagnetic interference shielding layer formed by the second conductor 4 can be improved, thereby further enhancing the reliability of the electromagnetic interference shielding.

[0049] In one embodiment, such as Figure 1 As shown, the electronic device also includes an encapsulating layer 5.

[0050] The encapsulation layer 5 is disposed on the side of the carrier 1 facing the chip 2, and the encapsulation layer 5 covers the chip 2, the first wire 3 and the second wire 4.

[0051] Specifically, the encapsulating layer 5 can completely encapsulate the chip 2, the first wire 3, and the second wire 4 to protect and dissipate heat, thus forming an electronic device.

[0052] In one embodiment, the support member 1 is a frame, or the support member 1 is a substrate.

[0053] Specifically, the frame can refer to a lead frame used to carry a chip.

[0054] The substrate may specifically have corresponding solder balls 11 for use when reflow soldering with the corresponding circuit board.

[0055] In one embodiment, the first conductor 3 and the second conductor 4 can both be copper wire, gold wire, or other types of conductors, which are not limited here.

[0056] It should be noted that, in one example, see Figure 5 , Figure 5 This is a schematic diagram of the manufacturing process of an embodiment of the electronic device of this application, as shown below. Figure 5 As shown, the manufacturing process of electronic devices may specifically include the following steps:

[0057] First, in the wire bonding step, the pads on the surface of the chip 2 are electrically connected to the corresponding pins of the carrier 1 through the first wire 3 to achieve bonding and establish a bridge between the internal circuit of the chip 2 and the external electrical connection.

[0058] Second, in the wire bonding step, the corresponding pins on both sides of the chip 2 on the carrier 1 are electrically connected by the second wire 4 so that the chip 2 is located between the second wire 4 and the carrier 1, thus constructing an electromagnetic interference shielding layer formed by the second wire 4.

[0059] Third, in the molding process, epoxy resin or other types of encapsulating materials are injected into the corresponding mold so that the encapsulating material wraps around the bonding structure of the chip 2 and each wire, forming a protective shell. After the encapsulation is cured, it can perform functions such as mechanical processing, moisture protection, dust protection and heat dissipation, and isolate the chip 2 from external environmental damage as much as possible.

[0060] Fourth, in the solder ball mounting step, when the carrier 1 is a substrate, solder balls 11 containing tin lead or lead-free can be set on the side of the substrate away from the chip 2 to form external electrical contacts. These solder balls 11 are used later when electronic devices need to be soldered onto the corresponding circuit boards.

[0061] Fifth, in the cutting step, the encapsulated wafer or panel is cut into individual packages to form multiple electronic devices, each containing at least one chip 2.

[0062] Based on the above method, the electronic device can be constructed.

[0063] This application also proposes an electronic device, see [link to document]. Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device of this application, as shown below. Figure 6 As shown, the electronic device 20 includes electronic components 10.

[0064] Specifically, the electronic device 10 can be a microcontroller, a functional device, or other types of electronic devices, which are not limited here.

[0065] Unlike existing technologies, in the technical solution of this application, the electronic device includes a carrier, a chip, at least one first wire and at least one second wire. The chip is disposed on the carrier, the first wire connects the chip and the carrier respectively, and the two ends of the second wire are connected to the carrier respectively. The chip and the first wire are both located between the second wire and the carrier. Based on the above method, after the chip is placed on the carrier and electrically connected to at least one first wire, an electromagnetic interference (EMI) shielding layer is formed by setting at least one second wire. The chip and the first wire are both placed in the space between the EMI shielding layer and the carrier, so that the chip and its electrically connected first wire can be covered by the EMI shielding layer, thus achieving EMI shielding for the chip. Subsequently, only the chip and each wire need to be encapsulated to obtain an electronic device with EMI shielding capability. Since the wire bonding process of the second wire can be implemented in the same stage of the packaging process as the wire bonding process of the first wire, no additional equipment other than the equipment required for the packaging process is needed, nor is it necessary to use processes other than those required for the packaging process. This reduces the cost and complexity of EMI shielding in electronic devices, thereby reducing the cost of EMI shielding.

[0066] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An electronic device, characterized in that, include: Load-bearing components; The chip is disposed on the carrier; At least one first wire, the first wire being connected to the chip and the carrier respectively; At least one second conductor, with its two ends respectively connected to the carrier; The chip and the first wire are both located between the second wire and the carrier.

2. The electronic device according to claim 1, characterized in that, The bearing surface is the side of the bearing member used to support the chip. The first region and the second region are regions respectively disposed on the bearing surface and located on both sides of the chip. One end of the second wire is disposed in the first region, and the other end of the second wire is disposed in the second region.

3. The electronic device according to claim 2, characterized in that, The at least one second conductor includes a first type of conductor and a second type of conductor. The third region and the fourth region are regions respectively disposed on the bearing surface and located on both sides of the chip. The first region, the second region, the third region and the fourth region are arranged at intervals around the chip. One end of the first type of wire is disposed in the first region, and the other end of the first type of wire is disposed in the second region; One end of the second type of conductor is located in the third region, and the other end of the second type of conductor is located in the fourth region.

4. The electronic device according to claim 3, characterized in that, The connection between one end of the first type of conductor and the other end of the first type of conductor is the first connection, and the connection between one end of the second type of conductor and the other end of the second type of conductor is the second connection; The first connecting lines are parallel to each other, the second connecting lines are parallel to each other, and the first connecting lines intersect the second connecting lines.

5. The electronic device according to claim 4, characterized in that, The first line is perpendicular to the second line.

6. The electronic device according to any one of claims 1 to 5, characterized in that, The diameter of the second conductor is larger than that of the first conductor.

7. The electronic device according to any one of claims 1 to 5, characterized in that, The electronic device also includes an encapsulating layer; The encapsulating layer is disposed on the side of the carrier facing the chip, and the encapsulating layer covers the chip, the first wire, and the second wire.

8. The electronic device according to any one of claims 1 to 5, characterized in that, The support member is a frame, or the support member is a substrate.

9. The electronic device according to any one of claims 1 to 5, characterized in that, Both ends of the second conductor are grounded.

10. An electronic device, characterized in that, Includes the electronic device as described in any one of claims 1 to 9.

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