A device and method for collecting boc i2c data
By combining the main control board CPU and the sub-control board PCA9548A chip, the electromagnetic interference problem of multi-channel I2C data acquisition in complex circuit systems is solved, realizing efficient and low-cost acquisition and long-distance transmission of hundreds of I2C data channels.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THE 34TH RES INST OF CHINA ELECTRONICS TECH CORP
- Filing Date
- 2022-11-15
- Publication Date
- 2026-06-23
AI Technical Summary
Existing technologies cannot effectively acquire multiple I2C data streams. Especially in complex circuit systems, acquiring multiple I2C data streams can cause electromagnetic interference, affecting high-speed data transmission, and cannot meet the demand for efficient real-time acquisition of hundreds of data streams.
The system adopts a structure of main control board CPU and sub-control board PCA9548A chip. It realizes the acquisition of 120 channels of I2C data through address encoding and reset control. It uses GD32F450 processor and PCA9548A chip for address encoding and reset, and combined with the support of SDRAM and FLASH chips, it ensures that data acquisition does not affect the transmission of other signals.
It enables efficient acquisition of hundreds of I2C data streams from complex circuit systems, avoids electromagnetic interference, improves data acquisition efficiency and quantity, and supports long-distance data transmission.
Smart Images
Figure CN115712595B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to I2C data acquisition technology for ultra-large capacity and long-distance applications in complex circuit systems, specifically a device and method capable of acquiring hundreds of I2C data streams. Background Technology
[0002] The I2C bus, developed by Philips, is a bidirectional, two-wire bus that enables control between chips. Also known as the Inter-IC bus, it solves the interconnection problem between the following circuits:
[0003] 1) Intelligent control of other chips by microprocessors; 2) Various sensors, LCD drivers, remote I / O ports, RAM, EPROM, or digital-to-analog converters; 3) Digital tuning and signal processing circuits for radios and video systems, or DTMF generators for audio dial telephones. The I2C bus consists of two lines: a serial data line SDA (Serial Data) and a serial clock line SCL (Serial Clock). Both lines are connected to the positive power supply through a pull-up resistor and remain high when the bus is not busy. Each device on the bus has a unique address. These devices can be microprocessors, LCD drivers, memory, or A / D chips. Depending on their function, they can act as master or slave devices on a single I2C bus. The I2C bus typically operates at speeds of 0–400 kbit / s, with high levels exceeding 0.7 * VDD and low levels falling below 0.3 * VDD. The maximum current is 3 mA. Devices from different manufacturing processes, including CMOS, NMOS, and bipolar devices, may be connected to the I2C bus. The logic '0' and logic '1' levels are not fixed and depend on the actual level of VDD.
[0004] The timing diagram of the transmission process of single-channel I2C data between the master and slave in the existing technology is as follows: Figure 1 As shown, when each serial clock pulse SCL occurs, the serial data bus SDA transmits one data bit. During the high-level period of the clock signal, the data bit on the serial data bus SDA should remain stable. If the data on the serial data bus SDA changes during this period, it is considered a control signal for the bus. The change in the serial data bus SDA level from high to low when the serial clock pulse SCL is high serves as the bus start condition, and the change in the serial data bus SDA level from low to high when the serial clock pulse SCL is high serves as the bus stop condition. (See below) Figure 1 The bus will be busy for a short period of time after the start and stop conditions.
[0005] The start and stop conditions are generated by the host. There is no limit to the amount of data transmitted between the start and stop conditions, and each byte of data transmitted is 8 bits.
[0006] The most significant bit is transmitted first, followed by the other bits in sequence, and finally an acknowledge bit is transmitted (after the slave has finished transmitting). The clock pulse for the acknowledge bit is generated by the master. When the clock pulse corresponding to the acknowledge bit appears, the slave that generated the acknowledge bit will pull the SDA line low, and the master will release the SDA line. The slave must send an acknowledge signal after receiving each byte of data, and the master must also send an acknowledge signal after receiving data sent by the slave. If the slave cannot receive data immediately, it will pull the SCL line low, forcing the transmitter to enter a wait state.
[0007] Currently, I2C data signal acquisition technology is basically single-channel or multi-channel, and the slave device's I2C address is always the same fixed value or a few fixed values. However, with the increasing intelligence requirements of devices, the demands for the acquisition and control of various internal information states are growing. Dozens or even hundreds of I2C data streams are required for real-time data acquisition, reporting, and control. The previous single-channel or multi-channel I2C data acquisition technology cannot meet the demand for acquisition volume. Secondly, in complex circuit systems, data of various different rates are often transmitted simultaneously, with many internal transmission lines. These lines are often densely packed and arranged in a non-parallel structure, which easily leads to crosstalk between the wires. When the number of low-speed I2C data streams acquired in parallel exceeds three, it can easily cause electromagnetic interference to the adjacent high-speed data transmission, resulting in bit errors and transmission failures in other high-speed data transmissions.
[0008] Complex circuit systems refer to systems containing a wide variety of electrical signals that need to be processed, involving both digital and analog circuits. These include various digital signals at high, medium, and low speeds, ranging from high-speed serial signals at 5Gbps to low-speed data signals at tens of kHz, as well as parallel digital storage signals, high-precision clock signals, and so on. Due to the complexity of the system and the numerous technical specifications that need to be achieved, all of these signals need to be processed and operated simultaneously within the same system, or even on the same circuit board. Summary of the Invention
[0009] The purpose of this invention is to address the shortcomings of existing technologies by providing a device and method capable of acquiring data from hundreds of I2C channels. This device is simple in structure and low in cost. This method is easy to operate, avoids electromagnetic interference from other signals in complex circuit systems caused by multi-channel I2C data acquisition, and improves the efficiency and quantity of data acquisition.
[0010] The technical solution to achieve the objective of this invention is:
[0011] A device capable of acquiring data from hundreds of I2C channels includes a main control board CPU and 24 identical sub-control boards connected to the main control board CPU. The main control board CPU uses a GD32F450 main chip, which is a 32-bit general-purpose microcontroller based on the Arm® Cortex®-M4 processor with a maximum processing frequency of 200MHz. The main control board CPU also includes a crystal oscillator, FLASH chip, SDRAM chip, network interface unit, and remote reporting unit. The main control board CPU connects to both a local and a remote host computer. Each of the 24 identical sub-control boards has a PCA9548A chip, manufactured by NXP Semiconductors, which is an 8-channel I2C bus switch chip with reset. Each chip connects to 5 different I2C data terminals to be acquired. Three groups, A, B, and C, are set up to collect 120 channels of I2C data. Each group collects data from 8 sub-control boards, totaling 40 channels. Group A corresponds to SCL1, SDA1, and GD32F450 pins B6 and B5; Group B corresponds to SCL2, SDA2, and GD32F450 pins J4 and H4; Group C corresponds to SCL3, SDA3, and GD32F450 pins F15 and F14. The 24 sub-control boards are connected to the main control board CPU to the JL24-20ZJW socket using a JL24-20TKH connector. The signal lines on the connector are defined as power, ground, serial data SDA, serial clock SCL, and address codes A0, A1, and A2.
[0012] The main control board CPU is constructed using 10 layers stacked sequentially from top to bottom on the PCB. The I2C signal lines (serial data line SDA and serial clock line SCL) are placed on the 10th layer. The 5Gbps high-speed differential signal lines are placed on the top layer (layer 1). Other signal lines are placed on the middle layers of the PCB (layers 3, 5, 6, and 8). The I2C signal lines on the main control board maintain a distance of at least three times the I2C signal line width from other signal lines. The main board's stack-up impedance design is as follows: Layer 1 (top layer), with layer 2 as the reference plane, prioritizes high-speed differential signal traces on the top layer, maintaining a differential impedance of 100 ohms, a line width of 4.5 mil, a spacing of 5.5 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7.5 mil. Layer 3 (reference plane) comprises layers 2 and 4, maintaining a differential impedance of 100 ohms and a line width of 5.1 mil for differential signals. The first layer has a 6.0 mil spacing, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.3 mil. Layers 5 and 6, with reference planes on layers 4 and 7, maintain a differential signal impedance of 100 ohms, a line width of 5.2 mil, a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.5 mil. Layer 8, with reference planes on layers 7 and 9, maintains a differential signal impedance of 100 ohms, a line width of 5.1 mil, a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.3 mil. Layer 10, with reference planes on layer 9, maintains a differential signal impedance of 100 ohms, a line width of 4.5 mil, a spacing of 5.5 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7.5 mil. Layers 1, 3, 5, 6, 8, and 10 are signal routing layers, while layers 2, 4, 7, and 9 are designed as ground and power layers.
[0013] The control board is divided into 4 layers during PCB fabrication. High-speed signal lines are placed on the first layer, which is the top layer. The top layer is the reference surface of the second layer. The high-speed differential electrical signal lines have a differential impedance of 100 ohms, a line width of 7 mil, a spacing of 8 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7 mil. The second layer is the ground layer. The third layer is the power layer. The fourth layer is the bottom layer, where I2C signal lines are placed. The single-ended electrical signal lines have an impedance of 50 ohms and a line width of 7 mil.
[0014] The SDRAM chip is an SM48LC16M16M chip, which is a 256Mb SDRAM synchronous dynamic random access memory with 4 banks, each bank being 4Mbit*16. All control signals, address signals, and data signals of the circuit are synchronized with the external clock CLK.
[0015] The FLASH chip is GD25Q127C, which is an 8Mbit serial flash memory chip that can be read and written at least 100,000 times, powered by 3.3V, and can store data for 20 years. It supports SPI interface, hardware and software write protection, and has low power consumption.
[0016] The crystal oscillator is a high-precision active crystal oscillator with a working voltage of 3.3V, a frequency of 25MHz, and an accuracy of ±50ppm.
[0017] The remote reporting unit is equipped with level conversion and E / O and O / E circuit modules.
[0018] A method for collecting data from 100 I2C channels, comprising the aforementioned apparatus, the method comprising the following steps:
[0019] 1) The main control board completes the sub-control board address encoding: After the system is powered on, the crystal oscillator of the main control board starts to work. The third pin of the crystal oscillator outputs an 11.0592MHz square wave system clock. The main control board CPU first calls the pre-stored software from the FLASH chip GD25Q127C. Initially, it performs a frequency division operation of 96 times on the input 11.0592MHz clock to obtain a 115.2kHz square wave as the serial clock line SCL of the I2C bus. According to the previous grouping design, the address of the sub-control board is 7 bits. The first 4 bits are fixed to the default address 1110 of the chip PCA9548A. The last 3 bits A0A1A2 are encoded by the main control board as 000~111, i.e., 8 binary addresses, according to the different sub-control board sequences. The main control board pulls the A0A1A2 bits of different sub-control boards up to the power supply and represents them with 1, or pulls them down to ground and represents them with 0.
[0020] 2) Main control board detects host computer commands: The main control board CPU chip receives Ethernet commands from the host computer and detects the commands sent by the host computer. When it receives the command "Detect the power of the Y-channel I2C data of the X-th sub-control board", it calculates the corresponding address as 1110XXX and prepares to read the power of the Y-channel I2C data of the X-th sub-control board. Otherwise, if there is no command from the host computer, the CPU's A group reads the power of the I2C data of channels 1 to 40 in a fixed order according to the default order of channels 1 to 5 of the 1st sub-control board; channels 2 to 8, completing the polling acquisition of group A. The same applies to groups B and C.
[0021] 3) The main control board reads the power information of the Y-channel I2C data to be collected from the X-th sub-control board: The main control board generates a start bit S, pulling the serial clock line SCL high and the serial data line SDA low. After the sub-control board detects the start bit of the main control board, it starts receiving addresses from the main control board. Then it compares the address received from the main control board with its own encoded address. Once the two addresses are the same, the sub-control board will send an acknowledgment ACK. The main control board issues the first instruction to open the X-th sub-control board, the second instruction to open the Y-channel I2C data of the X-th sub-control board, and the third instruction to read... The power data of the Y-channel I2C data on the X-th sub-control board is retrieved. After receiving the power data sent by the sub-control board, the main control board must also reply with an acknowledgment signal. The fourth instruction shuts down the second channel I2C data on the X-th sub-control board. The main control board issues a shut-down instruction, and after the sub-control board generates an acknowledgment bit, the main control board generates a stop bit P, which pulls the serial clock SCL high and the serial data SDA high, completing the third step. The fourth instruction in this step must be executed; otherwise, multiple I2C data channels on the bus will respond simultaneously, leading to subsequent data read / write failures. The execution process is shown in the table below:
[0022] ;
[0023] 4) Main control board information reporting: The control host encodes the Y-channel I2C data power data collected from the X-th sub-control board into Ethernet data format and reports it to the host computer, thereby completing one I2C data acquisition at a specified address.
[0024] After power-on, the CPU processing chip on the main control board first calls the corresponding program from the FLASH chip GD25Q127C. Simultaneously, the operating system requires the support of the SDRAM chip SM48LC16M16M and a high-precision crystal oscillator. Then, the GD32F450 decodes the Ethernet acquisition instructions from the host computer and accesses the I2C switch chip of a specific channel on the sub-control board through a simulated I2C interface to acquire data from specific objects, completing a total of 120 channels of I2C data acquisition. The CPU then reports the acquired data to the host computer via Ethernet.
[0025] The system needs to collect a large amount of I2C data simultaneously, and the amount of information is large. In order to ensure that there are no errors during the data acquisition process and that the acquisition work does not cause electromagnetic interference to other high-speed data transmissions in the system, each PCA9548A chip is responsible for completing 5 different I2C data accesses. The CPU processor is responsible for address encoding and resetting of 24 PCA9548A chips, and at the same time analyzing the I2C acquisition requirements received from the host computer. According to the requirements, the system performs data acquisition of 120 I2C data channels at specified addresses, or the system defaults to grouped and time-division polling acquisition of data. While completing the access and reporting functions of voltage, temperature, power and other information of 120 I2C data acquisition objects, it does not affect the transmission of other high-speed signals on the control board.
[0026] After 120 channels of I2C data acquisition are completed, the CPU processor encodes the acquired data, adds CRC checksums, converts it into network data, and uploads it to the local host computer via the local network port. At the same time, the acquired data can also be processed by level change, converted into optical signals by E / O and O / E light intensity modulation, and transmitted to a remote host computer hundreds of kilometers away. After receiving the network data, the host computer performs CRC checksums on the data, and displays the acquired information after confirming that the received data is correct.
[0027] The CPU central processing unit chip mentioned above uses GD32F450I, which is a 32-bit general-purpose microcontroller based on Arm® Cortex®-M4 processor with a maximum processing frequency of 200MHz. The Cortex®-M4 processor is a 32-bit processor with floating-point operation capabilities, low interrupt latency, and low-cost debugging features.
[0028] The switch chip PCA9548A, manufactured by NXP Semiconductors, is an 8-channel I2C bus switch chip with reset. It is a bidirectional octal switch chip that can be controlled via I2C bus, and the SDL / SDA port can support eight SDLx / SDAx channels.
[0029] This technical solution performs real-time data acquisition from 120 I2C channels on the bus. It can acquire I2C data from specified addresses or perform polling data acquisition. By acquiring I2C data from hundreds of channels, useful data such as voltage, temperature, and power of the target object can be obtained. Without affecting the normal transmission of other signals on the board, such as high-speed 5Gbps signals, 10MHz analog clock signals, and 2Mbps RS422 data, the data acquired from the 120 I2C channels can be reported to the local computer terminal for display via the network port.
[0030] If the collected I2C data needs to be transmitted to a distant computer terminal, the collected data can be processed by level shifting, and then converted into an optical signal through E / O and O / E optical intensity modulation before being transmitted to a remote host computer hundreds of kilometers away. After receiving the network data, the host computer performs a CRC check on the data, and displays the collected information after confirming that the received data is correct. Issuing the collection command is the reverse process.
[0031] This device has a simple structure and low cost. This method is easy to operate, avoids electromagnetic interference to other signals in complex circuit systems caused by simultaneous acquisition of multiple I2C data streams, and improves the efficiency and quantity of data acquisition. Attached Figure Description
[0032] Figure 1 This is a timing diagram of the transmission process of single-channel I2C data between the master and slave devices in the existing technology.
[0033] Figure 2 This is a schematic diagram of the device in the embodiment;
[0034] Figure 3 This is a flowchart illustrating the method in the embodiment. Detailed Implementation
[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments, but this is not intended to limit the scope of the invention.
[0036] Example:
[0037] Reference Figure 2A device capable of acquiring data from hundreds of I2C channels includes a main control board CPU and 24 identical sub-control boards connected to the main control board CPU. The main control board CPU uses a GD32F450 chip, a 32-bit general-purpose microcontroller based on the Arm® Cortex®-M4 processor with a maximum processing frequency of 200MHz. The main control board CPU also includes a crystal oscillator, FLASH chip, SDRAM chip, network interface unit, and remote reporting unit. The main control board CPU connects to both a local and a remote host computer. Each of the 24 identical sub-control boards has one PCA9548A chip, manufactured by NXP Semiconductors, an 8-channel I2C bus switch chip with reset. Each chip connects to 5 different I2C data terminals to be acquired. Three groups, A, B, and C, are set up to collect 120 channels of I2C data. Each group collects data from 8 sub-control boards, totaling 40 channels. Group A corresponds to SCL1, SDA1, and GD32F450 pins B6 and B5; Group B corresponds to SCL2, SDA2, and GD32F450 pins J4 and H4; Group C corresponds to SCL3, SDA3, and GD32F450 pins F15 and F14. The 24 sub-control boards are connected to the main control board CPU to the JL24-20ZJW socket using a JL24-20TKH connector. The signal lines on the connector are power, ground, serial data SDA, serial clock SCL, and address codes A0, A1, and A2.
[0038] In this example, the CPU main control board is designed with 10 layers stacked sequentially from top to bottom. The I2C signal lines (serial data line SDA and serial clock line SCL) are placed on the 10th layer. The 5Gbps high-speed differential signal lines are placed on the top layer (layer 1). Other signal lines are placed on the middle layers of the PCB (layers 3, 5, 6, and 8). The I2C signal lines on the main control board maintain a distance of at least three times the I2C signal line width from other signal lines. The main control board's stack-up impedance design is as follows: Layer 1 (top layer), with layer 2 as the reference plane, prioritizes high-speed differential signal traces on the top layer, maintaining a differential impedance of 100 ohms, a line width of 4.5 mil, a spacing of 5.5 mil, and a single-ended electrical signal impedance of 50 ohms with a line width of 7.5 mil. Layer 3 (reference plane) comprises layers 2 and 4, maintaining a differential impedance of 100 ohms and a line width of 5.1 mil for differential signals. The first layer has a 6.0 mil spacing, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.3 mil. Layers 5 and 6, with reference planes on layers 4 and 7, maintain a differential signal impedance of 100 ohms, a line width of 5.2 mil, a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.5 mil. Layer 8, with reference planes on layers 7 and 9, maintains a differential signal impedance of 100 ohms, a line width of 5.1 mil, a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.3 mil. Layer 10, with reference planes on layer 9, maintains a differential signal impedance of 100 ohms, a line width of 4.5 mil, a spacing of 5.5 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7.5 mil. Layers 1, 3, 5, 6, 8, and 10 are signal routing layers, while layers 2, 4, 7, and 9 are designed as ground and power layers.
[0039] In this example, the control board is divided into 4 layers during PCB fabrication. The high-speed differential signal lines are placed on the first layer, which is the top layer. The reference plane of the top layer is the second layer. The differential impedance of the high-speed differential signal lines is 100 ohms, the line width is 7mil, the spacing is 8mil, the single-ended electrical signal impedance is 50 ohms, and the line width is 7mil. The second layer is the ground layer. The third layer is the power layer. The fourth layer is the bottom layer, where the I2C signal lines are placed. The single-ended electrical signal lines have an impedance of 50 ohms and a line width of 7mil.
[0040] In this example, the SDRAM chip is the SM48LC16M16M chip, which is a 256Mb SDRAM synchronous dynamic random access memory.
[0041] In this example, the FLASH chip is GD25Q127C. GD25Q127C is an 8Mbit serial flash memory chip that can be read and written at least 100,000 times and is powered by 3.3V.
[0042] The crystal oscillator is a high-precision active crystal oscillator with a working voltage of 3.3V, a frequency of 25MHz, and an accuracy of ±50ppm.
[0043] In this example, the remote reporting unit includes a level conversion chip, an electro-optical conversion (E / O) unit, and an opto-electrical conversion (O / E) unit.
[0044] like Figure 3 As shown, a method for collecting data from 100 I2C channels includes the aforementioned device, and the method includes the following steps:
[0045] 1) The main control board completes the sub-control board address encoding: After the system is powered on, the crystal oscillator of the main control board starts to work. The third pin of the crystal oscillator outputs an 11.0592MHz square wave system clock. The main control board CPU first calls the pre-stored software from the FLASH chip GD25Q127C. Initially, it performs a frequency division operation of 96 times on the input 11.0592MHz clock to obtain a 115.2kHz square wave as the serial clock line SCL of the I2C bus. According to the previous grouping design, the address of the sub-control board is 7 bits. The first 4 bits are fixed to the default address 1110 of the chip PCA9548A. The last 3 bits A0A1A2 are encoded by the main control board as 000~111, i.e., 8 binary addresses, according to the different sub-control board sequences. The main control board pulls the A0A1A2 bits of different sub-control boards up to the power supply and represents them with 1, or pulls them down to ground and represents them with 0.
[0046] 2) Main control board detects host computer commands: The main control board CPU chip receives Ethernet commands from the host computer and detects the command sent by the host computer, such as "detect the power of the second channel I2C data of sub-control board 8". Then it calculates the corresponding address (1110111) and prepares to read the power of the second channel I2C data of sub-control board 8. Otherwise, if there are no commands from the host computer, the CPU's A group reads the power of the I2C data of the first to the 40th channel in the fixed order of sub-control board 1 (channel 1 to channel 5); sub-control board 2... sub-control board 8, completing the polling acquisition of group A. The same applies to groups B and C.
[0047] 3) The main control board reads the power information of the second channel of I2C data to be collected from the sub-control board 8: The main control board generates a start bit (S), that is, pulls the serial clock line SCL high and the serial data line SDA low. After the sub-control board detects the start bit of the main control board, it starts to receive the address from the main control board. Then it compares the address received from the main control board with its own address (encoded address). Once the two addresses are the same, the sub-control board will send an acknowledgment (ACK). The main control board issues the first instruction to open the sub-control board. 8. The second instruction opens the second I2C data channel of the sub-control board 8. The third instruction reads the power data (-5dBm) of the second I2C data channel on the sub-control board 8. After receiving the power data sent by the sub-control board, the main control board must also reply with an acknowledgment signal. The fourth instruction closes the second I2C data channel of the sub-control board 8. The main control board issues a close instruction, and after the sub-control board generates an acknowledgment bit, the main control board generates a stop bit (P), that is, it pulls the serial clock SCL high and the serial data SDA high, completing the third step. The fourth instruction in this step must be executed; otherwise, multiple I2C data channels on the bus will respond simultaneously, resulting in data read / write failure. The execution process is shown in the table below:
[0048] ;
[0049] 4) Main control board information reporting: The control host encodes the power data of the second channel I2C data of the sub-control board 8 into Ethernet data format and reports it to the host computer, thereby completing the I2C data acquisition of the specified address.
[0050] If polling is used for data collection, all 120 I2C data channels will be collected in the default order of group A, group B, and group C.
Claims
1. A device capable of collecting data from hundreds of I2C channels, characterized in that, The system includes a main control board and 24 identical sub-control boards connected to the main control board's CPU. The main control board's main chip is a GD32F450 CPU chip. The main control board's CPU chip is physically connected to a crystal oscillator, FLASH chip, SDRAM chip, network interface circuit unit, and remote reporting circuit unit. The main control board's CPU is connected to both a local and a remote host computer. Each of the 24 identical sub-control boards has one PCA9548A chip, and each chip connects to five different I2C data acquisition terminals. Three groups, A, B, and C, are set up to collect a total of 120 channels of I2C data. Each group has 8 sub-control boards, totaling 40 channels. Group A (sub-control boards 1-8) corresponds to SCL1, SDA1, and GD32F450 pins B6 and B5; Group B (sub-control boards 9-16) corresponds to SCL2, SDA2, and GD32F450 pins J4 and H4; Group C (sub-control boards 17-24) corresponds to SCL3, SDA3, and GD32F450 pins F15 and F14. The 24 sub-control boards are connected to the main control board CPU to the main control board CPU using a JL24-20TKH connector. The signal lines on the connector are defined as power, ground, serial data SDA, serial clock SCL, and address codes A0, A1, and A2. The main control board CPU is constructed using 10 layers stacked sequentially from top to bottom on the PCB. The I2C signal lines (serial data line SDA and serial clock line SCL) are placed on the 10th layer. The 5Gbps high-speed differential signal lines are placed on the top layer (layer 1). Other signal lines are placed on the middle layers of the PCB (layers 3, 5, 6, and 8). The I2C signal lines on the main control board maintain a distance of at least three times the I2C signal line width from other signal lines. The CPU stack-up impedance design is as follows: Layer 1 (top layer), with layer 2 as the reference plane, prioritizes high-speed differential signal traces on the top layer, maintaining a differential impedance of 100 ohms, a line width of 4.5 mil, a spacing of 5.5 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7.5 mil. Layer 3 (reference plane) comprises layers 2 and 4, maintaining a differential impedance of 100 ohms and a line width of 5.1 mil for differential signals. Layer 1 has a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.3 mil; Layers 5 and 6, with reference planes at layers 4 and 7, have differential signal holding differential impedance of 100 ohms, a line width of 5.2 mil, a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.5 mil; Layer 8, with reference planes at layers 7 and 9, has differential signal holding differential impedance of 100 ohms, a line width of 5.1 mil, a spacing of 6.0 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 6.3 mil; Layer 10, with reference planes at layer 9, has differential signal holding differential impedance of 100 ohms, a line width of 4.5 mil, a spacing of 5.5 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7.5 mil; Layers 1, 3, 5, 6, 8, and 10 are signal routing layers, while layers 2, 4, 7, and 9 are designed as ground and power layers; The control board is divided into 4 layers during PCB fabrication. The high-speed differential signal lines are placed on the first layer, which is the top layer. The reference plane of the top layer is the second layer. The high-speed differential signal lines have a differential impedance of 100 ohms, a line width of 7 mil, a spacing of 8 mil, a single-ended electrical signal impedance of 50 ohms, and a line width of 7 mil. The second layer is the ground layer. The third layer is the power layer. The fourth layer is the bottom layer, where the I2C signal lines are placed. The single-ended electrical signal lines have an impedance of 50 ohms and a line width of 7 mil.
2. The device capable of collecting 100 I2C data streams according to claim 1, characterized in that, The SDRAM chip is an SM48LC16M16M chip, which is a 256Mb SDRAM synchronous dynamic random access memory.
3. The device capable of collecting data from hundreds of I2C channels according to claim 1, characterized in that, The FLASH chip is GD25Q127C.
4. The device capable of collecting data from hundreds of I2C channels according to claim 1, characterized in that, The crystal oscillator is a high-precision active crystal oscillator with a working voltage of 3.3V, a frequency of 25MHz, and an accuracy of ±50ppm.
5. The device capable of collecting data from hundreds of I2C channels according to claim 1, characterized in that, The main control board CPU is equipped with a remote reporting unit, which includes level conversion and E / O and O / E circuit modules.
6. A method for collecting data from 100 I2C channels, comprising the apparatus according to any one of claims 1-5, the method comprising the following steps: 1) The main control board completes the sub-control board address encoding: After the system is powered on, the crystal oscillator of the main control board starts to work. The third pin of the crystal oscillator outputs an 11.0592MHz square wave system clock. The main control board CPU first calls the pre-stored software from the FLASH chip GD25Q127C. Initially, it performs a frequency division operation of 96 times on the input 11.0592MHz clock to obtain a 115.2kHz square wave as the serial clock line SCL of the I2C bus. According to the previous grouping design, the address of the sub-control board is 7 bits. The first 4 bits are fixed to the default address 1110 of the chip PCA9548A. The last 3 bits A0A1A2 are encoded by the main control board as 000~111, i.e., 8 binary addresses, according to the different sub-control board sequences. The main control board pulls the A0A1A2 bits of different sub-control boards up to the power supply and represents them with 1, or pulls them down to ground and represents them with 0. 2) Main control board detects host computer commands: The main control board CPU chip receives Ethernet commands from the host computer and detects the commands sent by the host computer. When it receives the command "Detect the power of the Y-channel I2C data of the X-th sub-control board", it calculates the corresponding address as 1110XXX and prepares to read the power of the Y-channel I2C data of the X-th sub-control board. Otherwise, if there is no command from the host computer, the CPU's A group reads the power of the I2C data of channels 1 to 40 in a fixed order according to the default order of channels 1 to 5 of the 1st sub-control board; channels 2 to 8, completing the polling acquisition of group A. The same applies to groups B and C. 3) The main control board reads the power information of the Y-channel I2C data to be collected from the X-th sub-control board: The main control board generates a start bit S, pulling the serial clock line SCL high and the serial data line SDA low. After the sub-control board detects the start bit of the main control board, it starts receiving addresses from the main control board. Then, it compares the address received from the main control board with its own encoded address. If the two addresses are the same, the sub-control board will send an acknowledgment ACK. The main control board issues the first instruction to open the X-th sub-control board, and the second instruction to open the Y-channel I2C data of the X-th sub-control board. The third instruction reads the power data of the Y-channel I2C data on the X-th sub-control board. After receiving the power data sent by the sub-control board, the main control board must also reply with an acknowledgment signal. The fourth instruction shuts down the second channel I2C data on the X-th sub-control board. The main control board issues a shut-down instruction. After the sub-control board generates an acknowledgment bit, the main control board generates a stop bit P, which pulls the serial clock SCL high and the serial data SDA high, completing the third step. The fourth instruction in this step must be executed; otherwise, multiple I2C data channels on the bus will respond simultaneously, resulting in subsequent data read / write failures. 4) Main control board information reporting: The control host encodes the Y-channel I2C data power data collected from the X-th sub-control board into Ethernet data format and reports it to the host computer, thereby completing one I2C data acquisition at a specified address.