A chip package structure

Abstract

The utility model discloses a chip packaging structure, including the carrier, the upper fixed mounting of carrier is provided with the cover, the inside of cover is provided with the chip, the inside of cover is provided with the encapsulation glue along the outside of chip, the inside of encapsulation glue is provided with the fin along the both sides of chip top, every side the fin is provided with a plurality, and every side fin vertical interval arrangement, the one end of fin extends to the one side end face of cover, the both sides of encapsulation glue inside top are respectively provided with the heat pipe, and the one end of heat pipe extends to the outside of cover one side. It has realized the natural heat dissipation effect of chip itself, has increased the practicality, thereby solved the heat accumulation in the long time operation process after chip packaging, cannot promptly and effectively radiate, leads to the problem of the chip operating temperature being too high, the performance descending.

Description

Technical Field

[0001] This utility model relates to the field of packaging structure technology, specifically a chip packaging structure. Background Technology

[0002] Chips are indispensable core components in modern electronic devices. By integrating a large number of electronic components such as transistors, resistors, and capacitors onto a tiny piece of semiconductor material (such as silicon), they achieve high integration and miniaturization of circuits. Although chips themselves have powerful functions, bare chips are very fragile and cannot be directly used in actual products. Therefore, chip packaging becomes an important bridge connecting chips with the external environment. Packaging not only provides physical protection for chips, preventing them from being damaged by mechanical damage, chemical corrosion, and electromagnetic interference, but also enables electrical connection with external circuits through pins or solder balls, realizing signal transmission and power supply between chips and external devices.

[0003] For example, the patent with publication number CN222582891U (chip packaging structure) includes a substrate, a chip, a first photocurable layer, and a light-transmitting layer. The chip has a first side and a second side facing each other. The chip is disposed on the substrate with the first side facing it and is electrically coupled to the substrate. The first photocurable layer is disposed on the substrate and covers the outer periphery of the chip and the portion of the second side near the outer periphery of the chip. The light-transmitting layer is disposed on the first photocurable layer and is distributed opposite to the chip. The light-transmitting layer, the first photocurable layer, and the portion of the second side not covered by the first photocurable layer together surround and form a functional space.

[0004] While the aforementioned existing technologies are convenient for ensuring the performance of chip packaging structures, they lack internal heat dissipation structures. Consequently, heat accumulates during long-term operation after chip packaging and cannot be dissipated in a timely and effective manner, leading to excessively high chip operating temperatures and performance degradation. Therefore, the market urgently needs to develop a chip packaging structure to help people solve the existing problems. Utility Model Content

[0005] The purpose of this invention is to provide a chip packaging structure to solve the problem mentioned in the background art where heat accumulates during long-term operation after chip packaging and cannot be dissipated in a timely and effective manner, resulting in excessively high chip operating temperature and performance degradation.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a chip packaging structure, including a carrier wafer, a cover fixedly mounted on the top of the carrier wafer, a chip disposed inside the cover, an encapsulating adhesive disposed inside the cover along the outer side of the chip, and heat sinks disposed inside the encapsulating adhesive along both sides above the chip, with multiple heat sinks disposed on each side and arranged vertically at intervals, one end of each heat sink extending to one end face of the cover.

[0007] Preferably, heat pipes are symmetrically arranged on both sides of the upper part of the encapsulating adhesive, and one end of the heat pipe extends to the outside of one side of the encapsulation cover.

[0008] Preferably, a substrate is bonded and mounted in the middle below the chip, and a temperature-conducting plate is fixedly mounted inside the substrate along the bottom of the substrate, with the temperature-conducting plate in contact with the substrate.

[0009] Preferably, a bottom groove is provided inside the carrier along the lower part of the temperature-conducting plate, and multiple fins are fixedly installed below the temperature-conducting plate, with the fins located inside the bottom groove.

[0010] Preferably, a bottom groove is provided at the bottom inside the substrate, and multiple bottom grooves are provided. A positioning protrusion is provided inside the bottom groove, and the positioning protrusion is fixedly connected to the temperature guiding plate.

[0011] Preferably, electrodes are symmetrically fixedly mounted on both sides below the chip, and conductive bumps are provided below the electrodes, with the conductive bumps being fixedly connected to the carrier.

[0012] Preferably, a plurality of solder balls are fixedly mounted on the underside of the carrier.

[0013] Compared with the prior art, the beneficial effects of this utility model are:

[0014] This invention features multiple vertically spaced heat sinks arranged in the encapsulation adhesive inside the chip's outer side. This allows heat to be quickly transferred to the outside of the encapsulation during prolonged operation after chip packaging, preventing heat accumulation and ensuring timely and effective heat dissipation. This reduces the chip's operating temperature, effectively preventing performance degradation due to overheating, improving chip reliability and lifespan, and providing strong support for stable chip operation.

[0015] This invention, through the installation of heat pipes, can quickly conduct the heat generated by the chip from inside the encapsulation adhesive to the outside of the cover, further enhancing heat dissipation capabilities, ensuring the stability of the chip under long-term high-load operation, and increasing its practicality.

[0016] This utility model forms a bottom heat dissipation structure by setting a bottom plate and a heat-conducting plate, as well as multiple fins below the heat-conducting plate. The heat-conducting plate can conduct the heat generated by the chip to the fins, while the fins increase the heat dissipation area, improve the heat exchange efficiency with the surrounding air, and enhance the heat dissipation capacity of the bottom of the chip. Attached Figure Description

[0017] Figure 1 This is a front view of a chip packaging structure according to the present invention;

[0018] Figure 2 This is a cross-sectional view of a chip packaging structure according to the present invention;

[0019] Figure 3 This is an enlarged schematic diagram of part A of this utility model.

[0020] In the diagram: 1. Carrier; 2. Encapsulation; 3. Solder ball; 4. Chip; 5. Encapsulating adhesive; 6. Heat pipe; 7. Heat sink; 8. Base plate; 801. Bottom groove; 9. Thermal conductive plate; 10. Fin; 11. Electrode; 12. Conductive bump; 13. Positioning bump. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0022] Please see Figure 1-3 The present invention provides an embodiment of a chip packaging structure, including a carrier 1, a cover 2 fixedly mounted on the top of the carrier 1, a chip 4 disposed inside the cover 2, an encapsulating adhesive 5 disposed inside the cover 2 along the outer side of the chip 4, and heat sinks 7 disposed inside the encapsulating adhesive 5 along both sides above the chip 4. Multiple heat sinks 7 are disposed on each side, and the heat sinks 7 on each side are arranged vertically at intervals in a stepped manner. One end of the heat sink 7 extends to one side end face of the cover 2. The heat sink 7 is made of die-cast aluminum alloy.

[0023] By setting multiple heat sinks 7 arranged vertically in a stepped manner in the encapsulation adhesive 5 along the outer side of the chip 4 inside the cover 2, heat can be quickly transferred to the outside of the cover through the heat sinks during long-term operation after chip encapsulation, avoiding heat accumulation, ensuring that the chip can dissipate the generated heat in a timely and effective manner, and improving the reliability and service life of the chip.

[0024] Furthermore, heat pipes 6 are symmetrically arranged on both sides of the upper part of the encapsulating adhesive 5, with one end of the heat pipe 6 extending to the outside of one side of the cover 2.

[0025] The heat pipe 6 further enhances the heat dissipation capacity, enabling the heat generated by the chip to be quickly conducted from inside the encapsulating adhesive 5 to outside the cover 2, achieving rapid heat transfer, improving heat dissipation efficiency, and ensuring the stability of the chip under long-term high-load operation.

[0026] Furthermore, a substrate 8 is bonded and installed in the middle below the chip 4. A temperature-conducting plate 9 is fixedly installed inside the substrate 1 along the bottom of the substrate 8. The temperature-conducting plate 9 is in contact with the substrate 8. A bottom groove is provided inside the substrate 1 along the bottom of the temperature-conducting plate 9. A fin 10 is fixedly installed below the temperature-conducting plate 9, and multiple fins 10 are provided. The fins 10 are located inside the bottom groove. The substrate 8, the temperature-conducting plate 9, and the fins 10 are all made of die-cast aluminum alloy.

[0027] The contact between the substrate 8 and the thermal conductive plate 9, along with the arrangement of multiple fins 10 below the thermal conductive plate 9, together form a bottom heat dissipation structure. The thermal conductive plate 9 can conduct the heat generated by the chip to the fins 10, while the fins 10, by increasing the heat dissipation area, improve the heat exchange efficiency with the surrounding air, enhance the heat dissipation capacity of the bottom of the chip 4, help maintain the overall temperature uniformity of the chip, and improve the reliability and service life of the chip.

[0028] Furthermore, a bottom groove 801 is provided at the bottom inside the substrate 8, and multiple bottom grooves 801 are provided. A positioning protrusion 13 is provided inside the bottom groove 801, and the positioning protrusion 13 is fixedly connected to the temperature guiding plate 9.

[0029] The placement of the bottom groove 801 and the positioning bump 13 not only enhances the connection stability between the bottom plate 8 and the temperature-conducting plate 9, but also ensures the precise alignment between the temperature-conducting plate 9 and the chip 4 through the fixing effect of the positioning bump 13, thereby improving the overall accuracy and reliability of the packaging structure.

[0030] Furthermore, electrodes 11 are symmetrically fixedly installed on both sides below the chip 4, and conductive bumps 12 are provided below the electrodes 11. The conductive bumps 12 are fixedly connected to the carrier 1.

[0031] The electrode 11 and the conductive bump 12 provide a stable electrical connection channel for the chip 4. The fixed connection between the conductive bump 12 and the carrier 1 ensures good electrical contact between the electrode 11 and the carrier 1, reduces contact resistance, and improves signal transmission efficiency.

[0032] Furthermore, solder balls 3 are fixedly installed below the substrate 1, and multiple solder balls 3 are provided.

[0033] The placement of solder ball 3 provides an interface for the chip package structure to connect with external circuits, increasing its practicality.

[0034] Working principle: In use, in the chip 4 packaging structure, chip 4 is placed inside the cover 2 and fixed and protected by the encapsulating adhesive 5. The heat sink 7 can conduct the heat generated by chip 4 during operation to the outside of the cover 2 to avoid heat accumulation. The heat pipe 6, as a high-efficiency heat conduction element, quickly conducts heat from inside the encapsulating adhesive 5 to the outside of the cover 2. Working together with the heat sink 7, the heat dissipation efficiency is improved. At the same time, the bottom heat dissipation structure formed by the bottom plate 8, the temperature conducting plate 9 and the fins 10 is conducive to heat dissipation from the bottom of chip 4, which helps to maintain the overall temperature uniformity of chip 4, thereby improving the reliability and service life of chip 4 and increasing its practicality.

[0035] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A chip packaging structure, comprising a carrier (1), characterized in that: A cover (2) is fixedly installed on the top of the substrate (1). A chip (4) is disposed inside the cover (2). An encapsulating adhesive (5) is disposed inside the cover (2) along the outer side of the chip (4). Heat sinks (7) are disposed inside the encapsulating adhesive (5) along both sides above the chip (4). Multiple heat sinks (7) are disposed on each side, and the heat sinks (7) are arranged vertically at intervals on each side. One end of the heat sink (7) extends to one side end face of the cover (2).

2. The chip packaging structure according to claim 1, characterized in that: Heat pipes (6) are symmetrically arranged on both sides of the upper part of the encapsulating adhesive (5), and one end of the heat pipe (6) extends to the outside of one side of the cover (2).

3. The chip packaging structure according to claim 1, characterized in that: A substrate (8) is bonded and installed in the middle below the chip (4). A temperature-conducting plate (9) is fixedly installed inside the carrier (1) along the bottom of the substrate (8). The temperature-conducting plate (9) is in contact with the substrate (8).

4. The chip packaging structure according to claim 3, characterized in that: The inner side of the carrier plate (1) is provided with a bottom groove below the temperature-conducting plate (9). A fin (10) is fixedly installed below the temperature-conducting plate (9), and multiple fins (10) are provided. The fins (10) are located inside the bottom groove.

5. A chip packaging structure according to claim 4, characterized in that: The bottom of the substrate (8) is provided with a bottom groove (801) and there are multiple bottom grooves (801). The bottom groove (801) is provided with a positioning protrusion (13) inside, and the positioning protrusion (13) is fixedly connected to the temperature guiding plate (9).

6. A chip packaging structure according to claim 1, characterized in that: Electrodes (11) are symmetrically fixedly installed on both sides below the chip (4). Conductive bumps (12) are provided below the electrodes (11), and the conductive bumps (12) are fixedly connected to the substrate (1).

7. A chip packaging structure according to claim 1, characterized in that: Solder balls (3) are fixedly installed below the substrate (1), and multiple solder balls (3) are provided.

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