A new MEMS and MCU combined encapsulation structure
By using a MEMS and MCU co-package structure and connecting them with gold wires and RDL lines, the problems of low integration, poor signal integrity, and poor heat dissipation of MEMS and MCU chips are solved, achieving high integration, low power consumption, and high signal stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- 广西华芯振邦半导体有限公司
- Filing Date
- 2025-05-09
- Publication Date
- 2026-06-02
AI Technical Summary
The separate packaging of MEMS chips and MCU chips in the existing technology and their connection through PCB lead to problems such as low integration, poor signal integrity, high power consumption and poor heat dissipation.
It adopts a MEMS and MCU co-package structure, connects the MEMS chip and the substrate through gold wires, and uses RDL lines to interconnect with the substrate. It combines wafer-level circuit rewiring and long bump technology to reduce the number of pins, shorten the signal path, and increase the metal contact area to improve heat dissipation efficiency.
It improves chip integration, reduces power consumption, enhances the stability and integrity of signal transmission, improves heat dissipation performance, and reduces the impact of thermal expansion coefficient mismatch on system reliability.
Smart Images
Figure CN224313240U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field, specifically a novel MEMS and MCU co-package structure. Background Technology
[0002] MEMS chips are used for the detection and conversion of physical quantities, and their stability and reliability depend on a good packaging structure environment. MCU chips are used for data processing and control logic, and they draw a large current during operation, requiring a good heat dissipation packaging structure to achieve stable logic calculations. Currently, the common structure of MEMS chips on the market is a single-chip die bond, followed by a metal shield packaging, with circuit connections to the independently packaged MCU chip via a PCB board. This method of separate packaging and PCB connection has problems such as low integration density, impact on signal integrity, high power consumption, and poor heat dissipation.
[0003] Currently, the common MEMS chip structure on the market is a single-chip die bond followed by metal shielding, with circuit connections to independently packaged MCU chips via a PCB board. However, this method of separate packaging and PCB connection usually has certain drawbacks, such as: low integration density (because each chip requires an independent package structure and additional wiring space on the PCB board, occupying more space); impact on signal integrity (the longer signal path through the PCB connection easily introduces parasitic capacitance and inductance, leading to signal delay and interference, affecting system performance); high power consumption and poor heat dissipation (the longer signal path and additional packaging may increase power consumption, while the PCB has limited heat dissipation capacity and is more susceptible to the effects of mechanical stress and mismatched coefficients of thermal expansion, thus reducing system reliability). Utility Model Content
[0004] The purpose of this invention is to provide a novel MEMS and MCU co-package structure. In this device, the MEMS chip is fixed to the substrate with die-bonding insulating adhesive, and gold wires are used to connect the MEMS chip and the PAD on the substrate. The MCU's AL-PAD is led out via RDL lines and then connected to the PAD on the substrate via a bump circuit. The signal interconnection between the co-packaged substrate and the MEMS is achieved with shorter circuits, effectively improving the chip integration. The co-packaged structure is less susceptible to interference from external signals, ensuring the integrity of signal transmission. At the same time, the shorter signal path results in lower chip power consumption. The RDL line design effectively ensures the heat dissipation performance of the MCU logic chip, thus solving the problems mentioned in the background technology.
[0005] To achieve the above objectives, this utility model provides the following technical solution:
[0006] A novel MEMS and MCU co-package structure includes, from left to right, a substrate, an MCU chip, an RDL layer, a metal shield, a filler adhesive, an air inlet in the metal shield, an oil-proof film, gold wire, a MEMS chip, die-bonding insulating adhesive, and an air outlet; wherein, the MCU chip is disposed on the substrate, the RDL layer is disposed on the MCU chip, and the metal shield is disposed on the substrate, with the MCU chip and the RDL layer disposed inside the metal shield.
[0007] As a further technical solution of this utility model, the gap between the iron cover and the substrate and the MCU chip is filled with filler glue; the iron cover is provided with an iron cover air inlet, which is connected to the outside.
[0008] As a further technical solution of this utility model, the MEMS chip and the PAD on the substrate are connected by gold wire; the MEMS chip is fixed on the substrate by die-bonding insulating adhesive; the substrate is provided with vent holes, which are through holes on the substrate, and the bottom layer of the substrate is provided with solder resist rings.
[0009] As a further technical solution of this utility model, the RDL layer includes, from bottom to top, a Si substrate, an insulating layer, an Al pad PAD, an electroplated Au layer, a sputtered UBM (TiW) layer, a first PI layer, a second PI layer, an electroplated Cu layer, an electroplated Ni layer, and an electroplated SnAg layer.
[0010] As a further technical solution of this utility model, the Si substrate is the substrate of an MCU chip;
[0011] As a further technical solution of this utility model, an oil-proof film is provided at the top of the air inlet hole on the iron cover.
[0012] As a further technical solution of this utility model, the fabrication of the MCU and MEMS chip co-package structure mainly includes the following steps:
[0013] Wafer preprocessing;
[0014] The incoming wafers are cleaned using a two-fluid process, ensuring that the surfaces of the insulating layer and the aluminum pad conductive layer are clean and free of dust.
[0015] The surface of the insulating layer and the aluminum pad conductive layer is subjected to a high-frequency etching process to remove oxides;
[0016] PI adhesive (polyimide adhesive) is applied to the wafer, and the thickness is made uniform by rotation;
[0017] The PI resin is exposed and developed to form windows of the same size;
[0018] A dense and strongly adherent Au film is formed on the PI and AL pad windows using physical vapor deposition technology, forming a sputtered UBM gold layer.
[0019] The PR adhesive is applied to the wafer, and the thickness is made uniform by rotating it. Then, it is exposed and developed to form the trace opening.
[0020] The gold plating process is carried out using gold plating base solution, additives, etc., to form a gold circuit layer (RDL).
[0021] Use a wet method to soften and detach the photoresist;
[0022] Dry etching utilizes plasma for etching, which is suitable for high-precision and high-selectivity etching. In this case, the Au layer is etched, and the TiW layer is subsequently etched using this method.
[0023] Wafer grinding, wafer dicing:
[0024] After the wafer completes the above RDL-Bump process, the wafer is thinned to 150-300μm by grinding equipment to ensure certain mechanical strength and heat dissipation performance before wafer dicing.
[0025] Substrate-level packaging:
[0026] a. Upon arrival, the substrate needs to be baked with nitrogen to protect the pads and dehumidify. It is recommended to control the temperature at 5-10℃ / min to avoid stress concentration in the substrate due to sudden temperature changes. Special attention should be paid to multilayer boards or composite substrates. The nitrogen purity in the baking chamber should be maintained at ≥99.99%, and the flow rate is usually 5-10L / min. Ensure that the oxygen content in the chamber is <100ppm to avoid oxidation of the pads. After baking, it is recommended to slowly cool to room temperature in a nitrogen atmosphere (such as natural cooling or introducing room temperature nitrogen) to prevent the substrate from absorbing moisture due to temperature difference.
[0027] b. The flip chip machine flips the chip and dips it in flux, aligns the chip bump with the substrate PAD, and then solders the tin-silver layer to the substrate PAD through reflow soldering to form a eutectic layer; the temperature control is usually 240~260℃.
[0028] c. Apply epoxy resin around the soldered MCU chip to fill the bottom through capillary effect.
[0029] Compared with the prior art, the beneficial effects of this utility model are:
[0030] 1. This utility model, through wafer-level circuit rewiring and long bump technology, directly merges PADs with the same functional signals, reduces the number of pins, eliminates the need for separate packaging of MEMS and MCU chips, avoids the occupation of extra wiring space on the PCB board, and solves the problems of large size and low integration caused by "single chip independent packaging + PCB connection" in traditional solutions, making it suitable for high integration products;
[0031] 2. In this invention, the MEMS chip is directly wired to the carrier PAD via gold wire, achieving a short-circuit interconnection with the MCU chip. This replaces the long-distance signal transmission of traditional PCB boards, shortens the signal path, reduces the introduction of parasitic capacitance and inductance, thereby reducing signal delay and interference, and improving the signal transmission stability and performance of the system.
[0032] 3. In this utility model, the MCU chip increases the metal contact area through RDL rewiring technology, forming a more efficient heat dissipation path, accelerating the dissipation of high heat during MCU operation, reducing the problem of increased power consumption caused by poor heat dissipation, and reducing the impact of thermal expansion coefficient mismatch on system reliability. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of the MEMS and MCU chip co-package structure of this utility model.
[0034] Figure 2 This is a schematic diagram of the process flow in this utility model.
[0035] Figure 3 This is a schematic diagram of the MCU wafer RDL-Bump fabrication process in this utility model.
[0036] Figure 4 This is a schematic diagram of the wafer RDL structure in this utility model.
[0037] In the diagram: 1-substrate, 2-MCU chip, 3-RDL layer, 4-iron cover, 5-filler adhesive, 6-air inlet of iron cover, 7-oil-proof film, 8-gold wire, 9-MEMS chip, 10-die bonding insulating adhesive, 11-air outlet, 12-Si substrate, 13-insulating layer, 14-Al pad, 15-electroplated Au layer, 16-sputtered UBM (TiW) layer, 17-first PI layer, 18-second PI layer, 19-electroplated Cu layer, 20-electroplated Ni layer, 21-electroplated SnAg layer. Detailed Implementation
[0038] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0039] Please see Figure 1-4 In this embodiment of the present invention, a novel MEMS and MCU co-package structure includes, from left to right, a substrate 1, an MCU chip 2, an RDL layer 3, an iron cover 4, a filler adhesive 5, an air inlet 6 in the iron cover, an oil-proof film 7, a gold wire 8, a MEMS chip 9, a die-bonding insulating adhesive 10, and an air outlet 11; wherein, the MCU chip 2 is disposed on the substrate 1, the RDL layer 3 is disposed on the MCU chip 2; the iron cover 4 is disposed on the substrate 1, and the MCU chip 2 and the RDL layer 3 are disposed inside the iron cover 4.
[0040] The gap between the iron cover 4, the substrate 1, and the MCU chip 2 is filled with filler glue; the iron cover 4 is provided with an iron cover air inlet 6, which is connected to the outside.
[0041] By adopting the above technical solution, through wafer-level redistribution line (RDL) and long bump technology, PAD pads with the same functional signals are directly merged, reducing the number of pins. There is no need to separately package MEMS and MCU chips, avoiding the occupation of extra wiring space on the PCB board. This solves the problems of large size and low integration caused by the traditional solution of "single chip independent packaging + PCB connection", and is suitable for high integration products.
[0042] In this embodiment, the MEMS chip 9 and the PAD on the substrate 1 are connected by gold wire 8; the MEMS chip 9 is fixed on the substrate 1 by die bonding insulating adhesive 10; the substrate 1 is provided with vent hole 11, which is a through hole on the substrate 1, and the bottom layer of the substrate 1 is provided with solder resist ring.
[0043] In this embodiment, the RDL layer 3 includes, from bottom to top, a Si substrate 12, an insulating layer 13, an Al pad PAD 14, an electroplated Au layer 15, a sputtered UBMTiW layer 16, a first PI layer 17, a second PI layer 18, an electroplated Cu layer 19, an electroplated Ni layer 20, and an electroplated SnAg layer 21.
[0044] By adopting the above technical solution, the MEMS chip is directly wired to the carrier PAD through gold wires, and the short-circuit interconnection with the MCU chip is achieved, which replaces the long-distance signal transmission of the traditional PCB board, shortens the signal path, reduces the introduction of parasitic capacitance and inductance, thereby reducing signal delay and interference, and improving the signal transmission stability and performance of the system.
[0045] Furthermore, the Si substrate 12 is the substrate of the MCU chip 2;
[0046] In this embodiment, an oil-proof film 7 is provided at the top of the air inlet 6 on the iron cover 4.
[0047] By adopting the above technical solution, the MCU chip increases the metal contact area through RDL redistribution technology, forming a more efficient heat dissipation path. This accelerates the dissipation of high heat during MCU operation, reduces the power consumption increase caused by poor heat dissipation, and minimizes the impact of thermal expansion coefficient mismatch on system reliability.
[0048] The working principle of this utility model is as follows: the signal of the MCU chip 2 is directly connected to the PAD of the substrate 1 through the gold wire 8, and then interconnected with the RDL layer 3 of the MCU chip 2 through the internal circuit of the substrate 1, thereby shortening the signal path by more than 90%.
[0049] A multi-layer rewiring network is constructed on the surface of the MCU wafer through a first layer PI17, a second layer PI18, and an electroplated Cu layer 19, etc., to rearrange the PADs of the original chip and merge signals with the same function, thereby reducing the number of pins and optimizing signal routing, and further reducing transmission loss.
[0050] By using the PAD merging technology of RDL layer 3, signals with the same function in MEMS chip 9 and MCU chip 2 are directly merged at the wafer level, avoiding repeated connections of independent wiring in traditional solutions and reducing the risk of signal crosstalk.
[0051] By increasing the metal contact area through electroplating Cu layer 19, Ni layer 20 and SnAg layer 21, the area of the PAD can be increased by 3-5 times compared with the traditional chip PAD, forming a large-area heat dissipation channel and accelerating the heat conduction from the chip core to the substrate.
[0052] The MCU chip 2 is tightly connected to the substrate 1 via flip-chip bonding. The substrate 1 acts as a heat carrier to transfer heat to the iron cover 4. The iron cover 4 further dissipates heat through contact with air on its surface. At the same time, epoxy resin filler fills the gap between the MCU chip 2 and the substrate 1 to reduce thermal resistance.
[0053] Epoxy resin is applied to the edge of MCU chip 2 to fill the gap between MCU chip 2 and substrate 1 through capillary effect. After curing, it forms a rigid support layer to relieve the stress caused by the difference in thermal expansion coefficient between MCU chip 2 and substrate 1 and prevent the solder joint from cracking.
[0054] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0055] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A novel MEMS and MCU co-package structure, characterized in that: The components include, from left to right, a substrate (1), an MCU chip (2), an RDL layer (3), an iron cover (4), a filler adhesive (5), an air inlet (6) in the iron cover, an oil-proof film (7), a gold wire (8), a MEMS chip (9), a die-bonding insulating adhesive (10), and an air outlet (11); wherein, the MCU chip (2) is disposed on the substrate (1), and the RDL layer (3) is disposed on the MCU chip (2); the iron cover (4) is disposed on the substrate (1), and the MCU chip (2) and the RDL layer (3) are disposed inside the iron cover (4).
2. The novel MEMS and MCU co-package structure according to claim 1, characterized in that: The gap between the iron cover (4) and the substrate (1) and the MCU chip (2) is filled with filler glue; the iron cover (4) is provided with an iron cover air inlet (6), which is connected to the outside.
3. The novel MEMS and MCU co-package structure according to claim 1, characterized in that: The MEMS chip (9) and the PAD on the substrate (1) are connected by gold wire (8); the MEMS chip (9) is fixed on the substrate (1) by die bonding insulating adhesive (10); the substrate (1) is provided with an air vent (11), which is a through hole on the substrate (1), and the bottom layer of the substrate (1) is provided with a solder resist ring.
4. The novel MEMS and MCU co-package structure according to claim 1, characterized in that: The RDL layer (3) includes, from bottom to top, a Si substrate (12), an insulating layer (13), an Al pad PAD (14), an electroplated Au layer (15), a sputtered UBM (TiW) layer (16), a first PI layer (17), a second PI layer (18), an electroplated Cu layer (19), an electroplated Ni layer (20), and an electroplated SnAg layer (21).
5. A novel MEMS and MCU co-package structure according to claim 4, characterized in that: The Si substrate (12) is the substrate of the MCU chip (2).
6. The novel MEMS and MCU co-package structure according to claim 1, characterized in that: An oil-proof film (7) is provided at the top of the air inlet (6) on the iron cover (4).