A chip precision positioning fixture

Abstract

This utility model discloses a chip precision positioning fixture. The chip has a colloid, and the colloid has a lead edge and a non-lead edge. The lead edge has a lead. The fixture includes a main body, which has a positioning groove. A colloid support boss is provided in the positioning groove. The edge of the colloid support boss has ribs that match the lead edge. A lead bearing area is provided on the outer side of the ribs, and the ribs avoid the lead. This utility model avoids the problem of chip jamming when the chip is too small or too large by setting ribs to avoid the lead and positioning the chip by chamfering the lead edge and the non-lead edge. The method is novel and has high positioning accuracy. At the same time, this utility model sets up a clearance area, which makes it easier for operators to pick up and put down the chip.

Description

Technical Field

[0001] This utility model belongs to the field of chip positioning technology, and specifically relates to a chip precision positioning fixture. Background Technology

[0002] In automated chip manufacturing, positioning fixtures are typically used for programming and testing. Currently, positioning of chips with leads mainly relies on dual positioning of the leads and the encapsulating material. However, due to large dimensional deviations in chip leads and burrs on the edges of the encapsulating material, traditional fixtures require amplifying the tolerances of the positioning edges. This amplification has the following drawbacks: when the chip leads are small or have few burrs, the chip may shift within the positioning fixture, affecting positioning accuracy and consequently testing accuracy; when the chip leads are large or have many burrs, jamming may occur, affecting chip quality.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide a chip precision positioning fixture, thereby overcoming the defects in the prior art.

[0005] To achieve the above objectives, this utility model provides a chip precision positioning fixture. The chip is provided with a colloid, the colloid has a lead edge and a non-lead edge, the lead edge has a lead, the fixture body is provided with a positioning groove, the positioning groove has a colloid support boss, the edge of the colloid support boss has a rib that matches the lead edge, the outer side of the rib has a lead bearing area, and the rib avoids the lead.

[0006] Furthermore, as a preferred embodiment, the rib is provided with a lead edge chamfer that matches the lead edge.

[0007] Furthermore, as a preferred embodiment, the ribs are provided in two parts, with each rib avoiding the pin and matching the edge of the pin.

[0008] Furthermore, as a preferred embodiment, the inner wall of the positioning groove is provided with a chamfer on the non-pin edge that matches the non-pin edge.

[0009] Furthermore, as a preferred embodiment, the gap between the chamfered edge of the lead and the lead edge of the chip colloid is 0.03-0.05mm.

[0010] Furthermore, as a preferred embodiment, the gap between the non-lead edge chamfer and the non-lead edge of the chip colloid is 0.03-0.05mm.

[0011] Furthermore, as a preferred embodiment, the positioning groove has a structure in which the diameter gradually decreases from top to bottom.

[0012] Furthermore, as a preferred embodiment, avoidance zones are provided at the four corners of the positioning groove.

[0013] Furthermore, preferably, the depth of the positioning groove is greater than the height of the chip.

[0014] Furthermore, preferably, the depth of the area formed by the ribs and supporting bosses is less than the height of the chip.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] This invention avoids the problem of chip jamming when the chip is too small or too large by setting ribs to avoid the pins and using chamfering on the pin edges and non-pin edges to position the chip. The method is novel and has high positioning accuracy.

[0017] This utility model features a clearance zone, making it easier for staff to pick up and put down the chip. Attached Figure Description

[0018] Figure 1 This is a top view of a prior art chip positioning fixture of this utility model;

[0019] Figure 2 The image shows a top view and a cross-sectional view along the CC direction of a prior art chip positioning fixture of this utility model.

[0020] Figure 3 The image shows a top view and a cross-sectional view along the DD direction of a prior art chip positioning fixture of this utility model.

[0021] Figure 4 For the present utility model Figure 2 Enlarged view of point E in the middle;

[0022] Figure 5 For the present utility model Figure 3 Enlarged view of point F in the middle;

[0023] Figure 6 This is a schematic diagram of the structure of a chip precision positioning fixture according to the present invention;

[0024] Figure 7 This is a top view of a chip precision positioning fixture according to the present invention;

[0025] Figure 8 This is a top view and a cross-sectional view along the AA direction of a chip precision positioning fixture according to this utility model.

[0026] Figure 9This is a top view and a cross-sectional view along the BB direction of a chip precision positioning fixture according to this utility model.

[0027] Figure 10 For the present utility model Figure 8 Enlarged view of point G in the middle;

[0028] Figure 11 For the present utility model Figure 9 Enlarged view of point H in the middle;

[0029] Reference numerals: 1-Jig body, 11-Positioning groove, 12-Supporting boss, 13-Positioning area, 14-Rib, 15-Pin bearing area, 16-Pin edge chamfer, 17-Non-Pin edge chamfer, 18-Avoidance area, 2-Chip, 21-Colloid, 22-Pin edge, 23-Non-Pin edge, 24-Pin. Detailed Implementation

[0030] The specific embodiments of this utility model are described in detail below, but it should be understood that the protection scope of this utility model is not limited to the specific embodiments.

[0031] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0032] Existing chip positioning fixtures such as Figures 1-5 As shown, the fixture includes a main body 1, a positioning groove 11 is provided inside the main body 1, a support boss 12 is provided inside the positioning groove 11, and a positioning area 13 is formed on the outer periphery of the support boss 12. The prior art has the following problems: when the chip pin size is too small or there are burrs (… Figure 5 a and Figure 6 When the chip size is small (as shown in b), the chip has a certain displacement within the positioning fixture, affecting the positioning accuracy and thus the testing accuracy. When the chip pin size is too large or there are many burrs, the chip is prone to jamming, which in turn affects the chip quality.

[0033] Example 1:

[0034] like Figures 6-11As shown, in order to overcome the shortcomings of the existing chip positioning fixtures, this embodiment provides a chip precision positioning fixture. The chip 2 is provided with a colloid 21, the colloid 21 is provided with a lead edge 22 and a non-lead edge 23, the lead edge 22 is provided with a lead 24, and the fixture body 1 is provided with a positioning groove 11. The positioning groove 11 is provided with a colloid support boss 12. The edge of the colloid support boss 12 is provided with a rib 14 that matches the lead edge 22. The outer side of the rib 14 is provided with a lead bearing area 15. The rib 14 avoids the lead 24.

[0035] In this embodiment, as a specific solution, the rib 14 is provided with a pin edge chamfer 16 that matches the pin edge 22.

[0036] In this embodiment, as a more specific solution, there are two ribs 14, which respectively avoid the pin 24 and match the pin edge 22.

[0037] In this embodiment, as a specific solution, the inner wall of the positioning groove 11 is provided with a non-pin edge chamfer 17 that matches the non-pin edge 23.

[0038] In this embodiment, as a specific solution, the gap between the lead edge chamfer 16 and the lead edge 22 of the chip colloid is 0.03-0.05mm; this gap can ensure that while facilitating chip placement, it is also positioned to avoid affecting chip detection.

[0039] In this embodiment, as a specific solution, the gap between the non-lead edge chamfer 17 and the non-lead edge 23 of the chip colloid is 0.03-0.05mm; this gap can ensure that while facilitating chip placement, it is also positioned to avoid affecting chip detection.

[0040] In this embodiment, as a specific solution, the positioning groove 11 has a structure in which the diameter gradually decreases from top to bottom; more preferably, the positioning groove 11 has a square truncated pyramid structure, which facilitates the operator to pick up and put down the chip.

[0041] In this embodiment, as a specific solution, a clearance area 18 is also provided at the four corners of the positioning groove 11; the clearance area 18 also makes it easier for operators to pick up and put down the chip.

[0042] In this embodiment, as a specific solution, the depth of the positioning groove 11 is greater than the height of the chip; the depth of the area formed by the rib 14 and the supporting boss 12 is less than the height of the chip.

[0043] This utility model has the following advantages:

[0044] This utility model avoids the pins by setting rib 14, and positions the chip by using pin edge chamfer 16 and non-pin edge chamfer 17. While achieving chip positioning, it can avoid the problem of material jamming when the chip is too small or too large. The method is novel and the positioning accuracy is high.

[0045] 2. This utility model has a clearance zone, which makes it easier for staff to pick up and put down the chip.

[0046] The foregoing description of specific exemplary embodiments of the present invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the present invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the present invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the present invention, as well as various different choices and variations. The scope of the present invention is intended to be defined by the claims and their equivalents.

Claims

1. A chip precision positioning fixture, wherein the chip is provided with a colloid, the colloid having a lead edge and a non-lead edge, the lead edge having leads, characterized in that: The fixture includes a main body, which has a positioning groove. A colloid support boss is provided in the positioning groove. The edge of the colloid support boss is provided with a rib that matches the pin edge. A pin bearing area is provided on the outside of the rib. The rib avoids the pin.

2. The chip precision positioning fixture of claim 1, wherein: The rib has a chamfer on the lead edge that matches the lead edge.

3. The chip precision positioning fixture of claim 2, wherein: The rib has two ribs, which respectively avoid the pin and match the edge of the pin.

4. The chip precision positioning fixture of claim 1, wherein: The inner wall of the positioning groove is provided with a chamfer on the non-pin side that matches the non-pin side.

5. The chip precision positioning fixture of claim 2, wherein: The gap between the chamfered edge of the lead and the lead edge of the chip colloid is 0.03-0.05mm.

6. The chip precise positioning fixture of claim 4, wherein: The gap between the chamfer on the non-lead edge and the non-lead edge of the chip colloid is 0.03-0.05mm.

7. The chip precision positioning fixture of claim 1, wherein: The positioning groove has a diameter that gradually decreases from top to bottom.

8. The chip precision positioning fixture of claim 1, wherein: The positioning groove is also provided with avoidance zones at its four corners.

9. The chip precision positioning fixture of claim 1, wherein: The depth of the positioning groove is greater than the height of the chip.

10. The chip precision positioning fixture of claim 1, wherein: The depth of the area formed by the ribs and supporting bosses is less than the height of the chip.

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