Packaging structure and power module

By setting up an upper and lower bridge region on the substrate in the packaging structure, and using copper bridges and bonding wires to optimize the current flow path, the problems of large device size and severe parasitic inductance in discrete packaging are solved, and the device size is reduced and the heat dissipation capability is improved.

CN224482067UActive Publication Date: 2026-07-10HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD
Filing Date
2025-07-23
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In the existing technology, discretely packaged motor drive inverter devices are large in size and have serious parasitic inductance problems, especially in electric motorcycles and low-speed vehicles. How to reduce the parasitic inductance of the packaged devices and reduce the size of the devices has become an urgent technical problem to be solved.

Method used

The packaging structure employs an upper bridge region and a lower bridge region on the substrate. By considering the positional relationship of the upper bridge chip soldering area, the lower bridge chip soldering area, and the bus negative terminal soldering area, the upper bridge chip and the lower bridge chip can be directly soldered onto the substrate. Combined with the design of copper bridges and bonding wires, the current flow path is optimized to reduce parasitic inductance, and the heat dissipation capacity is improved through the copper bridges.

Benefits of technology

It effectively reduces the size of the packaged device, lowers parasitic inductance and resistance, improves heat dissipation, and enhances the area utilization of the substrate.

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    Figure CN224482067U_ABST
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Abstract

The application provides a packaging structure and a power module, which comprise a substrate, the substrate comprises an upper bridge region and a lower bridge region which are arranged at intervals along a first direction, the upper bridge region comprises upper bridge chip welding areas and upper bridge gate lead-out areas which are arranged at intervals, and the lower bridge region comprises lower bridge chip welding areas, a bus negative terminal welding area, lower bridge gate terminal welding areas and lower bridge source terminal welding areas which are arranged at intervals, the application sets the positional relationship of the upper bridge chip welding areas, the upper bridge gate lead-out areas, the lower bridge chip welding areas, the bus negative terminal welding area, the lower bridge gate terminal welding areas and the lower bridge source terminal welding areas in the substrate, so that the flowing directions of the current of the upper bridge region and the current of the lower bridge region in the packaged device are opposite, the current loop area is small due to the compact arrangement between the chips, the current of the upper bridge region and the current of the lower bridge region are relatively close, and the principle of magnetic field cancellation is used to reduce the parasitic inductance in the current loop.
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