Multi-battery IIC and temperature dual-channel switching acquisition system

Abstract

This utility model discloses a multi-battery IIC and temperature dual-channel switching acquisition system, comprising: a main control module for generating channel control signals and processing acquired data; an IIC module for connecting the IIC interfaces of multiple batteries and reading the IIC information of the batteries; an acquisition module for connecting the NTC temperature sensors of multiple batteries and acquiring temperature signals; a communication module for connecting to a host computer to realize data transmission between the main control module and the host computer; and a control module for receiving the channel control signals from the main control module and outputting selection signals to the IIC module and the acquisition module; wherein: the signal output terminal of the main control module is connected to the input terminal of the control module; the first output terminal of the control module is connected to the channel enable terminal of the IIC module, and the second output terminal is connected to the channel enable terminal of the acquisition module; the data output terminals of the IIC module and the acquisition module are respectively connected to the data input terminal of the main control module; and the communication terminal of the main control module is connected to the communication module.

Description

Technical Field

[0001] This utility model relates to the field of battery testing technology, specifically to a multi-battery IIC and temperature dual-channel intelligent switching acquisition system. Background Technology

[0002] In a battery management system (BMS), communication data (such as I²C information) and temperature data (via NTC sensors) from multiple batteries need to be collected simultaneously. Traditional solutions require a separate I²C acquisition unit and temperature acquisition circuit for each battery, resulting in high hardware costs, complex wiring, and a large system size. Furthermore, multi-channel switching is susceptible to signal interference, affecting data accuracy, and time-sharing operation of the I²C bus and temperature acquisition is difficult, leading to high main control resource consumption and poor scalability. Existing technologies struggle to achieve efficient and low-cost time-sharing switching, acquisition, and synchronous processing of multi-battery data. Utility Model Content

[0003] In view of the technical defects and drawbacks existing in the prior art, this utility model provides a multi-battery IIC and temperature dual-channel switching acquisition system to overcome or at least partially solve the above problems. The specific solution is as follows:

[0004] A multi-battery IIC and temperature dual-channel switching acquisition system includes: a main control module for generating channel control signals and processing acquired data; an IIC module for connecting the IIC interfaces of multiple batteries and reading the IIC information of the batteries; an acquisition module for connecting the NTC temperature sensors of multiple batteries and acquiring temperature signals; a communication module for connecting to a host computer to realize data transmission between the main control module and the host computer; and a control module for receiving the channel control signals from the main control module and outputting selection signals to the IIC module and the acquisition module. Specifically: the signal output terminal of the main control module is connected to the input terminal of the control module; the first output terminal of the control module is connected to the channel enable terminal of the IIC module, and the second output terminal is connected to the channel enable terminal of the acquisition module; the data output terminals of the IIC module and the acquisition module are respectively connected to the data input terminals of the main control module; and the communication terminal of the main control module is connected to the communication module.

[0005] Furthermore, the IIC module includes an IIC expansion chip and multiple IIC isolation circuits:

[0006] The main I²C interface of the IIC expansion chip is connected to the main control module;

[0007] The IIC expansion chip has multiple slave I²C interfaces connected to the I²C bus of multiple batteries through corresponding IIC isolation circuits.

[0008] The second output terminal of the control module is connected to the address configuration terminal of the IIC expansion chip.

[0009] Furthermore, the acquisition module includes a channel switching chip and an acquisition circuit, wherein the multiple analog input terminals of the channel switching chip are respectively connected to the NTC temperature sensors of multiple batteries through the acquisition circuit;

[0010] The output terminal ADC_OUT of the channel switching chip is connected to the ADC interface of the main control module;

[0011] The first output of the control module is connected to the address configuration terminal of the channel switching chip via a channel selection signal.

[0012] Furthermore, each IIC isolation circuit includes a magnetic coupler isolator chip;

[0013] The first side of the magnetic coupling isolator chip includes: a power supply pin for connecting to a corresponding power supply (such as a 3.3V system power supply); and a signal input pin for connecting to the corresponding I²C interface of the IIC expansion chip.

[0014] The second side of the magnetic coupling isolator chip includes: an isolation power supply pin, which is connected to the corresponding isolation power supply (such as ISO_VCC of the isolated DC-DC output); and a signal output pin, which is connected to the I²C bus of the corresponding battery.

[0015] Signals are transmitted between the first and second sides via magnetic coupling, and there is no electrical connection between the power supply pin and the isolation power supply pin.

[0016] Furthermore, each acquisition circuit includes a voltage divider resistor network and a voltage follower:

[0017] The voltage divider resistor network includes a first resistor and a second resistor, wherein: one end of the first resistor is connected to a reference voltage source, one end of the second resistor is grounded, and the common node of the first resistor and the second resistor is connected to a battery NTC temperature sensor; the non-inverting input terminal of the voltage follower is connected to the common node, and the inverting input terminal is shorted to the output terminal; the output terminal of the voltage follower is connected to the corresponding analog input terminal of the channel switching chip.

[0018] Furthermore, the control module includes a latch chip and a driver chip:

[0019] The data input terminal of the latch chip is connected to the GPIO port of the main control module;

[0020] The output of the latch chip is connected to the input of the driver chip;

[0021] The driver chip has: a first set of output terminals, which are connected to the address configuration terminal of the acquisition module via a channel selection signal; and a second set of output terminals, which are connected to the address configuration terminal of the IIC module via an address configuration signal.

[0022] Furthermore, the system also includes a power supply module for supplying power to each module of the system. The power supply module includes a power isolation unit, which includes an isolated DC-DC converter chip and a filter circuit (L1, C1, C2).

[0023] The isolated DC-DC converter chip has: input-side pins VIN and PGND, which are connected to an external power supply; and output-side isolation pins VOUT and SGND, wherein there is no electrical connection between VOUT and SGND to the input side.

[0024] The filtering circuit includes: a π-type filter, consisting of a first capacitor C1, an inductor L1, and a second capacitor C2; the VOUT pin is connected in sequence to the positive terminals of C1, L1, and C2 to form an isolated power supply output terminal ISO_VCC; the SGND pin is connected to the negative terminals of C1 and C2.

[0025] The ISO_VCC output terminal of the isolation power supply supplies power to the isolation power supply pins of the IIC isolation circuit (U2-U9) and the latch chip of the control module, respectively.

[0026] Furthermore, the main control module is equipped with a hardware timer circuit, and the latch chip of the control module has a clock pin, which is connected to the timer output terminal of the main control module;

[0027] When the hardware timer circuit is triggered, the main control module outputs the first group of 3-bit binary encoded signals to the data input terminal of the latch chip through the GPIO port. The signal is converted into a channel selection signal by the driver chip to activate the target battery channel of the acquisition module.

[0028] When the hardware timer circuit is triggered again, the main control module outputs a second set of 3-bit binary encoded signals to the latch chip through the GPIO port. This signal is converted into an address configuration signal by the driver chip to activate the target battery channel of the IIC module.

[0029] The first and second sets of binary encoded signals correspond to the batteries with the same channel address, and the signal switching is triggered by the rising edge of the clock pin of the latch chip.

[0030] This utility model has the following beneficial effects:

[0031] 1. Resource reuse reduces costs: By using the control module to time-division select the channels of the IIC module and the acquisition module, the main control module can be reused to process data, reducing redundant circuits and significantly reducing hardware costs and complexity.

[0032] 2. High accuracy and anti-interference: The IIC module uses a magnetic coupling isolation circuit to eliminate electrical interference between batteries; the acquisition module switches the NTC signal through an analog switch (such as CD4051), and combines it with a voltage follower to ensure the accuracy of temperature acquisition.

[0033] 3. High-efficiency collaborative control: The main controller triggers the latch to output binary code through a timer, and synchronously switches the IIC and temperature channel addresses (such as S0-S2, A0-A2) to ensure that the dual-channel data correspond one-to-one, thereby improving the acquisition efficiency and synchronization.

[0034] 4. Strong scalability: Based on IIC expansion chips (such as TCA9548A), it supports 8-channel battery access, with flexible address configuration, and can easily adapt to more batteries by expanding control signals.

[0035] 5. Simplified communication architecture: The communication module uploads data to the host computer in a unified manner, realizing centralized monitoring and real-time analysis of multi-battery data and improving system reliability. Attached Figure Description

[0036] Figure 1 A schematic diagram of a multi-battery IIC and temperature dual-channel switching acquisition system provided for an embodiment of this utility model;

[0037] Figure 2 A schematic diagram of the structure of an IIC module provided in an embodiment of this utility model;

[0038] Figure 3 A schematic diagram of the structure of a data acquisition module provided in an embodiment of this utility model;

[0039] Figure 4 A schematic diagram of the structure of a magnetic coupling isolator chip provided in an embodiment of this utility model;

[0040] Figure 5 A schematic diagram of the structure of a control module provided in an embodiment of this utility model;

[0041] Figure 6 A schematic diagram of the structure of a power module provided in an embodiment of this utility model;

[0042] Figure 7 A schematic diagram of the dynamic control logic provided in an embodiment of this utility model. Detailed Implementation

[0043] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the present utility model, and not all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0044] To enable those skilled in the art to better understand the technical solutions of this utility model, exemplary embodiments of this utility model are described below with reference to the accompanying drawings, including various details of the embodiments of this utility model to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this utility model. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0045] Where there is no conflict, the various embodiments of this utility model and the features thereof can be combined with each other.

[0046] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Terms such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having the meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0049] See Figure 1 As shown, the multi-battery IIC and temperature dual-channel switching acquisition system provided in this embodiment of the utility model includes:

[0050] The system comprises the following modules: a main control module for generating channel control signals and processing acquired data; an IIC module for connecting multiple batteries via their IIC interfaces and reading battery IIC information; an acquisition module for connecting multiple batteries via NTC temperature sensors and acquiring temperature signals; a communication module for connecting to a host computer and enabling data transmission between the main control module and the host computer; and a control module for receiving channel control signals from the main control module and outputting selection signals to the IIC module and the acquisition module. Specifically: the signal output terminal of the main control module is connected to the input terminal of the control module; the first output terminal of the control module is connected to the channel enable terminal of the IIC module, and the second output terminal is connected to the channel enable terminal of the acquisition module; the data output terminals of the IIC module and the acquisition module are respectively connected to the data input terminal of the main control module; and the communication terminal of the main control module is connected to the communication module.

[0051] Optional:

[0052] The main control module is implemented by a microcontroller unit and includes:

[0053] Hardware timer peripheral TIMx;

[0054] Multiple general purpose input / output ports (GPIO);

[0055] I²C main controller interface;

[0056] Analog-to-digital converter (ADC);

[0057] UART (Uniform Serial Communication Interface)

[0058] In practical implementation, an ARM Cortex-M series microcontroller (such as the STM32F4 series) can be used to implement the main control module, and its hardware resources meet the following requirements:

[0059] TIMx timer: Generates a precise clock signal (connected to the CLK pin of the latch).

[0060] 2. ≥6 GPIO channels:

[0061] Three channels are used for latch data input (D0-D2)

[0062] 3-way backup (e.g., for extended control)

[0063] 3. I²C interface: Supports standard mode (100kbps) to fast mode (400kbps)

[0064] 4.12-bit ADC: Sampling rate ≥ 1Msps (meets NTC dynamic temperature acquisition requirements)

[0065] 5. Dual UART channels:

[0066] UART1 is used for communication with the host computer.

[0067] UART2 backup debugging.

[0068] Compared to existing technologies, this system achieves dual-channel switching functionality for IIC communication and temperature acquisition across multiple batteries. By integrating the main control module, control module, IIC module, and acquisition module, it avoids the complex design required by existing technologies, which necessitates multiple independent acquisition systems (such as separate IIC interfaces and temperature sensor circuits). This simplifies the system architecture, reduces hardware costs, and improves data acquisition efficiency: the main control module uniformly generates channel control signals, enabling rapid switching between channels for different batteries and reducing data acquisition latency. This makes it suitable for scenarios requiring real-time monitoring of multiple batteries, such as battery management systems (BMS).

[0069] See Figure 2 As shown, in some embodiments, the IIC module includes an IIC expansion chip and multiple IIC isolation circuits:

[0070] The main I²C interface (SDA0 / SCL0) of the IIC expansion chip is connected to the main control module;

[0071] The eight slave I²C interfaces (SDA1 / SCL1 - SDA8 / SCL8) of the IIC expansion chip are respectively connected to the I²C bus of the eight batteries through corresponding IIC isolation circuits.

[0072] The second output terminal of the control module is connected to the address configuration terminal (A0-A2) of the IIC expansion chip.

[0073] Among them, the IIC expansion chip is a central expansion device, which can be a TCA9548A chip, and the IIC isolation circuit consists of 8 independent isolation units, corresponding to the number of batteries in a 1:1 ratio.

[0074] Compared to existing technologies, this invention utilizes an IIC expansion chip (such as the TCA9548A) and multiple IIC isolation circuits, significantly expanding the number of IIC interfaces (supporting 8 batteries) without requiring an additional main control chip or complex bus arbitration logic. Existing technologies are often limited by the number of IIC main controllers or use non-isolated interfaces, making them susceptible to interference; while this design achieves electrical isolation through isolation circuits (such as magnetic coupling isolators), protecting the main control module from battery-side faults (such as overvoltage or short circuits), improving system reliability and safety. Simultaneously, the modular design (1:1 battery correspondence) simplifies maintenance and expansion.

[0075] See Figure 3 As shown, in some embodiments, the acquisition module includes a channel switching chip and an acquisition circuit, wherein the eight analog input terminals (CH0-CH7) of the channel switching chip are respectively connected to the NTC temperature sensors of eight batteries through the acquisition circuit;

[0076] The output terminal ADC_OUT of the channel switching chip is connected to the ADC interface of the main control module;

[0077] The first output terminal of the control module is connected to the address configuration terminal of the channel switching chip via channel selection signals (S0-S2).

[0078] The channel switching chip can be a CD4051 chip, using the CD4051's 8-channel analog switch as the switching chip, while the acquisition circuit is a classic design of voltage divider network + operational amplifier.

[0079] Compared to existing technologies, this acquisition module uses a channel switching chip (such as CD4051) and acquisition circuitry to achieve efficient switching between multiple analog signals (temperature signals), avoiding the cost of multiple independent ADCs or complex multiplexers required in existing technologies. The channel switching chip quickly selects NTC temperature sensors from different batteries through digital control. Combined with the standardized design of the acquisition circuitry (such as voltage divider networks and operational amplifiers), it improves the integration and accuracy of temperature acquisition, reduces signal attenuation and noise, and makes the system more compact, suitable for space-constrained embedded applications.

[0080] In some embodiments, each IIC isolation circuit includes a magnetic coupler isolator chip. In this embodiment, there are 8 IIC isolation circuits, namely U2-U9, and corresponding to 8 magnetic coupler chips, namely IC1-IC8.

[0081] The first side of the magnetic coupling isolator chip ICx (x=1~8) includes: power supply pins, which are connected to the corresponding power supply, including VDD1 and GND1; and signal input pins, which are connected to the corresponding slave I²C interface of the IIC expansion chip, including SDA_IN and SCL_IN.

[0082] The second side of the magnetic coupling isolator chip ICx includes: an isolation power supply pin connected to the corresponding isolation power supply, wherein the isolation power supply pin includes VDD2 and GND2; and a signal output pin connected to the I²C bus of the corresponding battery, wherein the signal output pin includes SDA_OUT and SCL_OUT.

[0083] Signals are transmitted between the first and second sides via magnetic coupling, and there is no electrical connection between VDD1 / GND1 and VDD2 / GND2.

[0084] The magnetic coupling isolator chip can be implemented using any of the following methods:

[0085] Analog Devices ADUM1250 (Dual-channel I²C isolator);

[0086] Silicon Labs SI8620 (Dual-channel digital isolator);

[0087] NXP MCU33664 (Automotive-grade magnetic coupler isolator);

[0088] See Figure 4 As shown, it illustrates the connection diagram of the magnetic coupling isolator chip IC1.

[0089] Compared to existing technologies, using magnetically coupled isolator chips (such as IC1-IC8) provides high electrical isolation performance (signal transmission is achieved through magnetic coupling), while existing technologies often use optocouplers or non-isolated interfaces, which suffer from slow speed, easy aging, or noise coupling problems. Magnetic coupling isolation ensures that VDD1 / GND1 and VDD2 / GND2 have no electrical connection, effectively isolating battery-side interference (such as surge or ground noise), improving the stability and data accuracy of IIC signal transmission. At the same time, magnetic coupling has a fast response speed, supports high-speed IIC communication, and improves the overall reliability of the system.

[0090] In some embodiments, each acquisition circuit includes a voltage divider resistor network and a voltage follower:

[0091] The voltage divider resistor network includes a first resistor and a second resistor, wherein: one end of the first resistor is connected to a reference voltage source, one end of the second resistor is grounded, and the common node of the first resistor and the second resistor is connected to a battery NTC temperature sensor; the non-inverting input terminal of the voltage follower is connected to the common node, and the inverting input terminal is shorted to the output terminal; the output terminal of the voltage follower is connected to the corresponding analog input terminal of the channel switching chip.

[0092] The voltage follower can be implemented using a general-purpose operational amplifier (such as LM358, TLV6001, etc.).

[0093] Compared to existing technologies, the advantages of using a voltage divider network and a voltage follower in the acquisition circuit are optimized signal conditioning of the NTC temperature sensor, avoiding the load effect and noise interference when directly reading the sensor signal in existing technologies. The voltage divider network provides a stable reference voltage, and the voltage follower output is shorted to the inverting input buffer signal, ensuring high input impedance and low output impedance, reducing signal distortion. This improves the accuracy and linearity of temperature measurement, especially over a wide temperature range, making the system more robust.

[0094] refer to Figure 5 As shown, in some embodiments, the control module includes a latch chip and a driver chip:

[0095] The data input terminals (D0-D2) of the latch chip are connected to the GPIO port of the main control module;

[0096] The output terminals (Q0-Q2) of the latch chip are connected to the input terminals of the driver chip;

[0097] The driver chip has: a first set of output terminals (OUT1-OUT3) connected to the address configuration terminal of the channel switching chip of the acquisition module through channel selection signals (S0-S2); and a second set of output terminals (OUT4-OUT6) connected to the address configuration terminal of the IIC expansion chip of the IIC module through address configuration signals (A0-A2).

[0098] Compared to existing technologies, the control module uses latch chips and driver chips to reliably latch and drive digital control signals. Existing technologies may rely on software polling or direct GPIO control, which is susceptible to timing jitter. Latch chips (such as the 74HC573 in the 74HC series) ensure the stability of the channel selection signal by hardware latching the signal; driver chips (such as the ULN2003) enhance signal driving capabilities, supporting simultaneous output of channel selection signals (S0-S2) and address configuration signals (A0-A2). This reduces the GPIO burden on the main control module, improves switching speed and synchronization, and reduces software complexity.

[0099] refer to Figure 6 As shown, in some embodiments, the system further includes a power module for supplying power to the various modules of the system; the power module includes a power isolation unit, which includes an isolated DC-DC converter chip and a filter circuit.

[0100] The isolated DC-DC converter chip has: input-side pins (VIN, PGND) connected to an external power supply;

[0101] Output-side isolation pins (VOUT, SGND), where there is no electrical connection between VOUT and SGND to the input side;

[0102] The filtering circuit includes: a π-type filter consisting of a first capacitor C1, an inductor L1, and a second capacitor C2; the VOUT pin is connected in sequence to the positive terminals of C1, L1, and C2 to form an isolated power supply output terminal ISO_VCC; the SGND pin is connected to the negative terminals of C1 and C2.

[0103] The ISO_VCC output terminal of the isolation power supply supplies power to the VDD2 pin of the IIC isolation circuit and the latch chip of the control module, respectively.

[0104] Compared to existing technologies, power modules include isolated DC-DC converter chips and π-type filter circuits to provide isolated power ISO_VCC. Existing technologies often use non-isolated power supplies, which are prone to ground loop noise and interference. This invention's isolated DC-DC converter ensures no electrical connection between the input side (VIN / PGND) and the output side (VOUT / SGND). Combined with π-type filters (C1, L1, C2), it effectively suppresses ripple and EMI noise. This provides clean power to the IIC isolation circuit and control module, improving the system's anti-interference capability, especially in multi-battery environments, extending equipment lifespan.

[0105] refer to Figure 7 As shown, in some embodiments, the main control module is configured with a hardware timer circuit TIMx, and the latch chip U12 of the control module has a clock pin CLK, which is connected to the timer output terminal TIM_Out of the main control module;

[0106] When the hardware timer circuit is triggered, the main control module outputs the first group of 3-bit binary encoded signals to the data input terminals (D0-D2) of the latch chip U12 through the GPIO port. The signals are converted into channel selection signals (S0-S2) by the driver chip (U13) to activate the target battery channel of the acquisition module.

[0107] When the hardware timer circuit is triggered again, the main control module outputs the second set of 3-bit binary encoded signals to the latch chip U12 through the GPIO port. The signal is converted into address configuration signals (A0-A2) by the driver chip to activate the target battery channel of the IIC module.

[0108] The first and second sets of binary encoded signals correspond to the batteries with the same channel address, and the signal switching is triggered by the rising edge of the clock pin CLK of the latch chip U12.

[0109] The hardware timer circuit can be implemented in any of the following ways:

[0110] a) Microcontroller built-in peripherals (such as ARM Cortex-M series TIMx timers)

[0111] b) Discrete timer chips (such as NE555)

[0112] c) Programmable logic devices (such as clock divider modules for CPLDs).

[0113] Compared to existing technologies, this invention uses a hardware timer circuit TIMx to control channel switching and achieve precise timing synchronization. Existing technologies rely on software timing or manual switching, which can easily introduce delays and asynchrony issues. The hardware timer triggers the latch chip U12 via its rising edge, ensuring that the switching of the IIC and temperature channels (the first and second sets of binary signals) is strictly synchronized and corresponds to the same battery address. This avoids phase differences in data acquisition, improves system response speed and data consistency, and is particularly suitable for high-speed, multi-task acquisition scenarios.

[0114] It should be noted that the scheme for which protection is sought in this utility model is related to the selection and connection relationship of various hardware devices. Those skilled in the art, upon learning of the hardware scheme of this application, can obtain the corresponding program without any objection. Therefore, the scheme for which protection is sought in this application does not involve any improvement of the program.

[0115] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A multi-battery IIC and temperature dual-channel switching acquisition system, characterized in that, include: The main control module is used to generate channel control signals and process the acquired data; The IIC module connects to the IIC interfaces of multiple batteries and is used to read the IIC information of the batteries. The system comprises: a data acquisition module, which connects to multiple NTC temperature sensors connected to batteries for acquiring temperature signals; a communication module, which connects to a host computer to enable data transmission between the main control module and the host computer; and a control module, which receives channel control signals from the main control module and outputs selection signals to the IIC module and the data acquisition module. Specifically: the signal output terminal of the main control module is connected to the input terminal of the control module; the first output terminal of the control module is connected to the channel enable terminal of the IIC module, and the second output terminal is connected to the channel enable terminal of the data acquisition module; the data output terminals of the IIC module and the data output terminal of the data acquisition module are respectively connected to the data input terminal of the main control module; and the communication terminal of the main control module is connected to the communication module.

2. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 1, characterized in that, The IIC module includes an IIC expansion chip and multiple IIC isolation circuits: The main I²C interface of the IIC expansion chip is connected to the main control module; The IIC expansion chip has multiple slave I²C interfaces connected to the I²C bus of multiple batteries through corresponding IIC isolation circuits. The second output terminal of the control module is connected to the address configuration terminal of the IIC expansion chip.

3. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 1, characterized in that, The acquisition module includes a channel switching chip and an acquisition circuit. The multiple analog input terminals of the channel switching chip are respectively connected to the NTC temperature sensors of multiple batteries through the acquisition circuit. The output terminal ADC_OUT of the channel switching chip is connected to the ADC interface of the main control module; The first output of the control module is connected to the address configuration terminal of the channel switching chip via a channel selection signal.

4. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 2, characterized in that, Each IIC isolation circuit includes a magnetic coupler isolator chip; The first side of the magnetic coupling isolator chip includes: a power supply pin for connecting to the corresponding power supply; and a signal input pin for connecting to the corresponding I²C interface of the IIC expansion chip. The second side of the magnetic coupling isolator chip includes: an isolation power supply pin, connected to the corresponding isolation power supply; and a signal output pin, connected to the I²C bus of the corresponding battery. Signals are transmitted between the first and second sides via magnetic coupling, and there is no electrical connection between the power supply pin and the isolation power supply pin.

5. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 3, characterized in that, Each acquisition circuit includes a voltage divider resistor network and a voltage follower: The voltage divider resistor network includes a first resistor and a second resistor, wherein: one end of the first resistor is connected to a reference voltage source, one end of the second resistor is grounded, and the common node of the first resistor and the second resistor is connected to a battery NTC temperature sensor; the non-inverting input terminal of the voltage follower is connected to the common node, and the inverting input terminal is shorted to the output terminal; the output terminal of the voltage follower is connected to the corresponding analog input terminal of the channel switching chip.

6. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 4, characterized in that, The control module includes a latch chip and a driver chip: The data input terminal of the latch chip is connected to the GPIO port of the main control module; The output of the latch chip is connected to the input of the driver chip; The driver chip has: a first set of output terminals, which are connected to the address configuration terminal of the acquisition module via a channel selection signal; and a second set of output terminals, which are connected to the address configuration terminal of the IIC module via an address configuration signal.

7. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 6, characterized in that, The system also includes a power module for supplying power to each module of the system; the power module includes a power isolation unit, which includes an isolated DC-DC converter chip and a filter circuit. The isolated DC-DC converter chip has: input-side pins VIN and PGND, which are connected to an external power supply; and output-side isolation pins VOUT and SGND, wherein there is no electrical connection between VOUT and SGND to the input side. The filtering circuit includes: a π-type filter, consisting of a first capacitor C1, an inductor L1, and a second capacitor C2; the VOUT pin is connected in sequence to the positive terminals of C1, L1, and C2 to form an isolated power supply output terminal ISO_VCC; the SGND pin is connected to the negative terminals of C1 and C2. The ISO_VCC output terminal of the isolation power supply supplies power to the isolation power supply pins of the IIC isolation circuit (U2-U9) and the latch chip of the control module, respectively.

8. The multi-battery IIC and temperature dual-channel switching acquisition system according to claim 6, characterized in that, The main control module is equipped with a hardware timer circuit, and the latch chip of the control module has a clock pin, which is connected to the timer output terminal of the main control module. When the hardware timer circuit is triggered, the main control module outputs the first group of 3-bit binary encoded signals to the data input terminal of the latch chip through the GPIO port. The signal is converted into a channel selection signal by the driver chip to activate the target battery channel of the acquisition module. When the hardware timer circuit is triggered again, the main control module outputs a second set of 3-bit binary encoded signals to the latch chip through the GPIO port. This signal is converted into an address configuration signal by the driver chip to activate the target battery channel of the IIC module. The first and second sets of binary encoded signals correspond to the batteries with the same channel address, and the signal switching is triggered by the rising edge of the clock pin of the latch chip.

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