Semiconductor resistor and integrated pHEMT device

Abstract

The utility model discloses a kind of semiconductor resistor and integrated pHEMT device, including from bottom to top sequentially laminated substrate, semiconductor layer and PIN structure, the PIN structure includes sequentially arranged on the N-type semiconductor layer, I-type semiconductor layer and P-type semiconductor layer of the semiconductor layer;The thickness of P-type semiconductor layer is H1, the thickness of I-type semiconductor layer is H2, in the PIN structure, ion implantation high resistance layer formed by injecting insulating ion along to the direction of top to bottom is equipped, the thickness of ion implantation high resistance layer is H, 0 The utility model not only improves the utilization of PIN structure, improves circuit integration efficiency, and makes high resistance value resistance have more flexible adjustment space according to demand.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor resistor and an integrated pHEMT device. Background Technology

[0002] In integrated circuit design, high-resistance resistors and electrostatic discharge (ESD) protection are two key requirements, but their fabrication processes are often separate. High-resistance resistors typically require CAP layer etching or high-resistance metal compound materials to achieve high resistance values ​​within a limited chip area. This resistance value is usually highly dependent on material properties, making flexible adjustment difficult. ESD protection structures (such as diodes) require thicker PIN layers (P-type semiconductor-I-type semiconductor-N-type semiconductor structure) to withstand high-voltage surges and prevent device damage from transient high voltages. With increasingly stringent ESD protection requirements, the thickness of the PIN layer needs to be further increased to ensure sufficient energy discharge capability.

[0003] The actual operating area of ​​ESD protection structures is typically concentrated in localized areas of the device (such as junctions or edges), while the thicker PIN layer is not fully utilized in most areas, leading to a waste of material and process costs. Meanwhile, achieving high-resistance resistors usually requires additional process steps, such as ion implantation and thin-film deposition. If the need for high-resistance resistors could be met using PIN layer structures, ESD robustness could be improved while optimizing the integration efficiency of high-resistance resistors. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a semiconductor resistor that not only improves the utilization rate of the PIN structure and enhances the circuit integration efficiency, but also allows for more flexible adjustment of high-resistance resistors as needed.

[0005] A semiconductor resistor includes a substrate, a semiconductor layer, and a PIN structure stacked sequentially from bottom to top. The PIN structure includes an N-type semiconductor layer, an I-type semiconductor layer, and a P-type semiconductor layer sequentially disposed on the semiconductor layer. The thickness of the P-type semiconductor layer is H1, and the thickness of the I-type semiconductor layer is H2. In the PIN structure, an ion-implanted high-resistivity layer is provided, formed by implanting insulating ions in a top-to-bottom direction. The thickness of the ion-implanted high-resistivity layer is H, where 0 < H < H1 + H2.

[0006] Optional, 100nm≤H1≤500nm, 0<H≤H1.

[0007] Optionally, 100nm≤H1≤500nm, 500nm≤H2≤2000nm, H1<H ​

[0008] Optionally, the insulating ions include Ar. 2+ and He + The amount of insulating ions injected is 2 × 10⁻⁶. 11 ~4×10 12 ion / cm 2 .

[0009] Optionally, the thickness of the N-type semiconductor layer is 100–500 nm, the thickness of the I-type semiconductor layer is 500–2000 nm, and the thickness of the P-type semiconductor layer is 100–500 nm.

[0010] Optionally, the substrate is made of GaAs, and the semiconductor layer includes a GaAs buffer layer, an InGaAs channel layer, an AlGaAs barrier layer, an InGaP barrier layer, and a GaAs capping layer arranged sequentially from bottom to top on one side of the substrate.

[0011] Optionally, it also includes a passivation layer and a resistive connection metal layer, wherein the passivation layer covers the PIN structure and forms an opening on the P-type semiconductor layer, and the resistive connection metal layer is connected to the P-type semiconductor layer through the opening.

[0012] Optionally, the semiconductor layer is made of GaAs, and the p-type semiconductor layer is made of p-type material. + The material of the I-type semiconductor layer is i-GaAs, and the material of the N-type semiconductor layer is n-GaAs. + GaAs; or, the semiconductor layer is made of GaN, and the p-type semiconductor layer is made of p-type material. + GaN, wherein the material of the I-type semiconductor layer is i-GaN, and the material of the N-type semiconductor layer is n-GaN. + GaN.

[0013] Optionally, the thickness H of the ion-implanted high-resistivity layer is 150 nm, or the thickness H of the ion-implanted high-resistivity layer is 1000 nm.

[0014] On the other hand, this utility model also provides an integrated pHEMT device, including a pHEMT device, a PIN antistatic structure, and a semiconductor resistor as described above.

[0015] This invention improves the resistance of the P-type semiconductor layer or the resistance of both the P-type and I-type semiconductor layers by injecting insulating ions into a PIN structure. Depending on the energy and injection concentration, different injection depths and resistance improvement effects can be achieved, and thus the resistance of the PIN structure will also change accordingly. Attached Figure Description

[0016] The specific embodiments of this utility model will now be described in detail with reference to the accompanying drawings. The drawings are only used to illustrate the spatial relationship of the various structural parts and do not represent the actual thickness, dimensions, or relative proportions of the structural parts.

[0017] Figure 1 This is a schematic diagram of the structure of this utility model;

[0018] Figure 2 This is a schematic diagram of the structure of an embodiment of the present utility model;

[0019] Figure 3 This is a schematic diagram of the integrated pHEMT device of this utility model;

[0020] Label Explanation

[0021] Substrate 1 Semiconductor layer 2 Isolation region 21 PIN structure 3 N-type semiconductor layer 31

[0022] 32 Type I semiconductor layer 33 Type P semiconductor layer 34 Ion implanted high resistivity layer

[0023] Passivation layer 41, resistive connection metal layer 42

[0024] pHEMT device 100 PIN anti-static structure 200 semiconductor resistor 300 Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships commonly used when the product is in use, and are merely for ease of description and should not be construed as limiting the present invention. It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. It should also be noted that the division of multiple embodiments in the present invention is merely for the convenience of description and should not constitute a special limitation; features in various embodiments can be combined and mutually referenced without contradiction.

[0026] This utility model discloses a semiconductor resistor, such as Figure 1As shown, this is a preferred embodiment of the present invention, comprising a substrate 1, a semiconductor layer 2, and a PIN structure 3 stacked sequentially from bottom to top. The PIN structure 3 includes an N-type semiconductor layer 31, an I-type semiconductor layer 32, and a P-type semiconductor layer 33 sequentially disposed on the semiconductor layer 2. The thickness of the P-type semiconductor layer 33 is H1, and the thickness of the I-type semiconductor layer 32 is H2. In the PIN structure 3, an ion-implanted high-resistivity layer 34 is formed by implanting insulating ions in a top-to-bottom direction. The thickness of the ion-implanted high-resistivity layer 34 is H, where 0 < H < H1 + H2. That is, the P-type semiconductor layer 33 can be partially implanted, or the P-type semiconductor layer 33 can be completely implanted while the I-type semiconductor layer 32 is partially implanted. The "high resistance" in the ion-implanted high-resistivity layer 34 refers to the fact that the ion-implanted high-resistivity layer 34 has a higher resistance value than the N-type semiconductor layer 31, the I-type semiconductor layer 32, or the P-type semiconductor layer 33.

[0027] Optionally, the amount of insulating ions implanted is 2 × 10⁻⁶. 11 ~4×10 12 ion / cm 2 .

[0028] Optionally, the thickness of the N-type semiconductor layer 31 is 100–500 nm, the thickness of the I-type semiconductor layer 32 is 500–2000 nm, and the thickness of the P-type semiconductor layer 33 is 100–500 nm. In this embodiment, the thickness of the N-type semiconductor layer 31 is 250 nm, the thickness of the I-type semiconductor layer 32 is 1000 nm, and the thickness of the P-type semiconductor layer 33 is 250 nm.

[0029] Optionally, the insulating ions include Ar. 2+ and He + Ar 2+ and He + These are commonly used isolating ions in semiconductor manufacturing. Therefore, there is no need to manufacture additional implantation sources; the energy and implantation density can be adjusted using commonly used ion implantation equipment, without introducing any extra burden to the production line. Of course, other insulating ions can also be used, but these will not be discussed further here.

[0030] Optionally, it also includes a passivation layer 41 and a resistive connection metal layer 42. The passivation layer 41 covers the PIN structure 3 and forms an opening in the PIN structure 3. The resistive connection metal layer 42 is connected to the ion-implanted high-resistivity layer 34 through the opening. The function of the passivation layer 41 is twofold: firstly, it protects the semiconductor material it covers; secondly, it prevents current from flowing to the N-type semiconductor layer 31 and the I-type semiconductor layer 32, thus avoiding the problem of unstable resistance.

[0031] Optionally, in this embodiment, the material of the semiconductor layer 2 is GaAs, and the material of the p-type semiconductor layer 33 is p... + GaAs, the material of the I-type semiconductor layer 32 is i-GaAs, and the material of the N-type semiconductor layer 31 is n-GaAs. + GaAs.

[0032] Of course, the material of semiconductor layer 2 can also be GaN, and the material of the P-type semiconductor layer can be p-type. + GaN, the material of the I-type semiconductor layer is i-GaN, and the material of the N-type semiconductor layer is n-GaN. + GaN.

[0033] Optionally, the substrate 1 is made of one of Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride).

[0034] Optionally, semiconductor layer 2 may include conventional functional layer structures such as buffer layer, nucleation layer, channel layer, isolation layer, and insertion layer, as well as barrier layer formed of AlGaAs material, barrier layer formed of InGaP material, and capping layer, wherein the capping layer includes i-GaAs capping layer and n+GaAs capping layer. (The specific layer structure is not shown in the figure).

[0035] Optionally, 100nm ≤ H1 ≤ 500nm, 0 < H ≤ H1. For example, a resistor can be formed directly using a PIN structure, with a P-type semiconductor layer 33 thickness of 250nm, an I-type semiconductor layer 32 thickness of 1000nm, and an N-type semiconductor layer 31 thickness of 250nm. Without insulating ion implantation, the sheet resistance of the PIN structure is 5Ω / sQ, achieving a forward turn-on voltage of approximately 1V and a reverse breakdown voltage of approximately 40V. When addressing resistor requirements with relatively small resistance values, this invention may only implant ions into the P-type semiconductor layer 33 and then stop implantation, leaving a portion of the P-type semiconductor layer 33 in an unimplanted state. For example... Figure 1 As shown, the depth of insulating ion implantation is 150 nm, that is, the thickness of the ion implanted high-resistivity layer 34 is 150 nm. After implantation, the sheet resistance of the PIN structure is about 50 Ω / SQ, which can be used for resistive device applications.

[0036] Optionally, 100nm ≤ H1 ≤ 500nm, 500nm ≤ H2 ≤ 2000nm, and H1 < H < H1 + H2. For example, a resistor can be formed directly using a PIN structure, with a P-type semiconductor layer 33 thickness of 250nm, an I-type semiconductor layer 32 thickness of 1000nm, and an N-type semiconductor layer 31 thickness of 250nm. Without insulating ion implantation, the sheet resistance of the PIN structure is 5Ω / sQ, achieving a forward turn-on voltage of approximately 1V and a reverse breakdown voltage of approximately 40V. Figure 2As shown, the P-type semiconductor layer 33 is subjected to insulating ion implantation, and a portion of the I-type semiconductor layer 32 is also subjected to insulating ion implantation. The depth of insulating ion implantation is 1000 nm, which means the thickness of the ion implanted high-resistivity layer 34 is 1000 nm. After implantation, the sheet resistance of the PIN structure is approximately 1000 Ω / SQ, which can be used for resistive device applications.

[0037] like Figure 3 As shown, on the other hand, this utility model also provides an integrated pHEMT device, including a pHEMT device 100, a PIN antistatic structure 200, and a semiconductor resistor 300 as described above. The substrate 1 is made of GaAs, and the semiconductor layer 2 includes a GaAs buffer layer, an InGaAs channel layer, an AlGaAs barrier layer, an InGaP barrier layer, and a GaAs capping layer arranged sequentially from bottom to top on one side of the substrate 1. The semiconductor layer 2 also has an isolation region 21, which is located between the pHEMT device 100 and the PIN antistatic structure 200, and between the PIN antistatic structure 200 and the semiconductor resistor 300, serving as an electrical isolation layer.

[0038] Semiconductor products typically use resistors such as ER (EPI Resistor), RER (Recessed EPI Resistor), and TFR (Thin Film Resistor). For example, a portion of the epitaxial region in the fabrication of pHEMT devices can be used to form resistors. However, simply using a pHEMT epitaxial structure as a semiconductor resistor results in a low resistance value; for example, a semiconductor resistor formed from a GaAs-based pHEMT epitaxial structure has a resistance of approximately 200 Ω / sQ. Furthermore, due to the requirements of HEMT devices, the fixed epitaxial structure results in a fixed and non-adjustable unit resistance value, limiting the application of some products in high-impedance characteristics. This invention changes the resistance value through implantation, thereby enabling the PIN structure to be used additionally for high-resistance applications. This improves the utilization rate of the P-type semiconductor layer 33 or the utilization rate of the I-type semiconductor layer 32 and the P-type semiconductor layer 33, thereby improving circuit integration efficiency. Simultaneously, by changing different implantation conditions (deeper implantation results in a larger high-resistance region, a higher sheet resistance of the PIN layer, and a higher total resistance value), the resistance of the high-resistance region can also be made controllable, suitable for resistance requirements with different sheet resistances.

[0039] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Although the present utility model has been disclosed above with reference to a preferred embodiment, it is not intended to limit the present utility model. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present utility model. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present utility model without departing from the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A semiconductor resistor, characterized by: The device comprises a substrate, a semiconductor layer, and a PIN structure stacked sequentially from bottom to top. The PIN structure includes an N-type semiconductor layer, an I-type semiconductor layer, and a P-type semiconductor layer sequentially disposed on the semiconductor layer. The thickness of the P-type semiconductor layer is H1, and the thickness of the I-type semiconductor layer is H2. In the PIN structure, an ion-implanted high-resistivity layer is provided, formed by implanting insulating ions in a top-to-bottom direction. The thickness of the ion-implanted high-resistivity layer is H, where 0 < H < H1 + H2.

2. A semiconductor resistor according to claim 1, wherein: 100nm≤H1≤500nm, 0<H≤H1.

3. A semiconductor resistor according to claim 1, wherein: 100nm≤H1≤500nm, 500nm≤H2≤2000nm, H1<H<H1+H2.

4. A semiconductor resistor as claimed in claim 1, characterized in that: The insulating ions include Ar. 2+ and He + The amount of insulating ions injected is 2 × 10⁻⁶. 11 ~4×10 12 ion / cm 2 .

5. A semiconductor resistor as claimed in claim 1, characterized in that: The thickness of the N-type semiconductor layer is 100–500 nm, the thickness of the I-type semiconductor layer is 500–2000 nm, and the thickness of the P-type semiconductor layer is 100–500 nm.

6. A semiconductor resistor as claimed in claim 1, characterized in that: The substrate is made of GaAs, and the semiconductor layer includes a GaAs buffer layer, an InGaAs channel layer, and an InGaAs channel layer arranged sequentially from bottom to top on one side of the substrate. AlGaAs barrier layer, InGaP barrier layer and GaAs capping layer.

7. A semiconductor resistor as claimed in claim 1, characterized in that: It also includes a passivation layer and a resistive connection metal layer. The passivation layer covers the PIN structure and forms an opening in the PIN structure. The resistive connection metal layer is connected to the ion-implanted high-resistivity layer through the opening.

8. A semiconductor resistor as claimed in claim 1, characterized in that: The thickness H of the ion-implanted high-resistivity layer is 150 nm, or the thickness H of the ion-implanted high-resistivity layer is 1000 nm.

9. A semiconductor resistor as claimed in claim 1, characterized in that: The semiconductor layer is made of GaAs, and the p-type semiconductor layer is made of p... + The material of the I-type semiconductor layer is i-GaAs, and the material of the N-type semiconductor layer is n-GaAs. + GaAs; or, the semiconductor layer is made of GaN, and the p-type semiconductor layer is made of p-type material. + GaN, wherein the material of the I-type semiconductor layer is i-GaN, and the material of the N-type semiconductor layer is n-GaN. + GaN.

10. An integrated pHEMT device, characterized by: Includes pHEMT devices, PIN antistatic structures, and semiconductor resistors as described in any one of claims 1 to 8.

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