ATE calibration device and ATE test system

Abstract

An ATE calibration device and ATE testing system are disclosed. The ATE calibration device is used to calibrate semiconductor testing equipment, which includes multiple control boards, at least one of which includes multiple test modules. The ATE calibration device includes a first calibration module and a second calibration module. The first calibration module is used to calibrate the test modules between control boards, while the second calibration module is used to calibrate each test module within the same control board. By cooperating with the first and second calibration modules, calibration of each test module in the semiconductor testing equipment can be achieved based on the clock signal of a single test module.

Description

Technical Field

[0001] This application belongs to the field of semiconductor testing technology, and in particular relates to an ATE calibration device and an ATE testing system. Background Technology

[0002] Currently, chips are a crucial component of electronic devices such as computers. Due to their intricate structure, complex manufacturing processes, and cumbersome procedures, potential defects are inevitably left during production, preventing the finished chips from meeting standard requirements. Therefore, to ensure chip quality, chips are typically tested, for example, by using semiconductor testing equipment to provide test signals to the chip to test its functionality.

[0003] Semiconductor testing equipment typically has multiple test terminals for connecting to the chip and multiple test modules. Each test module is used to transmit test signals to the chip through a test terminal. However, if the signal delays between the test modules are inconsistent, it will lead to inaccurate chip test results. Utility Model Content

[0004] The purpose of this application is to provide an ATE calibration device and an ATE testing system to solve the problem of inconsistent signal delays between test modules in existing semiconductor testing equipment.

[0005] A first aspect of this application provides an ATE calibration apparatus for calibrating a semiconductor testing device, the semiconductor testing device including multiple control boards, at least one control board including multiple test modules; the ATE calibration apparatus includes: a first calibration module connected to at least two of the test modules, the first calibration module being used to calibrate at least one of the test modules based on a clock signal provided by one of the test modules; and a second calibration module connected to each of the test modules in one of the control boards, the second calibration module being used to calibrate each of the test modules based on a clock signal provided by the test module calibrated by the first calibration module.

[0006] In one embodiment, the first calibration module includes a first input terminal, a plurality of first output terminals, a first buffer, and a first clock buffer; the first input terminal is used to connect to the output terminal of the control board, the first input terminal is used to receive the clock signal output by the control board, the first output terminal is used to connect to the input terminal of the control board, the input terminal of the first buffer is connected to the first input terminal, the output terminal of the first buffer is connected to the input terminal of the first clock buffer, and each output terminal of the first clock buffer is connected to each of the first output terminals.

[0007] In one embodiment, the total length of the traces from the first input terminal to each of the first output terminals is equal.

[0008] In one embodiment, the second calibration module includes a second input terminal, a plurality of second output terminals, a second buffer, and a second clock buffer; the first input terminal is used to connect to the output terminal of one of the test modules of the control board, each of the second output terminals is used to connect to the input terminal of each of the test modules of the same control board, the input terminal of the second buffer is connected to the second input terminal, the output terminal of the second buffer is connected to the input terminal of the second clock buffer, and each output terminal of the second clock buffer is connected to each of the second output terminals.

[0009] In one embodiment, the total length of the traces from the second input terminal to each of the second output terminals is equal.

[0010] In one embodiment, the semiconductor testing equipment includes a first control board and a second control board; the first calibration module is used to connect to the first control board and the second control board.

[0011] In one embodiment, the ATE calibration device includes two second calibration modules; the two second calibration modules are respectively connected to each of the test modules of the first control board and each of the test modules of the second control board.

[0012] In one embodiment, the ATE calibration device further includes a third calibration module; the third calibration module is used to short-circuit the test module of one of the control boards with the test module of the other control board.

[0013] A second aspect of this application provides an ATE testing system, including the ATE calibration apparatus and semiconductor testing equipment as described above.

[0014] In one embodiment, at least one test module of the semiconductor testing equipment includes a control unit, an output unit, an input unit, and an external switch; the input terminal of the output unit is connected to a first terminal of the control unit, the output terminal of the output unit is connected to a first terminal of the external switch, the second terminal of the external switch is used to connect to an external circuit, the input terminal of the input unit is connected to the output terminal of the output unit, and the output terminal of the input unit is connected to a second terminal of the control unit; the control unit is used to calibrate the output unit and the input unit based on the output test signal and the test signal fed back by the input unit when the external switch is disconnected.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: the first calibration module is used to calibrate the test modules between control boards, while the second calibration module is used to calibrate each test module within the same control board. Through the cooperation of the first and second calibration modules, calibration of each test module in the semiconductor testing equipment can be achieved based on the clock signal of one test module, ensuring the consistency of signal delay among all test modules. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an ATE calibration device provided in an embodiment of this application; Figure 2 A schematic diagram of a first calibration module provided in an embodiment of this application; Figure 3 A schematic diagram of a second calibration module provided in one embodiment of this application; Figure 4 This is a connection diagram of the first calibration module provided in an embodiment of this application; Figure 5 This is a connection diagram of the second calibration module provided in one embodiment of this application; Figure 6 This is a connection diagram of the third calibration module provided in one embodiment of this application; Figure 7 This is a schematic diagram of an ATE testing system provided in an embodiment of this application; Figure 8 This is a schematic diagram of one of the test modules of the ATE test system provided in an embodiment of this application. Detailed Implementation

[0017] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0021] Currently, in order to ensure the accuracy of test results from Automatic Test Equipment (ATE), calibration devices are typically used to calibrate the ATE.

[0022] Figure 1 A schematic diagram of an ATE calibration device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: An ATE calibration device 10 is provided for calibrating a semiconductor test equipment 20. The semiconductor test equipment 20 includes multiple control boards 100, and at least one control board 100 includes multiple test modules 110.

[0023] It should be noted that when the semiconductor test equipment 20 is used to test the test target, for example, when the semiconductor test equipment 20 tests the display driver IC (DDIC), each test module 110 is used to independently generate and output the set test signal based on its own clock signal.

[0024] The ATE calibration device 10 includes: a first calibration module 200 and a second calibration module 300.

[0025] The first calibration module 200 is used to connect to at least two control boards 100. The first calibration module 200 is used to transmit the clock signal provided by the test module 110 of one of the control boards 100 to the input terminal of at least one test module 110 in each control board 100. The test module 110 is configured to perform self-calibration based on the signal at the input terminal of the test module 110.

[0026] The second calibration module 300 is used to connect to each test module 110 in a control board 100. The second calibration module 300 is used to transmit the clock signal provided by the calibrated test module 110 to the input terminal of each test module 110.

[0027] It is understandable that when the test module 110 receives the clock signal output by the ATE calibration device 10, the test module 110 can configure its own clock signal according to the parameters of the received clock signal to complete self-calibration.

[0028] The first calibration module 200 is used to calibrate the test modules 110 between control boards 100, while the second calibration module 300 is used to calibrate each test module 110 within the same control board 100. Through the cooperation of the first calibration module 200 and the second calibration module 300, each test module 110 in the semiconductor testing equipment 20 can be calibrated based on the clock signal provided by one test module 110, ensuring the consistency of signal delay among all test modules 110.

[0029] In one embodiment, such as Figure 2 As shown, the first calibration module 200 includes a first input terminal 210, a plurality of first output terminals 220, a first buffer 230 and a first clock buffer 240.

[0030] The first input terminal 210 is used to connect to the output terminal of the test module 110 of one of the control boards 100. The first input terminal 210 is used to receive the clock signal output by the test module 110. Multiple first output terminals 220 are used to connect to the input terminals of the test modules 110 of at least two control boards 100 respectively. The input terminal of the first buffer 230 is connected to the first input terminal 210. The output terminal of the first buffer 230 is connected to the input terminal of the first clock buffer 240. Each output terminal of the first clock buffer 240 is connected one-to-one with each first output terminal 220.

[0031] After receiving the clock signal, the first input terminal 210 transmits the clock signal sequentially through the first buffer 230, the first clock buffer 240 and the first output terminal 220 to the input terminal of the test module 110. After receiving the clock signal, the input terminal of the test module 110 can perform self-calibration based on the received clock signal.

[0032] The first buffer 230 is used to achieve isolation between circuits, while the first clock buffer 240 is used to generate and output multiple identical clock signals based on a clock signal.

[0033] The first calibration module 200 can be used to achieve synchronous calibration of the test modules 110 in different control boards 100.

[0034] It is understood that each test module 110 may be provided with at least one external terminal, which, depending on its specific function, can be pluggably connected to the first input terminal 210 or the first output terminal 220 via corresponding connection lines. In some embodiments, the output terminal of the test module 110 is provided with an external terminal, and the input terminal of the test module 110 is provided with an external terminal.

[0035] In one embodiment, the total length of the traces from the first input terminal 210 to each of the first output terminals 220 is equal. This avoids changes in the time delay of the signals output by each of the first output terminals 220 due to differences in trace length, thus ensuring the consistency of the signals output by each of the first output terminals 220.

[0036] In some embodiments, such as Figure 2 As shown, switching devices are also provided between the first clock buffer 240 and the first buffer 230, and between the first clock buffer 240 and each of the first output terminals 220. It can be understood that the calibration process of the ATE calibration device 10 can be controlled by selectively disconnecting some of the switching devices.

[0037] In one embodiment, such as Figure 3 As shown, the second calibration module 300 includes a second input terminal 310, a plurality of second output terminals 320, a second buffer 330, and a second clock buffer 240.

[0038] The second input terminal 310 is used to connect to the output terminal of one of the test modules 110 of the control board 100. Multiple second output terminals 320 are used to connect to the input terminals of each test module 110 of the same control board 100 respectively. The input terminal of the second buffer 330 is connected to the second input terminal 310. The output terminal of the second buffer 330 is connected to the input terminal of the second clock buffer 240. Each output terminal of the second clock buffer 240 is connected one-to-one with each second output terminal 320.

[0039] After receiving the clock signal, the second input terminal 310 transmits the clock signal sequentially through the second buffer 330, the second clock buffer 240, and the second output terminal 320 to the input terminal of the test module 110. After receiving the clock signal, the input terminal of the test module 110 can perform self-calibration based on the received clock signal.

[0040] The second calibration module 300 can be used to synchronously calibrate each test module 110 in the same control board 100.

[0041] By using the second calibration module 300 in conjunction with the first calibration module 200, each test module 110 of multiple control boards 100 can be synchronously calibrated, thus avoiding inconsistent time delays in the test signals output by some test modules 110 when the semiconductor test equipment 20 is testing the target, which would affect the test results.

[0042] In one embodiment, the total length of the traces from the second input terminal 310 to each of the second output terminals 320 is equal. This avoids changes in the time delay of the signals output by each of the second output terminals 320 due to differences in trace length, thus ensuring the consistency of the signals output by each of the second output terminals 320.

[0043] In some embodiments, switching devices are provided between the second clock buffer 240 and the second buffer 330, and between the second clock buffer 240 and each of the second output terminals 320.

[0044] It should be noted that the first input terminal 210 and the second input terminal 310 can be the same terminal, and part of the first output terminal 220 and part of the second output terminal 320 can also be the same terminal.

[0045] In one embodiment, such as Figure 4 , Figure 5 As shown, the semiconductor testing equipment 20 includes a first control board 100a and a second control board 100b.

[0046] The first calibration module 200 is used to connect to one of the test modules 110 of the first control board 100a and one of the test modules 110 of the second control board 100b.

[0047] For example, the first calibration module 200 may include a first input terminal 210 and two first output terminals 220. The first input terminal 210 and one of the first output terminals 220 may be connected to the output terminal and input terminal of one of the test modules 110 of the first control board 100a, respectively, and the other first output terminal 220 may be connected to the input terminal of one of the test modules 110 of the second control board 100b. This enables synchronous calibration of one of the test modules 110 of the first control board 100a and one of the test modules 110 of the second control board 100b.

[0048] In one embodiment, the ATE calibration device 10 includes two second calibration modules 300. One second calibration module 300 is connected to each test module 110 of the first control board 100a, and the other second calibration module 300 is connected to each test module 110 of the second control board 100b.

[0049] When the first calibration module 200 works in conjunction with the second calibration module 300, synchronous calibration of each test module 110 of the first control board 100a and each test module 110 of the second control board 100b can be achieved.

[0050] In some embodiments, the test module 110 of the first control board 100a specifically includes a control unit 111 and an input unit 112 connected to the control unit 111, and the test module 110 of the second control board 100b specifically includes a control unit 111 and an input unit 112 and an output unit 113 connected to the control unit 111. The control unit 111 is used to output a clock signal and control the output unit 113 to output a test signal. The input unit 112 can transmit the received signal to the control unit 111. The control unit 111 can also calibrate the input unit 112 and the output unit 113 according to the received signal.

[0051] The control unit 111 may specifically include a field programmable gate array (FPGA) chip, the input unit 112 may specifically include a CMP chip, and the output unit 113 may specifically include a DGT chip.

[0052] In one embodiment, such as Figure 6 As shown, the ATE calibration device 10 also includes a third calibration module 400.

[0053] The third calibration module 400 is used to short-circuit the output terminal of the test module 110 of one control board 100 with the input terminal of the test module 110 of the other control board 100.

[0054] The third calibration module 400 can be connected to some special test modules 110 by shorting them up, according to the actual situation, to transmit some special signals for calibration.

[0055] For example, the testing equipment may also include a third control board 100c. The test module 110 of the third control board 100c can be used to output a drive signal. The drive signal can be transmitted to the test module 110 of the first control board 100a through the third calibration module 400. After receiving the drive signal, the test module 110 of the first control board 100a can configure the corresponding input unit 112 according to the drive signal so as to ensure normal communication with the test module 110 of the third control board 100c in the subsequent test process.

[0056] Specifically, the third calibration module 400 may include a first shorting terminal 410 and a second shorting terminal 420, the test module 110 of the third control board 100c may be a drive unit 114, the first shorting terminal 410 may be connected to the drive unit 114 of the third control board 100c, and the second shorting terminal 420 may be connected to the test module 110 of the first control board 100a.

[0057] The drive unit 114 may specifically include a drive chip. After receiving the drive signal, the test module 110 of the first control board 100a can configure its drive unit 114 and input unit 112 accordingly based on the received drive signal.

[0058] In some embodiments, the first control board 100a may be a DIG board, the second control board 100b may be an LCD board, and the third control board 100c may be an HSIF board.

[0059] Figure 7 A schematic diagram of an ATE testing system according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: An ATE test system 30 includes an ATE calibration device 10 and a semiconductor test device 20 as described in any of the above embodiments.

[0060] In one embodiment, such as Figure 8 As shown, at least one test module 110 of the semiconductor test equipment 20 includes a control unit 111, an output unit 113, an input unit 112, and an external switch S1.

[0061] The input terminal of the output unit 113 is connected to the first terminal of the control unit 111, the output terminal of the output unit 113 is connected to the first terminal of the external switch S1, the second terminal of the external switch S1 is used to connect to an external circuit, the input terminal of the input unit 112 is connected to the output terminal of the output unit 113, and the output terminal of the input unit 112 is connected to the second terminal of the control unit 111.

[0062] The control unit 111 is used to calibrate the output unit 113 and the input unit 112 based on the output test signal and the test signal fed back by the input unit 112 when the external switch S1 is off.

[0063] For some test modules 110, self-calibration can be performed by directly shorting the input terminal of the input unit 112 to the output terminal of the output unit 113.

[0064] From the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0065] It should be understood that the apparatuses and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another device. In addition, some features may be omitted or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0066] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units. That is, it can be located in one place or distributed in multiple different locations. Depending on the actual needs, some or all of the units can be selected to achieve the purpose of this solution.

[0067] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit; they can also exist physically separately; or some units can be integrated into one unit while others exist physically separately. The integrated units described above can be implemented in hardware or as software functional units.

[0068] It should be noted that all or part of the above embodiments provided in this application (e.g., part or all of any feature) can be arbitrarily combined or combined with each other.

[0069] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An ATE calibration device, characterized in that, Used for calibrating semiconductor testing equipment, the semiconductor testing equipment including multiple control boards, at least one of the control boards including multiple test modules; The ATE calibration device includes: A first calibration module is configured to connect to at least two of the control boards and transmit a clock signal provided by a test module of one of the control boards to the input of at least one test module in each control board; the test module is configured to perform self-calibration based on the signal at its input. The second calibration module is used to connect to each test module in the control board and to transmit the clock signal provided by the calibrated test module to the input terminal of each test module.

2. The ATE calibration device as described in claim 1, characterized in that, The first calibration module includes a first input terminal, multiple first output terminals, a first buffer, and a first clock buffer; The first input terminal is used to connect to the output terminal of the test module of one of the control boards. The first input terminal is used to receive the clock signal output by the test module. A plurality of first output terminals are used to connect to the input terminals of the test modules of at least two of the control boards respectively. The input terminal of the first buffer is connected to the first input terminal. The output terminal of the first buffer is connected to the input terminal of the first clock buffer. Each output terminal of the first clock buffer is connected one-to-one with each of the first output terminals.

3. The ATE calibration device as described in claim 2, characterized in that, The total length of the traces from the first input terminal to each of the first output terminals is equal.

4. The ATE calibration device as described in claim 1, characterized in that, The second calibration module includes a second input terminal, multiple second output terminals, a second buffer, and a second clock buffer; The second input terminal is used to connect to the output terminal of one of the test modules of the control board, and the plurality of second output terminals are used to connect to the input terminals of each of the test modules of the same control board respectively. The input terminal of the second buffer is connected to the second input terminal, the output terminal of the second buffer is connected to the input terminal of the second clock buffer, and each output terminal of the second clock buffer is connected to each of the second output terminals one-to-one.

5. The ATE calibration device as described in claim 4, characterized in that, The total length of the traces from the second input terminal to each of the second output terminals is equal.

6. The ATE calibration apparatus as described in claim 1, characterized in that, The semiconductor testing equipment includes a first control board and a second control board; the first calibration module is used to connect to one of the test modules of the first control board and one of the test modules of the second control board.

7. The ATE calibration apparatus as described in claim 6, characterized in that, The ATE calibration device includes two second calibration modules; one of the second calibration modules is used to connect to each of the test modules of the first control board, and the other of the second calibration modules is used to connect to each of the test modules of the second control board.

8. The ATE calibration apparatus according to any one of claims 1 to 7, characterized in that, The ATE calibration device also includes a third calibration module; The third calibration module is used to short-circuit the output terminal of the test module of one of the control boards with the input terminal of the test module of the other control board.

9. An ATE testing system, characterized in that, Includes the ATE calibration apparatus and semiconductor testing equipment as described in any one of claims 1 to 8.

10. The ATE testing system as described in claim 9, characterized in that, At least one test module of the semiconductor testing equipment includes a control unit, an output unit, an input unit, and an external switch; The input terminal of the output unit is connected to the first terminal of the control unit, the output terminal of the output unit is connected to the first terminal of the external switch, the second terminal of the external switch is used to connect to an external circuit, the input terminal of the input unit is connected to the output terminal of the output unit, and the output terminal of the input unit is connected to the second terminal of the control unit. The control unit is used to calibrate the output unit and the input unit based on the output test signal and the test signal fed back by the input unit when the external switch is off.

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