Power management integrated circuits and electronic devices

Abstract

This disclosure provides a power management integrated circuit and an electronic device. The power management integrated circuit includes: an internal logic device; and a reset module connected to a power button. The reset module is used to perform a reset operation on the internal logic device according to the operation signal of the power button. The power management integrated circuit provided by this disclosure reduces the manufacturing cost and footprint of the circuit and frees up some general-purpose input / output resources of the application processor. Furthermore, the embodiments provided by this disclosure can still initialize the internal logic elements of the circuit and restore the normal power supply control process even in extreme situations such as system crashes, application processor freezes, and battery depletion, thereby significantly improving the robustness of the reset operation and greatly enhancing the user experience.

Description

Technical Field

[0001] This disclosure relates to the field of power management technology, and more particularly to power management integrated circuits and electronic devices. Background Technology

[0002] In electronic devices such as mobile phones and tablets, in order to provide effective management and control of system power, device manufacturers usually design power management integrated circuits (PMICs) and configure them in electronic devices to provide power supply, system load reset and other power control functions.

[0003] When electronic devices require initialization due to factors such as system crashes or power depletion, power management integrated circuits are typically needed to perform the initialization process. However, in related technologies, power management integrated circuits often fail when these factors occur, thus failing to complete the initialization process and causing the system to remain inoperable, resulting in a poor user experience. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides a power management integrated circuit and an electronic device.

[0005] A first aspect of this disclosure provides a power management integrated circuit, the circuit comprising:

[0006] Internal logic devices;

[0007] A reset module connected to a power button, the reset module being connected to the internal logic device, the reset module being used to perform a reset operation on the internal logic device according to the operation signal of the power button.

[0008] Optionally, the circuit further includes:

[0009] A judgment module located between the reset module and the power button is used to control the reset module to perform a reset operation on the internal logic device based on the duration of the operation signal of the power button.

[0010] Optionally, the determination module includes:

[0011] A timing module is used to determine the duration of the operation signal of the power button.

[0012] Optionally, the timing module includes a resistor-capacitor oscillator.

[0013] Optionally, the circuit further includes:

[0014] A system switch used to connect to the battery and the equipment load, used to control the on / off connection of the power supply between the battery and the equipment load;

[0015] The judgment module is connected to the system switch and is used to control the system switch to disconnect the power supply connection between the battery and the device load according to the operation signal of the power button, and to reconnect the power supply connection between the battery and the device load after a reset time.

[0016] Optionally, when the determination module controls the reset module to perform a reset operation on the internal logic device, it is used to:

[0017] Disconnect the power supply connection between the battery and the device load, control the reset module to perform a reset operation on the internal logic device, and reconnect the power supply connection between the battery and the device load after the reset time.

[0018] The reset operation is completed within the reset duration.

[0019] Optionally, the determination module is configured as follows:

[0020] If the duration of the power button operation signal reaches a first threshold, the power supply connection between the battery and the device load is disconnected, and the power supply connection between the battery and the device load is reconnected after a reset duration.

[0021] If the duration of the operation signal of the power button reaches a second threshold, the reset module is controlled to perform a reset operation on the internal logic device.

[0022] Wherein, the first threshold is less than the second threshold.

[0023] Optionally, the circuit further includes:

[0024] An OR gate is provided between the reset module and the judgment module, the output of the OR gate is connected to the reset module, and the multiple inputs of the OR gate are respectively connected to the judgment module and the power-on reset module;

[0025] The power-on reset module is used to send a reset signal to the OR gate when the circuit is powered on.

[0026] Optionally, the internal logic device includes registers and / or a controller.

[0027] A second aspect of this disclosure provides a power management integrated chip, the power management integrated chip including the power management integrated circuit as described in the first aspect.

[0028] A third aspect of this disclosure provides an electronic device equipped with the power management integrated circuit described in the first aspect or the power management integrated chip described in the second aspect.

[0029] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0030] In this embodiment, the reset module's reset operation of internal logic elements does not rely on the device's internal processor. Instead, it directly receives signals from the user via a connection to the power button. This saves a pin on the power management integrated circuit, reducing manufacturing costs and footprint, and freeing up some general-purpose input / output resources of the application processor. Furthermore, since the power button signal is unaffected by system crashes, application processor freezes, or battery depletion, the above implementation will not fail when these factors occur. Even in extreme cases such as system crashes, application processor freezes, or battery depletion, the internal logic elements of the circuit can still be initialized to restore normal power supply control, thereby significantly improving the robustness of the reset operation and enhancing the user experience.

[0031] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0032] The accompanying drawings, which are incorporated in and form part of this disclosure, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0033] Figure 1 These are schematic diagrams illustrating a power management integrated circuit through some exemplary embodiments.

[0034] Figure 2 This is a schematic diagram illustrating another power management integrated circuit with some exemplary embodiments.

[0035] Figure 3 These are schematic diagrams illustrating another power management integrated circuit using some exemplary embodiments.

[0036] Figure 4 This is a control schematic diagram of a power management integrated circuit illustrated in some exemplary embodiments.

[0037] Figure 5 These are hardware structure diagrams of an electronic device illustrated by some exemplary embodiments. Detailed Implementation

[0038] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of power management integrated circuits and electronic devices consistent with some aspects of this disclosure as detailed in the appended claims.

[0039] In electronic devices such as mobile phones and tablets, in order to provide effective management and control of system power, device manufacturers usually design power management integrated circuits (PMICs) and configure them in electronic devices to provide power supply, system load reset and other power control functions.

[0040] When electronic devices require initialization due to factors such as system crashes or power depletion, power management integrated circuits are typically needed to perform the initialization process. However, in related technologies, power management integrated circuits often fail when these factors occur, thus failing to complete the initialization process and causing the system to remain inoperable, resulting in a poor user experience.

[0041] Specifically, please see Figure 1 This is an exemplary power management integrated circuit design. VBUS, RST, and PWRKEY are pins on the PMIC. The VBUS pin can be used to connect to external power supply modules such as chargers. The PWRKEY pin can be used to receive operation signals from the power key (also known as the power on / off button) (e.g., the power key being pressed and unpressed). The RST pin is used to connect to the GPIO (General Purpose Input / Output) of the application processor (AP). The PMIC can receive the reset signal sent by the AP through the RST pin and perform a reset operation on the internal logic elements based on the reset signal. The BATFET is connected to the battery-powered VBAT and the system load power supply VSYS, and is mainly used to control the power supply strategy and power on / off of external loads (hereinafter referred to as system loads) such as the application processor, system power IC, and peripheral power IC. Figure 1 In the example shown, the BATFET is connected to the PWRKEY pin, thereby controlling the power supply strategy for the system load based on the user's operation signal to the power button, such as powering down the system load after the user has pressed the power button for 15 seconds (Timer).

[0042] Internal logic elements are some or all of the logic elements included in a PMIC used to implement the inherent functions of the PMIC (such as controlling the power supply to the system load). These logic elements are typically electronic components with reset value (i.e., initialization requirements, or reset requirements). In simpler terms, in a circuit, one type of component has initialization requirements, such as registers, controllers, and some unmentioned programmable logic devices. They need to be correctly initialized when the chip is powered on (or at other necessary moments) to ensure the normal operation of the system. These components typically participate in logic operations and control processes, so their initial state settings are crucial to the system's functionality and performance. The other type of component does not have initialization requirements, such as basic connection components like wires, resistors, and capacitors. These components are typically used for basic functions such as transmitting current, adjusting voltage, and limiting current, and do not require specific initialization settings.

[0043] During application, both the PMIC and the system load require reset. However, in Figure 1 In the design shown, the PMIC may fail to reset. For example, in extreme cases such as system crashes or device freezes, the AP may be unable to control the GPIO, thus preventing the power management chip from being reset. Similarly, when the phone battery is low and enters an undervoltage shutdown state, the phone cannot power on, the AP cannot function, and therefore cannot send a reset signal to the PMIC's RST pin via GPIO to reset the power management chip. If the PMIC's internal logic devices malfunction in this situation, even if the user plugs in a charger, the electronic device cannot complete the normal charging and power-on process, resulting in the system remaining unusable and a poor user experience.

[0044] In view of the above, this disclosure provides a power management integrated circuit and an electronic device. The embodiments of this disclosure will now be described in detail.

[0045] This disclosure provides a power management integrated circuit, which can be applied to electronic devices such as mobile phones and tablets. Please refer to [link to relevant documentation]. Figure 2 The electronic device may include an internal logic device and a reset module, wherein the reset module is connected to the internal logic device and a power button, and is used to perform a reset operation on the internal logic device according to the operation signal of the power button.

[0046] In a power management system (PMIC), registers are typically used to store power management-related settings, such as power output voltage, current limits, and power management modes. Through read and write operations on these registers, the PMIC can configure and control power management functions. The controller is a key functional module in the PMIC, used to control the power supply's operating state and output. Controllers in a PMIC may include switching controllers, regulator controllers, clock controllers, etc. Switching controllers control the power supply's switching state, including switching inputs and outputs, to achieve different power supply voltages and current outputs. These are the main modules in the PMIC that have reset capabilities. Therefore, optionally, the internal logic devices in this disclosure may include at least one register and at least one controller set in the PMIC, thereby covering the reset scope as much as possible to the main components in the PMIC that require reset, ensuring the normal operation of the PMIC.

[0047] In the reset operation of the internal logic device of the PMIC, a hardware reset method can be optionally used, such as powering down and then powering on the internal logic device; alternatively, a software reset method can be selected, such as setting the pre-configured control bit in the software register to 1, thereby performing a software reset on the register (this reset method can be triggered by the AP through the Inter-Integrated Circuit (i.e., I2C) bus), and this disclosure does not limit it.

[0048] exist Figure 1 In the example shown, since the reset signal is controlled via the application processor's GPIO, a GPIO pin needs to be allocated on the application processor to control the power management chip's reset. This not only occupies the AP's GPIO resources and limits the implementation of other functions, but also increases the manufacturing cost and pin area of ​​the PMIC. In the above implementation, the reset module's reset operation of internal logic elements does not depend on the AP. Instead, it connects to the PWRKEY and directly receives signals from the user via the power button. This saves a PMIC pin, reducing the PMIC's manufacturing cost and area, and freeing up some of the AP's GPIO resources. Furthermore, since the power button signal is unaffected by system crashes, AP freezes, or battery depletion, the above implementation will not fail when these factors occur. Even in extreme cases such as system crashes, AP freezes, or battery depletion, the PMIC's internal logic elements can still be initialized to restore normal power supply control, thus significantly improving the robustness of the reset operation and enhancing the user experience.

[0049] In some embodiments, the circuit further includes a determination module. The determination module may be located between the reset module and the power button, and is used to control the reset module to perform a reset operation on the internal logic device based on the duration of the operation signal of the power button.

[0050] The advantage of this approach is that it allows the reset process for internal logic devices to better align with real-world user habits. Resetting the PMIC's internal logic devices can be achieved directly by pressing and holding the power button, improving the user experience. Simultaneously, it allows a single power button to be reused for multiple functions. For example, the judgment module can control the BATFET to reset the system load when the user presses the power button for a first duration t1. Then, when the user presses the power button for a second duration t2, it determines that a PMIC reset is needed and controls the reset module to perform the reset operation.

[0051] Specifically, the determination module may include a timing module for determining the duration of the power button's operation signal. This timing module can be implemented based on a resistor-capacitor oscillator (RC oscillating clock), thereby providing accurate timing functionality while maintaining low cost. See also... Figure 3 The RC oscillation clock and timer (which can be some components related to duration judgment) can be regarded as a judgment module.

[0052] In some embodiments, the circuit further includes a system switch, which can be connected to the battery and the device load to control the on / off connection of the power supply between the battery and the device load; and the judgment module can be connected to the system switch to control the system switch to disconnect the power supply connection between the battery and the device load according to the operation signal of the power button, and to reconnect the power supply connection between the battery and the device load after a reset time. Figure 3 In this configuration, the entire assembly consisting of the BATFET controller and the switching transistor Q4 can be considered as the system switch. Therefore, the decision module can control both the system switch and the reset module, thereby resetting the system load and achieving the functional multiplexing of a single power button as described above.

[0053] Since PMICs are typically used to control the power supply to the system load, to avoid the potential impact of PMIC reset on the system load, optionally, the judgment module controls the reset module to perform a reset operation on the internal logic device by: disconnecting the power supply connection between the battery and the device load, controlling the reset module to perform a reset operation on the internal logic device, and reconnecting the power supply connection between the battery and the device load after the reset duration; wherein the reset operation is completed within the reset duration.

[0054] In other words, when performing a reset operation on the internal logic device, the VSYS can be powered down first, and the power supply to the VSYS can be restored after the reset time Δt. The reset of the internal logic module can be completed within Δt.

[0055] Furthermore, this disclosure also provides a specific method for reusing the power button, namely, the determination module is configured as follows:

[0056] If the duration of the power button operation signal reaches a first threshold, the power supply connection between the battery and the device load is disconnected, and the power supply connection between the battery and the device load is reconnected after a reset duration.

[0057] When the duration of the operation signal of the power button reaches a second threshold, the reset module is controlled to perform a reset operation on the internal logic device; wherein the first threshold is less than the second threshold.

[0058] In the above implementation, when the user continuously triggers the power button operation signal, the system load is first power-down reset, and then the PMIC is reset when the user continues to trigger the power button operation signal. This not only conforms to the user's operating intuition, but also matches the situation in actual applications where the reset requirement for the system load is greater than the reset requirement for the PMIC, thereby reducing unnecessary reset operations.

[0059] In some embodiments, the reset operation performed by the reset module on its internal logic elements can be triggered not only by the judgment module but also by other modules. For example, the circuit further includes an OR gate disposed between the reset module and the judgment module, the output of the OR gate being connected to the reset module, and the plurality of inputs of the OR gate being connected to the judgment module and the power-on reset module, respectively; wherein, the power-on reset module is used to send a reset signal to the OR gate when the circuit is powered on.

[0060] The reset signal sent by the power-on reset module to the OR gate is in Figure 3This is called Power-On Reset. For example, when the VBUS voltage or VBAT voltage is greater than a certain value, the power-on reset module can consider the chip to be powered on successfully (that is, there is power from the battery or charger connected to the PMIC at this time, in other words, the PMIC has a power source at this time), and can then trigger a reset of the PMIC to ensure that the PMIC can perform its functions normally. Figure 3 The Regreset shown is a software register reset, which is a software reset method. Reg-reset can be the output of a digital circuit and can be used to instruct the PMIC to perform a reset at the software level.

[0061] Since the reset module is typically configured to perform a reset operation in response to a low-active reset signal, while the reset signals issued by the judgment module and the power-on reset module are typically high-active, a NOT gate can be connected in series between the OR gate and the reset module to form a low-active reset signal to trigger the reset operation of the reset module, thus forming a... Figure 3 The circuit shown is shown.

[0062] The following combination Figure 4 The control diagram shown provides a comprehensive explanation of some of the above embodiments. Here, VBAT refers to the battery power supply, VSYS refers to the PMIC power supply to the system load, PWRKEY refers to whether the power button is pressed, and "reset module" refers to the current operating state of the reset module. First, VBAT is powered on, at which point the PMIC can perform a power-on reset (…). Figure 4 (Not shown in the image), next, the user presses the power button.

[0063] When the user presses the power button for time t1, the judgment module can send a system reset signal to control the on / off state of the system switch, thereby controlling the system switch to disconnect the power supply connection between the battery and the device load, and then reconnect the power supply connection between the battery and the device load after a reset time. It should be understood that when the input of the OR gate is connected in parallel with the system switch to the judgment module, the system reset signal sent by the judgment module can be transmitted to both the OR gate and the system switch. Therefore, the OR gate or reset module can be set not to respond to the system reset signal, so that the system reset signal is only used to control the system switch.

[0064] When the user continues to press the power button for t2, the judgment module can send a reset signal to the reset module. This reset signal is used to control the reset module to perform a reset operation on the internal logic devices. When the input of the OR gate is connected in parallel with the system switch to the judgment module, the system switch can be configured to perform a power-down / power-on operation on the system load when it receives the aforementioned system reset signal or a reset signal. In this case, the judgment module can send only a reset signal to simultaneously control the system switch and the reset module. Alternatively, the system switch can be configured to respond only to the aforementioned system reset signal, and then the judgment module can respond to the user continuously pressing the power button for t2 by simultaneously sending a reset signal and a system reset signal, thereby controlling the system switch to perform a power-down / power-on operation on VSYS and the reset module to perform a reset operation on the internal logic devices.

[0065] After another Δt time, the internal components of the PMIC and the system load have completed the reset process.

[0066] Secondly, this disclosure also provides a power management integrated chip equipped with the power management integrated circuit as described in the first aspect. The chip can be a pre-packaged product, in which the power management integrated circuit provided in this disclosure is designed.

[0067] Thirdly, this disclosure also provides an electronic device equipped with a power management integrated circuit as described in the first aspect or a power integrated management chip as described in the second aspect. Please refer to [link to relevant documentation]. Figure 5 The illustration exemplifies a hardware schematic of an electronic device. For example, device 500 could be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0068] Device 500 may include one or more of the following components: processing component 501, memory 502, power supply component 503, multimedia component 504, audio component 505, input / output (I / O) interface 506, sensor component 507, and communication component 508.

[0069] Processing component 501 typically controls the overall operation of device 500, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 501 may include one or more processors 509 to execute instructions to perform the control logic associated with the aforementioned circuitry. Furthermore, processing component 501 may include one or more modules to facilitate interaction between processing component 501 and other components. For example, processing component 501 may include a multimedia module to facilitate interaction between multimedia component 504 and processing component 501.

[0070] Memory 502 is configured to store various types of data to support the operation of device 500. Examples of this data include instructions for any application or circuitry operating on device 500, contact data, phonebook data, messages, pictures, videos, etc. Memory 502 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0071] The power supply component 503 provides power to the various components of the device 500. The power supply component 503 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device 500.

[0072] Multimedia component 504 includes a screen that provides an output interface between the device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, swipe, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 504 includes a front-facing camera and / or a rear-facing camera. When the device 500 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0073] Audio component 505 is configured to output and / or input audio signals. For example, audio component 505 includes a microphone (MIC) configured to receive external audio signals when device 500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 502 or transmitted via communication component 508. In some embodiments, audio component 505 also includes a speaker for outputting audio signals.

[0074] I / O interface 506 provides an interface between processing component 501 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0075] Sensor assembly 507 includes one or more sensors for providing state assessments of various aspects of device 500. For example, sensor assembly 507 can detect the on / off state of device 500, the relative positioning of components such as the display and keypad of device 500, changes in the position of device 500 or a component of device 500, the presence or absence of user contact with device 500, the orientation or acceleration / deceleration of device 500, and temperature changes of device 500. Sensor assembly 507 may also include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 507 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 507 may also include an accelerometer, a gyroscope, a magnetometer, a pressure sensor, or a temperature sensor.

[0076] Communication component 508 is configured to facilitate wired or wireless communication between device 500 and other devices. Device 500 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G or 5G, or combinations thereof. In one exemplary embodiment, communication component 508 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 508 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0077] In an exemplary embodiment, device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to support the aforementioned power management integrated circuits.

[0078] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0079] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention applied herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not claimed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0080] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0081] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A power management integrated circuit, characterized by, The circuit includes: Internal logic devices; A reset module connected to a power button, the reset module being connected to the internal logic device, the reset module being used to perform a reset operation on the internal logic device according to the operation signal of the power button.

2. The power management integrated circuit of claim 1, wherein, The circuit also includes: A judgment module located between the reset module and the power button is used to control the reset module to perform a reset operation on the internal logic device based on the duration of the operation signal of the power button.

3. The power management integrated circuit of claim 2, wherein, The judgment module includes: A timing module is used to determine the duration of the operation signal of the power button.

4. The power management integrated circuit of claim 3, wherein, The timing module includes a resistor-capacitor oscillator.

5. The power management integrated circuit of claim 2, wherein, The circuit also includes: A system switch used to connect to the battery and the equipment load, used to control the on / off connection of the power supply between the battery and the equipment load; The judgment module is connected to the system switch and is used to control the system switch to disconnect the power supply connection between the battery and the device load according to the operation signal of the power button, and to reconnect the power supply connection between the battery and the device load after a reset time.

6. The power management integrated circuit of claim 5, wherein, When the judgment module controls the reset module to perform a reset operation on the internal logic device, it is used for: Disconnect the power supply connection between the battery and the device load, control the reset module to perform a reset operation on the internal logic device, and reconnect the power supply connection between the battery and the device load after the reset time. The reset operation is completed within the reset duration.

7. The power management integrated circuit of claim 5, wherein, The judgment module is configured as follows: If the duration of the power button operation signal reaches a first threshold, the power supply connection between the battery and the device load is disconnected, and the power supply connection between the battery and the device load is reconnected after a reset duration. If the duration of the operation signal of the power button reaches a second threshold, the reset module is controlled to perform a reset operation on the internal logic device. Wherein, the first threshold is less than the second threshold.

8. The power management integrated circuit of claim 2, wherein, The circuit also includes: An OR gate is provided between the reset module and the judgment module, the output of the OR gate is connected to the reset module, and the multiple inputs of the OR gate are respectively connected to the judgment module and the power-on reset module; The power-on reset module is used to send a reset signal to the OR gate when the circuit is powered on.

9. The power management integrated circuit of claim 1, wherein, The internal logic devices include registers and / or controllers.

10. A power supply integrated management chip, characterized by comprising: The power management integrated chip includes the power management integrated circuit as described in any one of claims 1 to 9.

11. An electronic device, comprising: The electronic device is equipped with a power management integrated circuit as described in any one of claims 1 to 9 or a power management integrated chip as described in claim 10.

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