An adaptive zero-current turn-off synchronous rectification control circuit

Abstract

This invention discloses an adaptive zero-current turn-off synchronous rectification control circuit, comprising: an OFF dead-time module, a counting module, and an adjustable reference voltage module connected sequentially; the OFF dead-time module is used to continue detecting the drain-source voltage of the switching transistor component after it is turned off, and outputs a level signal by comparing the drain-source voltage with a reference voltage threshold and the OFF dead-time with a reference time threshold; the counting module is used to detect the output level signal when the trigger delay signal of the drain-source voltage is at its rising edge; if the output level signal is low, the output result is decremented; if the output level signal is high, the output result is incremented; the adjustable reference voltage module is used to adjust the bias current according to the output result of the counting module, thereby gradually adjusting the reference voltage threshold. This solution enables the switching transistor component to turn off when the current truly crosses zero, reducing system losses and improving system efficiency.

Description

Technical Field

[0001] This utility model relates to the field of power supply and charging technology, and in particular to an adaptive zero-current shutdown synchronous rectification control circuit. Background Technology

[0002] Flyback power supply topologies are a common AC-DC power solution widely used in charging solutions for various electronic products. Common operating modes include CCM (Continuous On-Mode), QR (Quasi-Resonant Mode), and DCM (Discontinuous On-Mode). Among these three modes, QR and DCM effectively avoid the problem of simultaneous conduction of the primary and secondary MOSFETs. Both control modes force the system to turn off the secondary MOSFET when the current crosses zero, allowing the system to enter a resonant mode where both primary and secondary MOSFETs are off. Then, the primary controller decides whether to turn on the primary MOSFET based on loop adjustment needs, thus effectively avoiding the risk of simultaneous conduction of both primary and secondary MOSFETs.

[0003] Please refer to Figure 1 , Figure 1 This is a circuit diagram of a flyback power supply system in the prior art. In actual operation, the primary-side MOSFET and the secondary-side MOSFET of the transformer will alternately conduct to transfer energy. Their conduction and cutoff are controlled by the primary-side controller and the secondary-side synchronous rectification controller, respectively. During actual system operation, due to transformer isolation, the primary-side controller and the secondary-side synchronous rectification controller cannot directly transmit signals, which poses a risk to system control. If the primary and secondary MOSFETs conduct simultaneously, it will cause an instantaneous surge of energy, leading to system failure. In the above system, the VD_SR pin of the synchronous rectification controller is connected to the drain of the MOSFET. When the MOSFET current crosses zero, the voltage drop across the MOSFET drain and source is zero. Synchronous rectification turns off the MOSFET by comparing VD_SR with a zero reference voltage. The key waveform is shown below. Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram of key waveforms in QR mode for a flyback power supply system in the prior art. Figure 3 This is a schematic diagram of the key waveforms of a flyback power supply system in DCM mode in the prior art.

[0004] In practical systems, MOSFET packages have parasitic inductance (equivalent to Ld), as shown in the schematic diagram. Figure 4 As shown, Figure 4This is a circuit diagram illustrating the parasitic inductance of the synchronous rectifier MOSFET package in a flyback power supply system in the prior art. The value of Ld varies depending on the MOSFET package, typically ranging from a few nH to tens of nH. Based on the electrical characteristics of the inductor (V=Ld*di / dt), a voltage drop will be generated across the parasitic inductance during actual circuit operation, causing an error between the voltage drop sampled by the synchronous rectifier controller and the voltage drop of the MOSFET itself. Due to this error voltage, the synchronous rectifier MOSFET will turn off prematurely, and its key waveform is shown below. Figure 5 As shown, Figure 5 This is a schematic diagram of the actual waveform of the parasitic inductance of the synchronous rectification MOSFET package in a flyback power supply system in the prior art. When the MOSFET is turned off prematurely, the Id current will be freewheeled by the MOSFET's body diode. Since the voltage drop of the body diode is approximately -0.7V, which is much larger than the voltage drop when the MOSFET is on (typically <100mV), this will lead to increased system losses and reduced efficiency. Because the value of Ld varies in different packages, the error voltage also varies. The synchronous rectification chip cannot be set to a suitable fixed voltage value to offset the influence of the error voltage in order to achieve the purpose of precise turn-off when the MOSFET current crosses zero.

[0005] In view of this, it is necessary to propose improvements to the current MOSFET current zero-crossing turn-off circuit. Utility Model Content

[0006] To solve at least one of the above-mentioned technical problems, the main objective of this utility model is to provide an adaptive zero-current shutdown synchronous rectification control circuit.

[0007] To achieve the above objectives, the present invention provides an adaptive zero-current turn-off synchronous rectification control circuit, comprising: a zero-crossing turn-off comparator, a conduction judgment circuit, and a logic and drive circuit connected in sequence. The zero-crossing turn-off comparator and the conduction judgment circuit are respectively connected to the drain of the switching transistor assembly, and the logic and drive circuit is connected to the gate of the switching transistor assembly. The circuit further comprises: an OFF dead-time module, a counting module, and an adjustable reference voltage module connected in sequence. The OFF dead-time module is electrically connected to a parasitic inductor, and the adjustable reference voltage module is electrically connected to the inverting terminal of the zero-crossing turn-off comparator. The OFF dead time module is used to continue detecting the drain-source voltage of the switching transistor component after it is turned off. If the drain-source voltage is lower than the reference voltage threshold, it indicates that the switching transistor component is in the freewheeling conduction state after being turned off. The module also detects the duration of the corresponding OFF dead time and compares it with the reference time threshold. If the OFF dead time is greater than the reference time threshold, a high-level signal is output when the drain-source voltage trigger signal is a rising edge after the drain-source voltage is greater than the reference voltage threshold; a low-level signal is output when the drain-source voltage trigger signal is a rising edge after the drain-source voltage is less than or equal to the reference voltage threshold. The counting module is electrically connected to the OFF dead time module and is used to detect the output level signal of the OFF dead time module when the trigger delay signal of the drain-source voltage is a rising edge; if the output level signal of the OFF dead time module is low, the output result is decremented; if the output level signal of the OFF dead time module is high, the output result is incremented. The adjustable reference voltage module is electrically connected to the counting module and is used to adjust the bias current according to the output of the counting module, thereby gradually adjusting the reference voltage threshold.

[0008] The OFF dead time module includes a trigger unit, an OFF dead time detection unit, a delay unit, and a trigger. The trigger unit is connected to the trigger and is used to generate a trigger signal. The OFF dead time detection unit is electrically connected to the delay unit and is used to detect the duration of the OFF dead time. The delay unit is used to generate a reference time threshold.

[0009] The triggering unit includes a first switching transistor unit, a second switching transistor unit, and an inverter. The drain of the first switching transistor unit is connected to a parasitic inductor, the source of the first switching transistor unit is connected to the gate of the second switching transistor unit, the gate of the first switching transistor unit is connected to a preset voltage, the drain of the second switching transistor unit is connected to a reference voltage, and the source of the second switching transistor unit is grounded. The input terminal of the inverter is connected to the drain of the second switching transistor unit, and the output terminal of the inverter is connected to the trigger terminal of the trigger.

[0010] The delay unit includes a first resistor and a first capacitor connected in series. The first resistor is connected to the OFF dead time detection unit, the first capacitor is grounded, and the common node connecting the first resistor and the first capacitor is electrically connected to the data terminal of the trigger.

[0011] The delay time of the delay unit is two or more delay units.

[0012] The delay unit is a hysteresis comparator, a timer, or a delay chip.

[0013] The OFF dead time module further includes a delay comparator, the input of which is connected to the output of an inverter, and the output of which is connected to the counting module of the counting module.

[0014] The adjustable reference voltage unit is used to adjust the reference current or resistance to adjust the bias current.

[0015] The technical solution of this utility model mainly adopts an OFF dead-time module, a counting module, and an adjustable reference voltage module. The OFF dead-time module is used to continue detecting the drain-source voltage of the switching transistor assembly after it is turned off. It outputs a level signal by comparing the drain-source voltage with a reference voltage threshold and the OFF dead-time with a reference time threshold. The counting module detects the output level signal of the OFF dead-time module when the trigger delay signal of the drain-source voltage is at its rising edge. If the output level signal of the OFF dead-time module is low, the output result is decremented; if it is high, the output result is incremented. The adjustable reference voltage module adjusts the bias current based on the output result of the counting module, thereby gradually adjusting the reference voltage threshold. Thus, by implementing this solution, the switching transistor assembly can be turned off when the current truly crosses zero, reducing system losses and improving system efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a circuit diagram of a flyback power supply system in the prior art; Figure 2 This is a schematic diagram of key waveforms in QR mode for a flyback power supply system in the prior art; Figure 3 This is a schematic diagram of key waveforms in the DCM mode of a flyback power supply system in the prior art; Figure 4 This is a circuit diagram of the parasitic inductance of the synchronous rectifier MOSFET package in a flyback power supply system in the prior art; Figure 5 This is a schematic diagram of the actual waveform of the parasitic inductance in the synchronous rectification MOSFET package of a flyback power supply system in the prior art; Figure 6 The schematic diagram of the synchronous rectifier controller circuit in QR mode / DCM mode of the existing flyback power supply system; Figure 7 This is a block diagram of an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention. Figure 8 This is a detailed circuit diagram of an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention; Figure 9 This is a waveform diagram of an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention during adaptive zero-current turn-off. Figure 10 This is a flowchart of a control method for an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention.

[0018] Label Explanation: 100. Switching transistor assembly; 200. Parasitic inductance; 300. Synchronous Rectifier Controller: 310. OFF Dead Time Module: 311. Trigger Unit, 312. Inverter, 313. OFF Dead Time Detection Unit, 314. Delay Unit, 315. Trigger, 316. Delay Comparator; 320. Counting module; 330. Adjustable reference voltage module; 331. Adjustable reference voltage unit; 340. Zero-crossing shutdown comparator; 350. On-time judgment circuit; 360. Logic AND drive circuit.

[0019] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] It should be noted that the descriptions involving "first," "second," etc., in this utility model are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0022] Unlike existing QR / DCM synchronous rectifier controllers that determine whether the current crosses zero by detecting the drain-source voltage of the MOSFET, such as Figure 6 As shown, Figure 6 This paper presents the principle of a synchronous rectification controller circuit in a flyback power supply system in QR / DCM mode. The MOSFET (Metal-Oxide-Semiconductor MOSFET) is turned off by detecting whether the VD_SR voltage crosses zero. However, due to the parasitic inductance of the MOSFET package, there is an error between the voltage VD_SR detected by the synchronous rectification controller and the actual drain-source voltage of the MOSFET. This leads to premature turn-off of the secondary MOSFET during actual operation, resulting in increased system losses and reduced efficiency. To address this, this paper proposes an adaptive zero-current turn-off synchronous rectification control circuit. This circuit aims to achieve MOSFET turn-off when the current truly crosses zero, reducing power consumption and improving system efficiency, even with varying package parasitic inductance. The specific structure of this adaptive zero-current turn-off synchronous rectification control circuit is shown in the following embodiment.

[0023] Please refer to Figure 7 and Figure 8 , Figure 7 This is a block diagram of an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention. Figure 8This is a detailed circuit diagram of an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention. In this embodiment, the adaptive zero-current turn-off synchronous rectification control circuit is applied in a flyback power supply to detect whether the drain-source voltage of the switching transistor assembly in the flyback power supply has crossed zero, and turns it off when the current truly crosses zero. The circuit includes: a zero-crossing turn-off comparator 340, a conduction judgment circuit 350, and a logic AND drive circuit 360 connected in sequence. The zero-crossing turn-off comparator 340 and the conduction judgment circuit 350 are respectively connected to the drain of the switching transistor assembly 100, and the logic AND drive circuit 360 is connected to the gate of the switching transistor assembly 100. The source of the switching transistor assembly 100 is grounded, and the switching transistor assembly 100 has a parasitic inductance Ld200. Specifically, the aforementioned switching transistor assembly 100 is a metal MOSFET. The circuit also includes: an OFF dead-time module 310, a counting module 320, and an adjustable reference voltage module 330 connected sequentially. Specifically, the OFF dead-time module 310 is electrically connected to the counting module 320, and the counting module 320 is electrically connected to the adjustable reference voltage module 330. The OFF dead-time module 310 is electrically connected to the parasitic inductor Ld200, and the adjustable reference voltage module 330 is electrically connected to the inverting terminal of the zero-crossing turn-off comparator 340. The positive terminal of the zero-crossing turn-off comparator 340 is connected to a third switching transistor unit Q3. Specifically, the drain of the third switching transistor unit Q3 is connected to the drain of the switching transistor assembly 100, i.e., the drain-source voltage VD-SR; the gate is connected to a preset voltage of 5V; and the source is connected to the positive terminal of the zero-crossing turn-off comparator 340.

[0024] The OFF dead time module 310 is used to continue detecting the drain-source voltage VD-SR of the switching transistor assembly 100 after it is turned off. At this time, the switching transistor assembly 100 is equivalent to a diode. If the drain-source voltage VD-SR is lower than the reference voltage threshold, it indicates that the switching transistor assembly 100 is in a freewheeling conduction state after being turned off, and the corresponding OFF dead time duration is detected. Then, the OFF dead time is compared with the reference time threshold. If the OFF dead time is greater than the reference time threshold, a high-level signal is output when the trigger signal VDclk of the drain-source voltage VD-SR is rising after the drain-source voltage VD-SR is greater than the reference voltage threshold; a low-level signal is output when the trigger signal VDclk of the drain-source voltage VD-SR is rising after the drain-source voltage VD-SR is less than or equal to the reference voltage threshold. Specifically, if the OFF dead time is less than the delay time, VDclk goes high when VD_SR is higher than the reference voltage, at which point SROFF_DLY=1 and Q_dead=1; if the OFF dead time is less than the delay time, VDclk goes high when VD_SR is higher than the reference voltage, at which point SR_OFF_DLY=0 and Q_dead=0, where the reference voltage is the reference voltage threshold.

[0025] The counting module 320 is electrically connected to the OFF dead-time module 310. It detects the output level signal of the OFF dead-time module 310 when the trigger delay signal VDclk-dly of the drain-source voltage VD-SR is at its rising edge. If the output level signal of the OFF dead-time module 310 is low, the output result is decremented; if the output level signal of the OFF dead-time module 310 is high, the output result is incremented. The output result of the counting module 320 is decremented or incremented by one, or other equivalent data. Specifically, the counting module 320 is an Up-Down counter.

[0026] The adjustable reference voltage module 330 is electrically connected to the counting module 320 and is used to adjust the bias current based on the output of the counting module 320, thereby gradually adjusting the reference voltage threshold. This reference voltage threshold is the reference voltage of the zero-crossing turn-off comparator 340. Specifically, the output Q<3:0> of the Up-Down counter is used to adjust the bias current in the adjustable reference voltage module 330. The larger the value of Q<3:0>, the larger the bias current and the higher the corresponding reference voltage; conversely, the smaller the value of Q<3:0>, the smaller the bias current and the lower the corresponding reference voltage.

[0027] It is worth noting that the zero-crossing turn-off comparator 340, the conduction judgment circuit 350, the logic and drive circuit 360, the OFF dead time module 310, the counting module 320, and the adjustable reference voltage module 330 constitute the synchronous rectification controller 300.

[0028] In one specific embodiment, the OFF dead time module 310 includes a trigger unit 311, an OFF dead time detection unit 313, a delay unit 314, and a trigger 315. The trigger unit 311 is connected to the trigger 315, and the trigger unit 311 is used to generate a trigger signal VDclk. The OFF dead time detection unit 313 is electrically connected to the delay unit 314, and the OFF dead time detection unit 313 is used to detect the duration of the OFF dead time. The delay unit 314 is used to generate a reference time threshold. The trigger signal VDclk consists of high and low levels. The OFF dead time detection unit 313 can be implemented using a timer. The delay unit 314 can be implemented using a delay device. The trigger 315 has a trigger terminal, a data terminal, and an output terminal. The trigger terminal is connected to the output terminal of the trigger unit 311, the data terminal is connected to the output terminal of the delay unit 314, and the output terminal is connected to the counting module 320.

[0029] Specifically, the trigger unit 311 includes a first switching transistor unit Q1, a second switching transistor unit Q2, and an inverter 312. The drain of the first switching transistor unit Q1 is connected to the parasitic inductor Ld200, the source of the first switching transistor unit Q1 is connected to the gate of the second switching transistor unit Q2, the gate of the first switching transistor unit Q1 is connected to a preset voltage of 5V, the drain of the second switching transistor unit Q2 is connected to a reference voltage, and the source of the second switching transistor unit Q2 is grounded. The input terminal of the inverter 312 is connected to the drain of the second switching transistor unit Q2, and the output terminal of the inverter 312 is connected to the trigger terminal of the trigger 315. The inverter 312 outputs a trigger signal VDclk. Specifically, when the drain-source voltage VD-SR is high, the first switching transistor unit Q1 outputs a high level, controlling the second switching transistor unit Q2 to turn on, with its drain and source connected to ground. At this time, the input of the inverter 312 is low and the output is high. When the drain-source voltage VD-SR is low, the first switching transistor unit Q1 outputs a low level, controlling the second switching transistor unit Q2 to turn off, with its drain and source disconnected. At this time, the input of the inverter 312 is high and the output is low.

[0030] In one specific embodiment, the delay unit 314 includes a first resistor R1 and a first capacitor C1 connected in series. The first resistor R1 is connected to the OFF dead time detection unit 313, and the first capacitor C1 is grounded. The common node connecting the first resistor R1 and the first capacitor C1 is electrically connected to the data terminal of the trigger 315. The OFF dead time detection unit 313 outputs an SROFF signal. After being delayed by the first resistor R1 and the first capacitor C1, the SROFF signal is obtained as the SROFF-DLY signal, which is then output to the data terminal of the trigger 315. Considering the reliability and accuracy of the SROFF signal, integrated operational amplifiers can be added before and after the SROFF signal passes through the delay unit 314 to amplify the signal.

[0031] Specifically, the delay time of the delay unit 314 is two or more delay units. The delay unit 314 can be one delay unit or two or more delay units. The specific delay unit can be flexibly designed according to actual requirements, and is not limited here.

[0032] Specifically, the delay unit 314 is a hysteresis comparator, a timer, or a delay chip. The purpose of the delay unit 314 is to achieve a delay effect on the SROFF signal. The delay unit 314 can also be implemented by a hysteresis comparator, a timer, a delay chip, a digital delay circuit, etc. The specific delay circuit structure can be flexibly designed according to actual requirements, and there are no restrictions here.

[0033] In one specific embodiment, the OFF dead time module 310 further includes a delay comparator 316. The input of the delay comparator 316 is connected to the output of the inverter 312, and the output of the delay comparator 316 is connected to the counting module 320 of the counting module 320. The delay comparator 316 mainly delays the trigger signal VDclk to obtain the trigger delay signal VDclk-dly.

[0034] Specifically, the adjustable reference voltage module 330 includes an adjustable reference voltage unit 331 connected in series and a grounding resistor R2. The adjustable reference voltage unit 331 is electrically connected to the counting module 320, and the grounding resistor R2 is grounded. The adjustable reference voltage unit 331 is used to adjust the bias current by adjusting the reference current or resistance. The adjustable reference voltage unit 331 can be composed of multiple resistors connected in series, parallel, or a mixed series-parallel connection. By connecting different resistor nodes, the reference current or circuit can be adjusted.

[0035] Please refer to Figure 9 , Figure 9 This is a waveform diagram of an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention during adaptive zero-current turn-off, as shown below. Figure 9 As shown in the waveform, when the synchronous rectification turns off the switching transistor assembly 100 early, the OFF dead time is greater than the delay time set by the first resistor R1 and the first capacitor C1. Therefore, the flip-flop 315 outputs a high level, i.e., Q_dead=1. The counting module 320 gradually increases the reference voltage threshold of the comparator until the OFF dead time is less than the delay time, at which point the flip-flop 315 outputs a low level, i.e., Q_dead=0. At this time, the early turn-off time of the switching transistor assembly 100 is almost zero, achieving a near-ideal zero-current turn-off. Since this adjustment process is automatically adjusted according to the OFF dead time, it can adapt to different Ld parasitic inductances Ld200.

[0036] Please refer to Figure 10 , Figure 10 This is a flowchart of a control method for an adaptive zero-current turn-off synchronous rectification control circuit according to an embodiment of the present invention. In this embodiment, the adaptive zero-current turn-off synchronous rectification control circuit includes a zero-crossing turn-off comparator 340, a conduction judgment circuit 350, and a logic AND drive circuit 360 connected sequentially. The zero-crossing turn-off comparator 340 and the conduction judgment circuit 350 are respectively connected to the drain of the switching transistor assembly 100, and the logic AND drive circuit 360 is connected to the gate of the switching transistor assembly 100. The circuit also includes an OFF dead-time module 310, a counting module 320, and an adjustable reference voltage module 330. The method includes the following steps: S110. After the switching transistor assembly 100 is turned off, the drain-source voltage VD-SR of the switching transistor assembly 100 is continuously detected. If the drain-source voltage VD-SR is lower than the reference voltage threshold, it indicates that the switching transistor assembly 100 is in the freewheeling conduction state after being turned off, and the duration of the corresponding OFF dead time is detected. S120. Compare the OFF dead time with the reference time threshold. If the OFF dead time is greater than the reference time threshold, then when the drain-source voltage VD-SR is greater than the reference voltage threshold and the trigger signal VDclk of the drain-source voltage VD-SR is at the rising edge, output a high-level signal; when the drain-source voltage VD-SR is less than or equal to the reference voltage threshold and the trigger signal VDclk of the drain-source voltage VD-SR is at the rising edge, output a low-level signal. S130. When the trigger delay signal VDclk-dly of the drain-source voltage VD-SR is rising, detect the output level signal of the OFF dead time module 310; if the output level signal of the OFF dead time module 310 is low, decrement the output result; if the output level signal of the OFF dead time module 310 is high, increment the output result. S140. Adjust the bias current according to the output of the counting module 320, and then gradually adjust the reference voltage threshold to adapt to the switching transistor assembly 100 turning off when the current crosses zero.

[0037] In summary, this solution compares the OFF dead time after synchronous rectification turn-off with the reference time, and then adjusts the turn-off threshold voltage through the counting module 320. This allows the turn-off threshold voltage to be adjusted to an ideal value close to zero current turn-off under different package parasitic inductances Ld200, thus solving the problem of premature turn-off of the switching transistor assembly 100 and improving system efficiency.

[0038] In the various embodiments of this application, the functional modules can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. It should be noted that, for the foregoing method embodiments, for the sake of simplicity, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0039] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0040] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. All equivalent structural transformations made under the inventive concept of the present utility model using the contents of the present utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present utility model.

Claims

1. An adaptive zero-current turn-off synchronous rectification control circuit, comprising: The zero-crossing turn-off comparator, the on-time judgment circuit, and the logic and drive circuit are connected in sequence. The zero-crossing turn-off comparator and the on-time judgment circuit are respectively used to connect to the drain of the switching transistor assembly, and the logic and drive circuit is used to connect to the gate of the switching transistor assembly. The feature is that it further includes: an OFF dead-time module, a counting module, and an adjustable reference voltage module connected in sequence. The OFF dead-time module is electrically connected to a parasitic inductor, and the adjustable reference voltage module is electrically connected to the inverting terminal of the zero-crossing turn-off comparator. The OFF dead time module is used to continue detecting the drain-source voltage of the switching transistor component after it is turned off. If the drain-source voltage is lower than the reference voltage threshold, it indicates that the switching transistor component is in the freewheeling conduction state after being turned off. The module also detects the duration of the corresponding OFF dead time and compares it with the reference time threshold. If the OFF dead time is greater than the reference time threshold, a high-level signal is output when the drain-source voltage trigger signal is a rising edge after the drain-source voltage is greater than the reference voltage threshold; a low-level signal is output when the drain-source voltage trigger signal is a rising edge after the drain-source voltage is less than or equal to the reference voltage threshold. The counting module is electrically connected to the OFF dead time module and is used to detect the output level signal of the OFF dead time module when the trigger delay signal of the drain-source voltage is a rising edge; if the output level signal of the OFF dead time module is low, the output result is decremented; if the output level signal of the OFF dead time module is high, the output result is incremented. The adjustable reference voltage module is electrically connected to the counting module and is used to adjust the bias current according to the output result of the counting module, thereby gradually adjusting the reference voltage threshold. The adjustable reference voltage module includes an adjustable reference voltage unit, which is used to adjust the reference current or resistance to adjust the bias current.

2. The adaptive zero-current- turn-off synchronous rectification control circuit according to claim 1, wherein, The OFF dead time module includes a trigger unit, an OFF dead time detection unit, a delay unit, and a trigger. The trigger unit is connected to the trigger and is used to generate a trigger signal. The OFF dead time detection unit is electrically connected to the delay unit and is used to detect the duration of the OFF dead time. The delay unit is used to generate a reference time threshold.

3. The adaptive zero-current- turn-off synchronous rectification control circuit according to claim 2, wherein, The triggering unit includes a first switching transistor unit, a second switching transistor unit, and an inverter. The drain of the first switching transistor unit is connected to a parasitic inductor, the source of the first switching transistor unit is connected to the gate of the second switching transistor unit, the gate of the first switching transistor unit is connected to a preset voltage, the drain of the second switching transistor unit is connected to a reference voltage, and the source of the second switching transistor unit is grounded. The input terminal of the inverter is connected to the drain of the second switching transistor unit, and the output terminal of the inverter is connected to the trigger terminal of the trigger.

4. The adaptive zero-current turn-off synchronous rectification control circuit as described in claim 2, characterized in that, The delay unit includes a first resistor and a first capacitor connected in series. The first resistor is connected to the OFF dead time detection unit, the first capacitor is grounded, and the common node connecting the first resistor and the first capacitor is electrically connected to the data terminal of the trigger.

5. The adaptive zero-current- turn-off synchronous rectification control circuit according to claim 2, wherein, The delay time of the delay unit is two or more delay units.

6. The adaptive zero-current- turn-off synchronous rectification control circuit according to claim 2, wherein, The delay unit is a hysteresis comparator, a timer, or a delay chip.

7. The adaptive zero-current- turn-off synchronous rectification control circuit according to claim 2, wherein, The OFF dead time module also includes a delay comparator, the input of which is connected to the output of an inverter, and the output of which is connected to the counting module of the counting module.

8. The adaptive zero-current- turn-off synchronous rectification control circuit of claim 1, wherein, The adjustable reference voltage module includes a grounding resistor connected in series with the adjustable reference voltage unit. The adjustable reference voltage unit is electrically connected to the counting module, and the grounding resistor is grounded.

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