Shift register, gate driving circuit and display device

Abstract

A shift register, a gate driving circuit and a display device. The shift register comprises: a first input circuit, which writes a second working voltage provided by a second power supply terminal to a first node in response to control of a voltage at a third node; a second input circuit, which writes a signal provided by a light emitting signal input terminal to a second node in response to control of a signal at a first clock signal terminal; a light emitting driving output circuit, which writes a first working voltage provided by a first power supply terminal to a light emitting driving signal output terminal in response to control of a voltage at the first node, and writes the second working voltage to the light emitting driving signal output terminal in response to control of a voltage at a fourth node; a first voltage control circuit, which writes the first working voltage to the first node and the third node in response to control of a voltage at the second node; a second voltage control circuit, which controls the voltage at the third node; and an isolation circuit, which isolates the potentials of the second node and the fourth node in response to control of the second working voltage.

Description

Technical Field

[0001] This disclosure pertains to the field of display technology, specifically relating to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] OLED (Organic Light-Emitting Diode) displays have attracted widespread attention due to their advantages such as self-illumination, low power consumption, thinness, flexibility, vibrant colors, high contrast, and fast response speed. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a shift register, including: a first input circuit connected to a second power supply terminal, a third node and a first node, configured to write a second operating voltage provided by the second power supply terminal to the first node in response to voltage control at the third node;

[0004] The second input circuit is connected to the light-emitting signal input terminal, the first clock signal terminal, and the second node, and is configured to write the signal provided by the light-emitting signal input terminal to the second node in response to the control of the first clock signal terminal signal.

[0005] A light-emitting drive output circuit is connected to a first power supply terminal, a second power supply terminal, a light-emitting drive signal output terminal, a first node, and a fourth node. It is configured to write a first operating voltage provided by the first power supply terminal to the light-emitting drive signal output terminal in response to the control of the voltage at the first node, and to write a second operating voltage provided by the second power supply terminal to the light-emitting drive signal output terminal in response to the control of the voltage at the fourth node.

[0006] A first voltage control circuit is connected to the first power supply terminal, the first node, the second node, and the third node, and is configured to write the first operating voltage provided by the first power supply terminal to the first node and the third node in response to the control of the voltage at the second node.

[0007] A second voltage control circuit is connected to the third node and configured to control the voltage of the third node;

[0008] An isolation circuit, connected to the second power supply terminal, the second node, and the fourth node, is configured to isolate the potentials of the second node and the fourth node in response to control of the second operating voltage provided by the second power supply terminal.

[0009] In some embodiments, the second voltage control circuit includes a first capacitor.

[0010] The first terminal of the first capacitor is connected to the third node, and the second terminal of the first capacitor is connected to the first clock signal terminal.

[0011] In some embodiments, the second voltage control circuit includes a first capacitor, an eighth transistor, and a ninth transistor.

[0012] The first terminal of the first capacitor is connected to the third node, and the second terminal of the first capacitor, the second electrode of the eighth transistor, the second electrode of the ninth transistor, and the fifth node are connected.

[0013] The control electrode of the eighth transistor is connected to the second clock signal terminal, and the first electrode of the eighth transistor is connected to the first power supply terminal;

[0014] The control electrode of the ninth transistor is connected to the first clock signal terminal, and the first electrode of the ninth transistor is connected to the second power supply terminal.

[0015] In some embodiments, the second voltage control circuit includes a first capacitor, an eighth transistor, and a ninth transistor.

[0016] The first terminal of the first capacitor is connected to the third node, and the second terminal of the first capacitor, the second electrode of the eighth transistor, the second electrode of the ninth transistor, and the fifth node are connected.

[0017] The control electrode of the eighth transistor is connected to the third clock signal terminal, and the first electrode of the eighth transistor is connected to the first power supply terminal.

[0018] The control electrode of the ninth transistor is connected to the fourth clock signal terminal, and the first electrode of the ninth transistor is connected to the third power supply terminal.

[0019] In some embodiments, the third operating voltage provided by the third power supply terminal is lower than the second operating voltage provided by the second power supply terminal;

[0020] The second operating voltage provided by the second power supply terminal is lower than the first operating voltage provided by the first power supply terminal.

[0021] In some embodiments, the high level of the third clock signal provided by the third clock signal terminal is the first operating voltage, and the low level of the third clock signal is the third operating voltage;

[0022] The high level of the fourth clock signal provided by the fourth clock signal terminal is the first operating voltage, and the low level of the fourth clock signal is the third operating voltage.

[0023] In some embodiments, the eighth transistor and the ninth transistor are both P-type low-temperature polycrystalline silicon transistors;

[0024] The high level of the third clock signal corresponds to the low level of the fourth clock signal, and the low level of the third clock signal corresponds to the high level of the fourth clock signal.

[0025] In some embodiments, the high level of the first clock signal provided by the first clock signal terminal is the first operating voltage, and the low level of the first clock signal is the second operating voltage;

[0026] The high level of the second clock signal provided by the second clock signal terminal is the first operating voltage, and the low level of the second clock signal is the second operating voltage.

[0027] In some embodiments, the eighth transistor and the ninth transistor are both P-type low-temperature polycrystalline silicon transistors;

[0028] The high level of the first clock signal corresponds to the low level of the second clock signal, and the low level of the first clock signal corresponds to the high level of the second clock signal.

[0029] In some embodiments, the isolation circuit includes a seventh transistor.

[0030] The control electrode of the seventh transistor is connected to the second power supply terminal, the first electrode of the seventh transistor is connected to the second node, and the second electrode of the seventh transistor is connected to the fourth node.

[0031] In some embodiments, the isolation circuit includes a seventh transistor and an eleventh transistor.

[0032] The control terminals of the seventh transistor and the eleventh transistor are connected to the second power supply terminal, the first terminal of the seventh transistor is connected to the second node, and the second terminal of the seventh transistor is connected to the first terminal of the eleventh transistor.

[0033] The second terminal of the eleventh transistor is connected to the fourth node.

[0034] In some embodiments, a leakage protection circuit is also included, which is connected to the third power supply terminal, the light-emitting drive signal output terminal and the leakage protection node, and is configured to write the third operating voltage provided by the third power supply terminal to the leakage protection node in response to the control of the voltage at the light-emitting drive signal output terminal.

[0035] The leakage protection node is located between the second node and the fourth node.

[0036] In some embodiments, the leakage protection circuit includes a tenth transistor.

[0037] The control electrode of the tenth transistor is connected to the light-emitting drive signal output terminal, and the first electrode of the tenth transistor is connected to the third power supply terminal.

[0038] The second terminal of the seventh transistor, the first terminal of the eleventh transistor, and the second terminal of the tenth transistor are connected to the leakage protection node.

[0039] In some embodiments, the seventh crystal, the eleventh transistor, and the tenth transistor are all P-type low-temperature polycrystalline silicon transistors.

[0040] In some embodiments, the first input circuit includes a third transistor; the second input circuit includes a first transistor; the light-emitting drive output circuit includes a fourth transistor, a fifth transistor, a second capacitor, and a third capacitor; and the first voltage control circuit includes a second transistor and a sixth transistor.

[0041] The control electrode of the third transistor is connected to the third node, the first electrode of the third transistor is connected to the second power supply terminal, and the second electrode of the third transistor is connected to the first node;

[0042] The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the light emission signal input terminal, and the second electrode of the first transistor is connected to the second node.

[0043] The control electrode of the fourth transistor and the first terminal of the second capacitor are connected to the first node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor, the second terminal of the second capacitor, the first electrode of the fifth transistor and the second terminal of the third capacitor are connected to the light-emitting drive signal output terminal.

[0044] The control electrode of the fifth transistor and the first terminal of the third capacitor are connected to the fourth node, and the second electrode of the fifth transistor is connected to the second power supply terminal.

[0045] The control electrode of the second transistor and the control electrode of the sixth transistor are connected to the second node, the first electrode of the second transistor is connected to the first node, the first electrode of the sixth transistor is connected to the third node, and the second electrodes of the second transistor and the second electrodes of the sixth transistor are connected to the first power supply terminal.

[0046] In some embodiments, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all P-type low-temperature polycrystalline silicon transistors.

[0047] Secondly, embodiments of this disclosure also provide a gate driving circuit, including: a plurality of cascaded shift registers, wherein the shift registers are the shift registers described in the above embodiments;

[0048] The light emission signal input terminal of the shift register located in the first stage is connected to the light emission start signal line, and the light emission signal input terminal of the shift registers in other stages besides the first stage is connected to the light emission drive signal output terminal of the shift register in the previous stage.

[0049] The output terminal of the light-emitting drive signal of each shift register is connected to the corresponding light-emitting control signal line.

[0050] Thirdly, embodiments of this disclosure also provide a display device including the gate driving circuit described above.

[0051] The shift register provided in this embodiment can control the voltage of the first and third nodes by setting a first voltage control circuit; it can control the voltage of the third node by setting a second voltage control circuit; and it can control the voltage of the fourth node by setting an isolation circuit. In this embodiment, when the light-emitting driving signal (i.e., EM signal) output from the light-emitting driving signal output terminal of the shift register switches from high level to low level, its falling edge can achieve stepless operation. Therefore, when the OLED display panel using this shift register is displaying, the light-emitting driving signal can stably drive the OLED display panel to display, thereby ensuring the stable display of the OLED display panel.

[0052] The gate driving circuit provided in this embodiment, by employing the shift register in the above embodiment, can stably drive the display panel to display when the display panel using the gate driving circuit is in use, and ensures stable display of the display panel.

[0053] The display device provided in this embodiment of the present disclosure, by employing the above-described gate driving circuit, can ensure stable display during low-frequency display, thereby improving the display effect of the display device during display. Attached Figure Description

[0054] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0055] Figure 1A This is a circuit diagram of a shift register according to an embodiment of the present disclosure.

[0056] Figure 1B for Figure 1ATiming diagram of the shift register.

[0057] Figure 2A This is a circuit diagram of another shift register in an embodiment of this disclosure.

[0058] Figure 2B for Figure 2A Timing diagram of the shift register.

[0059] Figure 3A This is a circuit diagram of another shift register in an embodiment of this disclosure.

[0060] Figure 3B for Figure 3A Timing diagram of the shift register.

[0061] Figure 4A This is a circuit diagram of yet another shift register in an embodiment of this disclosure.

[0062] Figure 4B for Figure 4A Simulated waveforms of the fourth node potential change when the threshold voltage of all transistors in the shift register circuit drifts.

[0063] Figure 4C for Figure 4A The simulated waveform of the light-emitting drive signal output at the output terminal of the light-emitting drive signal when the threshold voltage of all transistors in the shift register circuit drifts. Detailed Implementation

[0064] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the following describes in further detail a shift register, gate driving circuit, and display device provided by the embodiments of this disclosure in conjunction with the accompanying drawings and specific implementation methods.

[0065] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0066] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas, but are not intended to be limiting.

[0067] In related technologies, when an OLED display panel is displayed at a low frequency (referring to a display with a lower refresh rate), the light-emitting gate driving signal (i.e., the EM signal) output by its light-emitting gate driving circuit (EM GOA circuit) has a step problem in its falling edge when it switches from a high level to a low level. This causes instability when the light-emitting gate driving signal drives the display panel, resulting in unstable display of the display panel.

[0068] To address the aforementioned problems in the related art, in a first aspect, embodiments of this disclosure provide a shift register, such as... Figure 1A As shown, it includes: a first input circuit 1, connected to a second power supply terminal VGL, a third node N3, and a first node N1, configured to write a second operating voltage provided by the second power supply terminal VGL to the first node N1 in response to voltage control at the third node N3; a second input circuit 2, connected to a light-emitting signal input terminal STV, a first clock signal terminal CK, and a second node N2, configured to write a signal provided by the light-emitting signal input terminal STV to the second node N2 in response to the signal control at the first clock signal terminal CK; and a light-emitting drive output circuit 3, connected to a first power supply terminal VGH, a second power supply terminal VGL, a light-emitting drive signal output terminal OUT, a first node N1, and a fourth node N4, configured to write a first operating voltage provided by the first power supply terminal VGH to the light-emitting drive output circuit in response to voltage control at the first node N1. The system includes a drive signal output terminal OUT, and a second operating voltage provided by the second power supply terminal VGL written to the light-emitting drive signal output terminal OUT in response to the voltage control at the fourth node N4; a first voltage control circuit 4, connected to the first power supply terminal VGH, the first node N1, the second node N2 and the third node N3, configured to write the first operating voltage provided by the first power supply terminal VGH to the first node N1 and the third node N3 in response to the voltage control at the second node N2; a second voltage control circuit 5, connected to the third node N3, configured to control the voltage of the third node N3; and an isolation circuit 6, connected to the second power supply terminal VGL, the second node N2 and the fourth node N4, configured to isolate the potentials of the second node N2 and the fourth node N4 in response to the control of the second operating voltage provided by the second power supply terminal VGL.

[0069] In this embodiment, by setting the first voltage control circuit 4, the voltages of the first node N1 and the third node N3 can be controlled; by setting the second voltage control circuit 5, the voltage of the third node N3 can be controlled; and by setting the isolation circuit 6, the voltage of the fourth node N4 can be controlled. In this embodiment, the shift register, through the stable control of the voltages of the first node N1, the third node N3, and the fourth node N4 by the first voltage control circuit 4, the second voltage control circuit 5, and the isolation circuit 6, can ensure that when the light-emitting driving signal (i.e., the EM signal) output from the light-emitting driving signal output terminal OUT switches from a high level to a low level, its falling edge can achieve stepless operation. Therefore, when the OLED display panel using this shift register is displaying at low frequencies, the light-emitting driving signal can stably drive the OLED display panel to display, thereby ensuring the stable display of the OLED display panel. For example, when the light-emitting driving signal (i.e., the EM signal) output from the light-emitting driving signal output terminal OUT switches from a high level to a low level, the voltage of the fourth node N4 is lower than VGL, which makes the fifth transistor stably output VGL, so that the output terminal OUT directly outputs VGL, and its output terminal OUT can achieve stepless falling edge; thus, when the OLED display panel using this shift register is displaying at low frequency, the light-emitting driving signal can stably drive the OLED display panel to display, thereby ensuring the stable voltage of the fourth node N4 of the OLED display panel.

[0070] In some embodiments, such as Figure 1A As shown, the second voltage control circuit 5 includes a first capacitor C1, the first end of the first capacitor C1 is connected to the third node N3, and the second end of the first capacitor C1 is connected to the first clock signal terminal CK.

[0071] In some embodiments, such as Figure 1A As shown, the isolation circuit 6 includes a seventh transistor T7. The control terminal of the seventh transistor T7 is connected to the second power supply terminal VGL, the first terminal of the seventh transistor T7 is connected to the second node N2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4.

[0072] In some embodiments, the first input circuit 1 includes a third transistor T3; the second input circuit 2 includes a first transistor T1; the light-emitting drive output circuit 3 includes a fourth transistor T4, a fifth transistor T5, a second capacitor C2, and a third capacitor C3; and the first voltage control circuit 4 includes a second transistor T2 and a sixth transistor T6.

[0073] The control electrode of the third transistor T3 is connected to the third node N3, the first electrode of the third transistor T3 is connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is connected to the first node N1; the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is connected to the light emission signal input terminal STV, and the second electrode of the first transistor T1 is connected to the second node N2; the control electrode of the fourth transistor T4 and the first terminal of the second capacitor C2 are connected to the first node N1, the first electrode of the fourth transistor T4 is connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 and the second capacitor C2 are connected to the first power supply terminal VGH. The second terminal of the transistor, the first terminal of the fifth transistor T5, and the second terminal of the third capacitor C3 are connected to the light-emitting drive signal output terminal OUT; the control terminal of the fifth transistor T5 and the first terminal of the third capacitor C3 are connected to the fourth node N4, and the second terminal of the fifth transistor T5 is connected to the second power supply terminal VGL; the control terminals of the second transistor T2 and the sixth transistor T6 are connected to the second node N2, the first terminal of the second transistor T2 is connected to the first node N1, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminals of the second transistor T2 and the sixth transistor T6 are connected to the first power supply terminal VGH.

[0074] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type low-temperature polycrystalline silicon transistors.

[0075] In some embodiments, the second operating voltage provided by the second power supply terminal VGL is lower than the first operating voltage provided by the first power supply terminal VGH. For example, the second operating voltage is a low-level voltage (such as VGL), and the first operating voltage is a high-level voltage (such as VGH).

[0076] In some embodiments, such as Figure 1B As shown, Figure 1A The operation of the shift register includes four stages: Stage 1 S1: The light emission signal input terminal STV receives a high-level signal, the first clock signal terminal CK receives a low-level signal, the first transistor T1 is turned on, and the second node N2 is at a high level (e.g., VGH); the second transistor T2 and the sixth transistor T6 are turned off; the potential of the third node N3 is pulled low by the low-level signal of the first clock signal terminal CK, that is, the third node N3 is at a low level (e.g., VGL), the third transistor T3 is turned on, and the first node N1 is the second operating voltage (e.g., VGL) of the second power supply terminal VGL; the voltage of the first node N1 turns on the fourth transistor T4, and the light emission drive signal output terminal OUT outputs the first operating voltage (e.g., VGH) of the first power supply terminal VGH; the seventh transistor T7 is turned on, the fourth node N4 is at a high level (e.g., VGH); the fifth transistor is turned off.

[0077] Phase 2 S2: A high-level signal is input to the light-emitting signal input terminal STV, a high-level signal is input to the first clock signal terminal CK, the first transistor T1 is turned off, and the second node N2 remains at a high level (e.g., VGH); the second transistor T2 and the sixth transistor T6 remain off; the potential of the third node N3 is pulled high by the high-level signal of the first clock signal terminal CK, that is, the third node N3 becomes high level (e.g., VGH), the third transistor T3 is turned off, and the first node N1 maintains the second operating voltage (e.g., VGL) of the second power supply terminal VGL; the voltage of the first node N1 keeps the fourth transistor T4 on, and the light-emitting drive signal output terminal OUT outputs the first operating voltage (e.g., VGH) of the first power supply terminal VGH; the seventh transistor T7 is turned on, the fourth node N4 remains at a high level (e.g., VGH); the fifth transistor is turned off.

[0078] In the third stage S3: a low-level signal is input to the light-emitting signal input terminal STV, a low-level signal is input to the first clock signal terminal CK, the first transistor T1 is turned on, and the second node N2 becomes low (e.g., VGL); the second transistor T2 and the sixth transistor T6 are turned on; the potential of the third node N3 becomes the first operating voltage of the first power supply terminal VGH (e.g., VGH), the third transistor T3 is turned off, the potential of the first node N1 becomes the first operating voltage of the first power supply terminal VGH (e.g., VGH); the voltage of the first node N1 turns off the fourth transistor T4; the seventh transistor T7 is turned on, the potential of the fourth node N4 is pulled low to a low level by the potential of the second node N2 (e.g., VGL), the fifth transistor is turned on, and the light-emitting drive signal output terminal OUT outputs the light-emitting drive signal as the second operating voltage of the second power supply terminal VGL (e.g., VGL).

[0079] Phase 4 (S4): The light-emitting signal input terminal STV receives a low-level signal, the first clock signal terminal CK receives a high-level signal, the first transistor T1 is turned off, and the second node N2 remains low (e.g., VGL); the second transistor T2 and the sixth transistor T6 remain on; the potential of the third node N3 maintains the first operating voltage (e.g., VGH) of the first power supply terminal VGH, the third transistor T3 remains off, and the potential of the first node N1 maintains the first operating voltage (e.g., VGH) of the first power supply terminal VGH; the voltage of the first node N1 turns off the fourth transistor T4; the seventh transistor T7 remains on, and the potential of the fourth node N4 is pulled down to a low level (e.g., VGL) by the second operating voltage (e.g., VGL) of the second power supply terminal VGL output by the light-emitting drive signal output terminal OUT; the fifth transistor turns on, and the light-emitting drive signal output by the light-emitting drive signal output terminal OUT is the second operating voltage (e.g., VGL) of the second power supply terminal VGL.

[0080] In the third stage S3 and the fourth stage S4, when the gate-source voltage Vgs of the seventh transistor T7 is less than the threshold voltage Vth of the seventh transistor T7, the seventh transistor T7 is turned off, thereby isolating the potentials of the second node N2 and the fourth node N4. This prevents the potential of the second node N2 from being pulled up by the input signal of the light-emitting signal input terminal STV, which in turn pulls up the potential of the fourth node N4. Ultimately, this prevents the fifth transistor T5 from being unable to turn on due to the potential of the fourth node N4 being pulled up. Consequently, it prevents the second working voltage (such as VGL) of the second power supply terminal VGL from being unable to be stably output by the light-emitting drive signal output terminal OUT due to the inability of the fifth transistor T5 to turn on. In other words, it ensures that the fifth transistor T5 is turned on normally, thereby ensuring that the second working voltage (such as VGL) of the second power supply terminal VGL is stably output by the light-emitting drive signal output terminal OUT.

[0081] In some embodiments, such as Figure 2A As shown, unlike the shift register in the above embodiment, the second voltage control circuit 5 includes a first capacitor C1, an eighth transistor T8, and a ninth transistor T9. The first terminal of the first capacitor C1 is connected to the third node N3, and the second terminal of the first capacitor C1, the second terminal of the eighth transistor T8, the second terminal of the ninth transistor T9, and the fifth node N5 are connected. The control terminal of the eighth transistor T8 is connected to the second clock signal terminal CB, and the first terminal of the eighth transistor T8 is connected to the first power supply terminal VGH. The control terminal of the ninth transistor T9 is connected to the first clock signal terminal CK, and the first terminal of the ninth transistor T9 is connected to the second power supply terminal VGL.

[0082] In some embodiments, such as Figure 2B As shown, the eighth transistor T8 and the ninth transistor T9 are both P-type low-temperature polysilicon transistors; the high level of the first clock signal corresponds to the low level of the second clock signal, and the low level of the first clock signal corresponds to the high level of the second clock signal.

[0083] In some embodiments, the eighth transistor T8 is a P-type low-temperature polysilicon transistor, and the ninth transistor T9 is an N-type low-temperature polysilicon transistor; the high level of the first clock signal corresponds to the high level of the second clock signal, and the low level of the first clock signal corresponds to the low level of the second clock signal.

[0084] In some embodiments, such as Figure 2B As shown, the high level of the first clock signal provided by the first clock signal terminal CK is the first operating voltage (e.g., VGH), and the low level of the first clock signal is the second operating voltage (e.g., VGL); the high level of the second clock signal provided by the second clock signal terminal CB is the first operating voltage (e.g., VGH), and the low level of the second clock signal is the second operating voltage (e.g., VGL).

[0085] In this embodiment, as Figure 2BAs shown, Figure 2A The operating state of the intermediate shift register can be compared with Figure 1A The shift registers in the middle have the same operating states, all including four stages, and in each stage, Figure 2A Zhongyu Figure 1A The signals at the same signal terminals are the same. Figure 2A and Figure 1A Unlike the shift register, the voltage control of the third node N3 in each stage is as follows: In the first stage S1: When the first clock signal terminal CK inputs a low-level signal, the ninth transistor T9 is turned on, and the second operating voltage provided by the second power supply terminal VGL is written to the fifth node N5. The potential of the third node N3 is pulled low by the potential of the fifth node N5, that is, the third node N3 is at a low level (such as VGL); When the second clock signal terminal CB inputs a high-level signal, the eighth transistor T8 is turned off.

[0086] In the second stage S2: a high-level signal is input to the first clock signal terminal CK, and the ninth transistor T9 is turned off; a low-level signal is input to the second clock signal terminal CB, and the eighth transistor T8 is turned on; the first operating voltage provided by the first power supply terminal VGH is written to the fifth node N5, and the potential of the third node N3 is pulled high by the potential of the fifth node N5.

[0087] In the third stage S3 and the fourth stage S4: the light-emitting signal input terminal STV receives a low-level signal, the first clock signal terminal CK receives a low-level signal, the first transistor T1 is turned on, the second node N2 becomes low (e.g., VGL); the second transistor T2 and the sixth transistor T6 are turned on; the potentials of the third node N3 and the first node N1 are both changed to the first operating voltage of the first power supply terminal VGH (e.g., VGH).

[0088] In this embodiment, as Figure 2A As shown, by adding the eighth transistor T8 and the eighth transistor T9, the voltage regulation function of the third node N3 can be optimized. Meanwhile, since the first operating voltage of the first power supply terminal VGH and the second operating voltage of the second power supply terminal VGL are DC signals, their impact on the power consumption of the first capacitor C1 is relatively small. Therefore, compared to... Figure 1A The second voltage control circuit 5 in the circuit can reduce the frequent charging and discharging of the first clock signal (AC signal) of the first clock signal terminal CK to the first capacitor C1, thereby reducing the power consumption of the first clock signal terminal CK and the first capacitor C1.

[0089] In some embodiments, such as Figure 3AAs shown, unlike the shift register in the above embodiment, the second voltage control circuit 5 includes a first capacitor C1, an eighth transistor T8, and a ninth transistor T9. The first terminal of the first capacitor C1 is connected to the third node N3, and the second terminal of the first capacitor C1, the second terminal of the eighth transistor T8, the second terminal of the ninth transistor T9, and the fifth node N5 are connected. The control terminal of the eighth transistor T8 is connected to the third clock signal terminal CB2, and the first terminal of the eighth transistor T8 is connected to the first power supply terminal VGH. The control terminal of the ninth transistor T9 is connected to the fourth clock signal terminal CK2, and the first terminal of the ninth transistor T9 is connected to the third power supply terminal VGL2.

[0090] In some embodiments, such as Figure 3A As shown, the third operating voltage provided by the third power supply terminal VGL2 is lower than the second operating voltage provided by the second power supply terminal VGL; the second operating voltage provided by the second power supply terminal VGL is lower than the first operating voltage provided by the first power supply terminal VGH.

[0091] In this embodiment, the shift register, by increasing the third operating voltage provided by the third power supply terminal VGL2 and making the third operating voltage lower than the second operating voltage provided by the second power supply terminal VGL, can improve the problem of insufficient potential reset of the third node N3 after the threshold voltage drift of the ninth transistor T9 and the third transistor T3, thereby improving the problem that the first node N1 cannot be turned on in time due to insufficient potential reset of the third node N3.

[0092] In some embodiments, such as Figure 3B As shown, the eighth transistor T8 and the ninth transistor T9 are both P-type low-temperature polysilicon transistors; the high level of the third clock signal corresponds to the low level of the fourth clock signal, and the low level of the third clock signal corresponds to the high level of the fourth clock signal.

[0093] In some embodiments, the eighth transistor T8 is a P-type low-temperature polysilicon transistor, and the ninth transistor T9 is an N-type low-temperature polysilicon transistor; the high level of the third clock signal corresponds to the high level of the fourth clock signal, and the low level of the third clock signal corresponds to the low level of the fourth clock signal.

[0094] In some embodiments, such as Figure 3B As shown, the high level of the third clock signal provided by the third clock signal terminal CB2 is the first operating voltage, and the low level of the third clock signal is the third operating voltage; the high level of the fourth clock signal provided by the fourth clock signal terminal CK2 is the first operating voltage, and the low level of the fourth clock signal is the third operating voltage.

[0095] In some embodiments, such as Figure 3B As shown, Figure 3A The working state of the shift register and Figure 2AThe operating states of the intermediate shift registers are basically the same. By making the low level of the third clock signal provided by the third clock signal terminal CB2 the third operating voltage, and the low level of the fourth clock signal provided by the fourth clock signal terminal CK2 the third operating voltage, compared to... Figure 2A In this scheme, the low level of the first clock signal and the low level of the second clock signal are both based on the second operating voltage (e.g., VGL). Since the third operating voltage (e.g., VGL2) is lower than the second operating voltage (e.g., VGL), therefore... Figure 3B The scheme of using the third clock signal terminal CB2 and the fourth clock signal terminal CK2 to control the control electrodes of the eighth transistor T8 and the ninth transistor T9 in the second voltage control circuit 5 respectively can ensure that after the threshold voltage of all transistors in the shift register drifts (e.g., -2V), the first node N1 to the fifth node N5 can maintain a stable potential, and the light-emitting drive signal output terminal OUT can maintain a stable output light-emitting drive signal with no step falling edge.

[0096] In some embodiments, such as Figure 4A As shown, unlike the shift register in the above embodiment, the isolation circuit 6 includes a seventh transistor T7 and an eleventh transistor T11. The control terminals of the seventh transistor T7 and the eleventh transistor T11 are connected to the second power supply terminal VGL. The first terminal of the seventh transistor T7 is connected to the second node N2, and the second terminal of the seventh transistor T7 is connected to the first terminal of the eleventh transistor T11. The second terminal of the eleventh transistor T11 is connected to the fourth node N4.

[0097] In some embodiments, such as Figure 4A As shown, the shift register also includes a leakage protection circuit 7, which is connected to the third power supply terminal VGL2, the light-emitting drive signal output terminal OUT, and the leakage protection node OFF. It is configured to write the third operating voltage provided by the third power supply terminal VGL2 to the leakage protection node OFF in response to the control of the voltage at the light-emitting drive signal output terminal OUT. The leakage protection node OFF is located between the second node N2 and the fourth node N4.

[0098] In some embodiments, such as Figure 4A As shown, the leakage protection circuit 7 includes a tenth transistor T10. The control electrode of the tenth transistor T10 is connected to the light-emitting drive signal output terminal OUT, and the first electrode of the tenth transistor T10 is connected to the third power supply terminal VGL2. The second electrode of the seventh transistor T7, the first electrode of the eleventh transistor T11, and the second electrode of the tenth transistor T10 are connected to the leakage protection node OFF.

[0099] In some embodiments, the seventh crystal T7, the eleventh transistor T11, and the tenth transistor T10 are all P-type low-temperature polycrystalline silicon transistors.

[0100] In this embodiment, as Figure 4A As shown, the other circuitry of the shift register is... Figure 2A The same as in, such as Figure 2B As shown, Figure 4A The working state of the shift register and Figure 2A The operation of the shift register is basically the same. The fourth node N4 is the control electrode of the fifth transistor T5. In order to ensure that the fifth transistor T5 can be turned on normally in the third stage S3 and the fourth stage S4, the fourth node N4 must be kept at a lower potential than the second node N2. However, in the low frequency (i.e., low refresh rate) display state, the second node N2 will leak current to the fourth node N4, causing the low potential of the fourth node N4 to be unsustainable. By setting the anti-leakage circuit 7, on the one hand, the potential of the fourth node N4 can be kept at the second working voltage provided by the second power supply terminal VGL; on the other hand, in the third stage S3 and the fourth stage S4, when the potential of the second node N2 is higher than the potential of the fourth node N4, the leakage current from the second node N2 to the fourth node N4 will be discharged to the lower potential third power supply terminal VGL2 through the seventh transistor T7 and the tenth transistor T10, thereby preventing the high potential of the second node N2 from leaking to the fourth node N4, thus ensuring that the fifth transistor T5 can be turned on normally, and finally ensuring that the light-emitting drive signal output terminal OUT can stably output the light-emitting drive signal. Meanwhile, when the gate-source voltage Vgs of the seventh transistor T7 is less than its threshold voltage Vth, and / or the gate-source voltage Vgs of the eleventh transistor T11 is less than its threshold voltage Vth, the seventh transistor T7 and / or the eleventh transistor T11 are turned off, which can isolate the potentials of the second node N2 and the fourth node N4, thereby preventing the potential of the second node N2 from being pulled up by the input signal of the light emission signal input terminal STV, which in turn will pull up the potential of the fourth node N4, thus preventing the fifth transistor T5 from being unable to turn on due to the potential of the fourth node N4 being pulled up.

[0101] Furthermore, when the width-to-length ratio of the channel region of the tenth transistor T10 is small, the width-to-length ratio of the channel region of the tenth transistor T10 is 0.2 to 0.8, for example, 0.4 or 0.6. This results in better leakage protection, meaning the high potential of the second node N2 is more easily discharged through the tenth transistor T10, thereby reducing the impact on the potential of the fourth node N4.

[0102] In some embodiments, such as Figure 4B As shown, Figure 4A Simulated waveforms of the potential change at the fourth node N4 when the threshold voltage drifts of all transistors in the shift register circuit are -5V, -4V, -3V, -2V, -1V, and 0V, respectively. Figure 4C As shown, Figure 4AThe simulated waveform of the light-emitting drive signal output from the OUT terminal is obtained when the threshold voltage drifts of all transistors in the shift register circuit are -5V, -4V, -3V, -2V, -1V, and 0V, respectively. Figure 4B As can be seen, when Figure 4A When the threshold voltage drifts of all transistors in the shift register circuit are -5V, -4V, -3V, -2V, -1V, and 0V respectively, the fourth node N4 can still maintain a low potential (such as below -7V), thus ensuring that the fifth transistor T5 can remain stably turned on in the third stage S3 and the fourth stage S4. Figure 4C As can be seen, when Figure 4A When the threshold voltage drift of all transistors in the shift register circuit is -5V, -4V, -3V, -2V, -1V, and 0V respectively, the falling edge of the light-emitting drive signal output terminal OUT can be stepless when it switches from high level to low level. Therefore, when the OLED display panel using this shift register is displaying at low frequency, the light-emitting drive signal can stably drive the OLED display panel to display, thereby ensuring the stable display of the OLED display panel.

[0103] The shift register provided in this embodiment can control the voltages of the first and third nodes by setting a first voltage control circuit; it can control the voltage of the third node by setting a second voltage control circuit; and it can control the voltage of the fourth node by setting an isolation circuit. The shift register in this embodiment, through the stable control of the voltages of the first, third, and fourth nodes by the first voltage control circuit, the second voltage control circuit, and the isolation circuit, can ensure that when the light-emitting driving signal (i.e., the EM signal) output from the light-emitting driving signal output terminal switches from a high level to a low level, its falling edge can achieve stepless operation. Therefore, when the OLED display panel using this shift register is displaying at low frequencies, the light-emitting driving signal can stably drive the OLED display panel to display, thereby ensuring the stable display of the OLED display panel.

[0104] Secondly, embodiments of this disclosure also provide a gate driving circuit, including: a plurality of cascaded shift registers, wherein the shift registers are shift registers as described in any of the above embodiments; the light emission signal input terminal of the shift register located in the first stage is connected to the light emission start signal line, and the light emission signal input terminals of the shift registers in other stages besides the first stage are connected to the light emission drive signal output terminals of the shift registers in the previous stage; the light emission drive signal output terminals of each shift register are connected to the corresponding light emission control signal line.

[0105] The gate driving circuit provided in this embodiment, by employing the shift register in any of the above embodiments, can stably drive the display panel to display at low frequencies and ensure stable display of the display panel.

[0106] Thirdly, embodiments of this disclosure also provide a display device, including the gate driving circuit described in the above embodiments.

[0107] By employing the gate driving circuit in the above embodiments, the display device can be ensured to display stably at low frequencies, thereby improving the display effect of the display device at low frequencies.

[0108] Fourthly, embodiments of this disclosure also provide a driving method for a display device, comprising: a gate driving circuit providing a light-emitting driving signal for the display of the display device.

[0109] The display device provided in this disclosure can be any product or component with display function, such as an OLED panel, OLED TV, OLED billboard, monitor, mobile phone, or navigator.

[0110] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, characterized in that, include: A first input circuit, connected to a second power supply terminal, a third node, and a first node, is configured to write a second operating voltage provided by the second power supply terminal to the first node in response to voltage control at the third node. The second input circuit is connected to the light-emitting signal input terminal, the first clock signal terminal, and the second node, and is configured to write the signal provided by the light-emitting signal input terminal to the second node in response to the control of the first clock signal terminal signal. A light-emitting drive output circuit is connected to a first power supply terminal, a second power supply terminal, a light-emitting drive signal output terminal, a first node, and a fourth node. It is configured to write a first operating voltage provided by the first power supply terminal to the light-emitting drive signal output terminal in response to the control of the voltage at the first node, and to write a second operating voltage provided by the second power supply terminal to the light-emitting drive signal output terminal in response to the control of the voltage at the fourth node. A first voltage control circuit is connected to the first power supply terminal, the first node, the second node, and the third node, and is configured to write the first operating voltage provided by the first power supply terminal to the first node and the third node in response to the control of the voltage at the second node. A second voltage control circuit is connected to the third node and configured to control the voltage of the third node; An isolation circuit, connected to the second power supply terminal, the second node, and the fourth node, is configured to isolate the potentials of the second node and the fourth node in response to control of the second operating voltage provided by the second power supply terminal.

2. The shift register according to claim 1, characterized in that, The second voltage control circuit includes a first capacitor. The first terminal of the first capacitor is connected to the third node, and the second terminal of the first capacitor is connected to the first clock signal terminal.

3. The shift register according to claim 1, characterized in that, The second voltage control circuit includes a first capacitor, an eighth transistor, and a ninth transistor. The first terminal of the first capacitor is connected to the third node, and the second terminal of the first capacitor, the second electrode of the eighth transistor, the second electrode of the ninth transistor, and the fifth node are connected. The control electrode of the eighth transistor is connected to the second clock signal terminal, and the first electrode of the eighth transistor is connected to the first power supply terminal; The control electrode of the ninth transistor is connected to the first clock signal terminal, and the first electrode of the ninth transistor is connected to the second power supply terminal.

4. The shift register according to claim 1, characterized in that, The second voltage control circuit includes a first capacitor, an eighth transistor, and a ninth transistor. The first terminal of the first capacitor is connected to the third node, and the second terminal of the first capacitor, the second electrode of the eighth transistor, the second electrode of the ninth transistor, and the fifth node are connected. The control electrode of the eighth transistor is connected to the third clock signal terminal, and the first electrode of the eighth transistor is connected to the first power supply terminal. The control electrode of the ninth transistor is connected to the fourth clock signal terminal, and the first electrode of the ninth transistor is connected to the third power supply terminal.

5. The shift register according to claim 4, characterized in that, The third operating voltage provided by the third power supply terminal is lower than the second operating voltage provided by the second power supply terminal. The second operating voltage provided by the second power supply terminal is lower than the first operating voltage provided by the first power supply terminal.

6. The shift register according to claim 5, characterized in that, The high level of the third clock signal provided by the third clock signal terminal is the first operating voltage, and the low level of the third clock signal is the third operating voltage; The high level of the fourth clock signal provided by the fourth clock signal terminal is the first operating voltage, and the low level of the fourth clock signal is the third operating voltage.

7. The shift register according to claim 6, characterized in that, Both the eighth transistor and the ninth transistor are P-type low-temperature polycrystalline silicon transistors. The high level of the third clock signal corresponds to the low level of the fourth clock signal, and the low level of the third clock signal corresponds to the high level of the fourth clock signal.

8. The shift register according to claim 3, characterized in that, The high level of the first clock signal provided by the first clock signal terminal is the first operating voltage, and the low level of the first clock signal is the second operating voltage; The high level of the second clock signal provided by the second clock signal terminal is the first operating voltage, and the low level of the second clock signal is the second operating voltage.

9. The shift register according to claim 8, characterized in that, Both the eighth transistor and the ninth transistor are P-type low-temperature polycrystalline silicon transistors. The high level of the first clock signal corresponds to the low level of the second clock signal, and the low level of the first clock signal corresponds to the high level of the second clock signal.

10. The shift register according to claim 1, characterized in that, The isolation circuit includes a seventh transistor. The control electrode of the seventh transistor is connected to the second power supply terminal, the first electrode of the seventh transistor is connected to the second node, and the second electrode of the seventh transistor is connected to the fourth node.

11. The shift register according to claim 1, characterized in that, The isolation circuit includes a seventh transistor and an eleventh transistor. The control terminals of the seventh transistor and the eleventh transistor are connected to the second power supply terminal, the first terminal of the seventh transistor is connected to the second node, and the second terminal of the seventh transistor is connected to the first terminal of the eleventh transistor. The second terminal of the eleventh transistor is connected to the fourth node.

12. The shift register according to claim 11, characterized in that, It also includes a leakage protection circuit, which is connected to the third power supply terminal, the light-emitting drive signal output terminal and the leakage protection node, and is configured to write the third working voltage provided by the third power supply terminal to the leakage protection node in response to the control of the voltage at the light-emitting drive signal output terminal. The leakage protection node is located between the second node and the fourth node.

13. The shift register according to claim 12, characterized in that, The leakage protection circuit includes a tenth transistor. The control electrode of the tenth transistor is connected to the light-emitting drive signal output terminal, and the first electrode of the tenth transistor is connected to the third power supply terminal. The second terminal of the seventh transistor, the first terminal of the eleventh transistor, and the second terminal of the tenth transistor are connected to the leakage protection node.

14. The shift register according to claim 13, characterized in that, The seventh crystal, the eleventh transistor, and the tenth transistor are all P-type low-temperature polycrystalline silicon transistors.

15. The shift register according to any one of claims 1-14, characterized in that, The first input circuit includes a third transistor; the second input circuit includes a first transistor; the light-emitting drive output circuit includes a fourth transistor, a fifth transistor, a second capacitor, and a third capacitor; the first voltage control circuit includes a second transistor and a sixth transistor. The control electrode of the third transistor is connected to the third node, the first electrode of the third transistor is connected to the second power supply terminal, and the second electrode of the third transistor is connected to the first node; The control electrode of the first transistor is connected to the first clock signal terminal, the first electrode of the first transistor is connected to the light emission signal input terminal, and the second electrode of the first transistor is connected to the second node. The control electrode of the fourth transistor and the first terminal of the second capacitor are connected to the first node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor, the second terminal of the second capacitor, the first electrode of the fifth transistor and the second terminal of the third capacitor are connected to the light-emitting drive signal output terminal. The control electrode of the fifth transistor and the first terminal of the third capacitor are connected to the fourth node, and the second electrode of the fifth transistor is connected to the second power supply terminal. The control electrode of the second transistor and the control electrode of the sixth transistor are connected to the second node, the first electrode of the second transistor is connected to the first node, the first electrode of the sixth transistor is connected to the third node, and the second electrodes of the second transistor and the second electrodes of the sixth transistor are connected to the first power supply terminal.

16. The shift register according to claim 15, characterized in that, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all P-type low-temperature polycrystalline silicon transistors.

17. A gate driving circuit, characterized in that, include: A series of cascaded shift registers, wherein the shift registers are the shift registers described in any one of claims 1-16 above; The light emission signal input terminal of the shift register located in the first stage is connected to the light emission start signal line, and the light emission signal input terminal of the shift registers in other stages besides the first stage is connected to the light emission drive signal output terminal of the shift register in the previous stage. The output terminal of the light-emitting drive signal of each shift register is connected to the corresponding light-emitting control signal line.

18. A display device, characterized in that, Includes the gate drive circuit as described in claim 17.

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