Power converter circuit and control circuit therefor

Abstract

The power converter circuit includes a power stage circuit and a control circuit. The power stage circuit generates an output signal at an output node in accordance with a duty cycle. The control circuit includes an error amplifier circuit, a comparison circuit, and a dynamic adjustment circuit. The error amplifier circuit outputs a compensation signal in accordance with a reference signal and a feedback signal related to the output signal. The comparison circuit compares the compensation signal with a ramp signal to generate a task signal. The dynamic adjustment circuit detects a high frequency component when the output signal changes to generate a dynamic adjustment signal corresponding to the change of the output signal. The dynamic adjustment circuit controls the error amplifier circuit with the dynamic adjustment signal to make the event of the compensation signal exceeding the ramp signal occur earlier or end earlier, thereby adjusting the duty cycle. By detecting the high frequency component when the output signal changes to generate the dynamic adjustment signal, the control circuit can make the event of the compensation signal exceeding the ramp signal occur earlier or end earlier to avoid the output signal from having undershoot or overshoot.

Description

Technical Field

[0001] This utility model relates to a control circuit, and more particularly to a control circuit for a power converter circuit. Background Technology

[0002] With the development of semiconductor technology, the responsiveness of power converter circuits to load transients has become increasingly important. Some related technologies use a reference signal and a feedback signal related to the output of the power converter circuit to generate an error signal, and compare the error signal with a ramp or sawtooth wave signal to respond to load transients. However, the response speed of these related technologies still does not meet user needs for load transients. Therefore, it is necessary to propose new circuits to solve the above problems. Utility Model Content

[0003] One embodiment of this utility model is a control circuit. The control circuit is applicable to a power converter circuit. The power converter circuit includes a power stage circuit. The power stage circuit generates an output signal at the output node of the power converter circuit based on a duty cycle. The control circuit includes an error amplifier circuit, a comparator circuit, and a dynamic adjustment circuit. The error amplifier circuit is coupled to the output node and outputs a compensation signal based on the difference between a reference signal and a feedback signal associated with the output signal. The comparator circuit is coupled to the error amplifier circuit and compares the compensation signal with a ramp signal to generate a task signal. The task signal has an enable level when the compensation signal exceeds the ramp signal. The dynamic adjustment circuit is coupled to the error amplifier circuit and the output node and detects high-frequency components of the output signal changes based on the feedback signal to generate a dynamic adjustment signal. The dynamic adjustment signal corresponds to the changes in the output signal, and the dynamic adjustment circuit uses the dynamic adjustment signal to control the error amplifier circuit to cause the event of the compensation signal exceeding the ramp signal to occur or end earlier, thereby adjusting the duty cycle.

[0004] In some embodiments, the dynamic adjustment circuit includes a high-pass filter circuit and an error amplifier. The high-pass filter circuit receives the feedback signal and performs high-pass filtering on the feedback signal to generate a filtered signal. The error amplifier is coupled to the high-pass filter circuit, receives the feedback signal and the filtered signal, and amplifies the difference between the feedback signal and the filtered signal to generate the dynamic adjustment signal.

[0005] In some embodiments, the dynamic adjustment circuit further includes an adder circuit. The adder circuit is coupled to the non-inverting input of the error amplifier circuit and is used to add the dynamic adjustment signal to the reference signal, wherein the inverting input of the error amplifier circuit is used to receive the feedback signal.

[0006] In some embodiments, the dynamic adjustment circuit further includes a subtraction circuit. The subtraction circuit is coupled to the inverting input of the error amplifier circuit and is used to subtract the dynamic adjustment signal from the feedback signal, wherein the non-inverting input of the error amplifier circuit is used to receive the reference signal.

[0007] In some embodiments, the dynamic adjustment circuit further includes an adder circuit. The adder circuit is coupled to the output of the error amplifier circuit and is used to add the compensation signal to the dynamic adjustment signal, wherein the inverting input of the error amplifier circuit is used to receive the feedback signal, and the non-inverting input of the error amplifier circuit is used to receive the reference signal.

[0008] In some embodiments, the dynamic adjustment circuit includes a differentiator circuit. The differentiator circuit is used to receive the feedback signal and to perform a differentiating operation on the feedback signal to generate the dynamic adjustment signal.

[0009] In some embodiments, the dynamic adjustment circuit is coupled to the non-inverting input of the error amplifier circuit and adjusts the reference signal with the dynamic adjustment signal to control the error amplifier circuit to accelerate the compensation signal overtaking the ramp signal.

[0010] In some embodiments, the dynamic adjustment circuit is coupled to the inverting input of the error amplifier circuit and adjusts the feedback signal with the dynamic adjustment signal to control the error amplifier circuit to accelerate the compensation signal overtaking the ramp signal.

[0011] In some embodiments, the dynamic adjustment circuit is coupled to the output of the error amplifier circuit and adjusts the compensation signal with the dynamic adjustment signal to control the error amplifier circuit to accelerate the compensation signal to surpass the ramp signal.

[0012] One embodiment of this utility model is a power converter circuit. The power converter circuit includes a power stage circuit and a control circuit. The power stage circuit is coupled to the output node of the power converter circuit and generates an output signal at the output node according to a duty cycle. The control circuit receives a reference signal, a feedback signal related to the output signal, and a ramp signal, and includes an error amplifier circuit, a comparator circuit, and a dynamic adjustment circuit. The error amplifier circuit is coupled to the output node and outputs a compensation signal based on the difference between the reference signal and the feedback signal. The comparator circuit is coupled to the error amplifier circuit and compares the compensation signal with the ramp signal to generate a task signal. The task signal has an enable level when the compensation signal exceeds the ramp signal. The dynamic adjustment circuit is coupled to the error amplifier circuit and the output node and detects high-frequency components of changes in the output signal based on the feedback signal to generate a dynamic adjustment signal. The dynamic adjustment signal corresponds to the output signal in terms of change, and the dynamic adjustment circuit is used to control the error amplification circuit with the dynamic adjustment signal so that the event of the compensation signal exceeding the ramp signal occurs or ends earlier, thereby adjusting the duty cycle.

[0013] In summary, by detecting the high-frequency components of the output signal during changes to generate a dynamic adjustment signal, the control circuit of this invention allows the event of the compensation signal exceeding the ramp signal to occur or end earlier, thus avoiding undershoot or overshoot phenomena in the output signal. Therefore, the power converter circuit and its control circuit of this invention have advantages such as excellent load transient response capability and high power supply stability. Attached Figure Description

[0014] Figure 1 This is a circuit diagram illustrating a power converter circuit according to some embodiments of the present invention.

[0015] Figure 2A This is a timing diagram illustrating the compensation signal and ramp signal when a load withdrawal event occurs in the load device, according to some embodiments of the present invention.

[0016] Figure 2B This is a timing diagram illustrating the feedback signal and reference signal when a load withdrawal event occurs in the load device, according to some embodiments of the present invention.

[0017] Figure 3A This is a timing diagram illustrating the compensation signal and ramp signal when a load removal event occurs, according to some embodiments of the present invention.

[0018] Figure 3BThis is a timing diagram illustrating the feedback signal and reference signal when a load removal event occurs, according to some embodiments of the present invention.

[0019] Figure 4 This is a circuit diagram illustrating a power converter circuit according to some embodiments of the present invention.

[0020] Figure 5 This is a circuit diagram illustrating a power converter circuit according to some embodiments of the present invention.

[0021] Figure 6 This is a circuit diagram illustrating a dynamic adjustment circuit according to some embodiments of the present invention. Detailed Implementation

[0022] The following detailed description of embodiments, in conjunction with the accompanying drawings, is provided. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure resulting from the recombination of elements and producing a device with equivalent functionality is within the scope of this utility model.

[0023] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0024] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0025] Please see Figure 1 , Figure 1 This is a circuit diagram illustrating a power converter circuit 100 according to some embodiments of the present invention. Specifically, the power converter circuit 100 may be a DC / DC converter, such as a single-phase or multi-phase buck converter. In some embodiments, the power converter circuit 100 is used to convert the input voltage VIN into an output signal OUT at the output node NOUT. The output signal OUT may be a voltage signal. The load device LD may be electrically coupled to the output node NOUT, and the power converter circuit 100 may supply power to the load device LD through the output signal OUT. It should be understood that the load device LD may be a device such as a central processing unit (CPU).

[0026] In some embodiments, such as Figure 1As shown, the power converter circuit 100 includes a control circuit 10A, a conduction time generation circuit 20, and a power stage circuit 30. The power stage circuit 30 includes a drive circuit 310, a high-side switch M1, and a low-side switch M2. Specifically, the high-side switch M1 and the low-side switch M2 can each be implemented using a metal-oxide-semiconductor transistor, but this invention is not limited thereto. The control terminal (e.g., gate terminal) of the high-side switch M1 and the control terminal (e.g., gate terminal) of the low-side switch M2 are both coupled to the drive circuit 310. The remaining two ends of the high-side switch M1 (e.g., source and drain terminals) are respectively coupled to the input voltage VIN and the phase output node (not shown in the figure), and the remaining two ends of the low-side switch M2 (e.g., source and drain terminals) are respectively coupled to the phase output node and the ground terminal (which is used to receive the ground voltage (not shown in the figure)).

[0027] As described in the above embodiments, the drive circuit 310 of the power stage circuit 30 is coupled to the conduction time generation circuit 20 and can be controlled by the control signal CS (e.g., a pulse width modulation (PWM) signal) output by the conduction time generation circuit 20 to generate a high-side drive signal (not shown) and a low-side drive signal (not shown) to the high-side switch M1 and the low-side switch M2. The control signal CS has a preset duty cycle. That is, each pulse period of the control signal CS includes an enable period and a disable period, and the enable period and disable period are set according to a preset ratio. The high-side drive signal can be in phase with the control signal CS, while the low-side drive signal can be out of phase with the control signal CS. Accordingly, the high-side switch M1 and the low-side switch M2 are alternately turned on according to the high-side drive signal and the low-side drive signal to generate a phase output signal (not shown) at the phase output node. The output signal can be a square waveform voltage signal, and the voltage level of this square waveform voltage signal can be switched between the voltage level of the input voltage VIN and the voltage level of the ground voltage.

[0028] like Figure 1 As shown, the phase output node is coupled to the output node NOUT via inductor L, and capacitor CO and resistor RO are connected in series between the output node NOUT and the ground terminal. The circuit composed of inductor L, capacitor CO, and resistor RO processes the phase output signal at the phase output node, so that the output signal OUT is generated at the output node NOUT. As can be seen from the above description of the conduction time generation circuit 20 and the power stage circuit 30, the power stage circuit 30 is used to generate the output signal OUT at the output node NOUT according to the duty cycle of the control signal CS.

[0029] In some practical applications, the load device LD may switch to a light-load or heavy-load state due to temporary changes in task (e.g., running a specific application and / or software). Compared to the light-load state, the load device LD requires a larger operating current in real time under heavy-load conditions. When the load device LD switches to a light-load or heavy-load state, the change in its operating current will correspondingly cause the output signal OUT voltage level to rise or fall.

[0030] In view of the aforementioned changes in the voltage level of the output signal OUT, in some embodiments, the control circuit 10A is coupled between the output node NOUT and the on-time generation circuit 20 to form a feedback loop. Through this feedback loop, the power converter circuit 100 can adjust the duty cycle of the control signal CS in real time in response to changes in the voltage level of the output signal OUT, thereby improving the stability of the output signal OUT. This principle will be further explained in later paragraphs.

[0031] The control circuit 10A includes an error amplifier circuit 120, a comparator circuit 110, and a dynamic adjustment circuit 130A. In some embodiments, the error amplifier circuit 120 is implemented using an error amplifier. The non-inverting input (+) of the error amplifier circuit 120 is coupled to a reference signal REF, while the inverting input (-) of the error amplifier circuit 120 is coupled to a feedback signal FB associated with the output signal OUT. Specifically, the reference signal REF may be a voltage signal with a fixed voltage level. The feedback signal FB may reflect changes in the output signal OUT. For example, the feedback signal FB may be the output signal OUT or a voltage signal proportional to the output signal OUT. The error amplifier circuit 120 outputs a compensation signal COMP based on the difference between the reference signal REF and the feedback signal FB. For example, the error amplifier circuit 120 amplifies the result of subtracting the feedback signal FB from the reference signal REF to output the compensation signal COMP.

[0032] In some embodiments, the comparator circuit 110 is implemented using a comparator. The non-inverting input (+) of the comparator circuit 110 is coupled to the output of the error amplifier circuit 120, the inverting input (-) of the comparator circuit 110 is coupled to the ramp signal RAMP, and the output of the comparator circuit 110 is coupled to the on-time generation circuit 20. Specifically, the ramp signal RAMP can be a triangular waveform voltage signal. The comparator circuit 110 outputs a task signal DTY to the on-time generation circuit 20 based on the compensation signal COMP and the ramp signal RAMP. For example, the comparator circuit 110 compares the compensation signal COMP and the ramp signal RAMP to output a task signal DTY with an enable or disable level based on the comparison result of the compensation signal COMP and the ramp signal RAMP. In some embodiments, the ramp signal RAMP can be generated based on the inductor current flowing through the inductor L (not shown), based on the voltage drop based on the inductor current (not shown), or based on the result of filtering the phase output signal at the phase output node.

[0033] As described in the above embodiments, when the voltage level of the output signal OUT decreases significantly due to the load device LD switching to a heavy load state, the voltage level of the feedback signal FB also decreases significantly, causing the voltage level of the compensation signal COMP to increase. Furthermore, when the voltage level of the compensation signal COMP increases to a level greater than the voltage level of the ramp signal RAMP, the comparator circuit 110 controls the task signal DTY to have an enable level. The on-time generation circuit 20, in response to the enable level of the task signal DTY, changes the pulse period (or duty cycle) of the control signal CS. For example, the on-time generation circuit 20 shortens the inactivation period of the control signal CS in each pulse period. This increases the frequency at which the high-side switch M1 and the low-side switch M2 alternately conduct, thus mitigating the sudden decrease in the output signal OUT, such as softening the decrease in the voltage level of the output signal OUT or changing the voltage level of the output signal OUT from decreasing to increasing.

[0034] On the other hand, when the voltage level of the output signal OUT increases significantly due to the load device LD switching to a light load state, the voltage level of the feedback signal FB also increases significantly, causing the voltage level of the compensation signal COMP to decrease. Furthermore, when the voltage level of the compensation signal COMP decreases to be equal to or less than the voltage level of the ramp signal RAMP, the comparator circuit 110 controls the task signal DTY to have a disabled level. The on-time generation circuit 20, in response to the disabled level of the task signal DTY, changes the pulse period (or duty cycle) of the control signal CS. For example, the on-time generation circuit 20 extends the disabled period of the control signal CS in each pulse period. This reduces the frequency at which the high-side switch M1 and the low-side switch M2 alternately conduct, thus mitigating the sudden increase in the output signal OUT, such as softening the increase in the voltage level of the output signal OUT or changing the voltage level of the output signal OUT from increasing to decreasing.

[0035] As described above regarding the error amplifier circuit 120 and the comparator circuit 110, the control circuit 10A receives the reference signal REF, the feedback signal FB related to the output signal OUT, and the ramp signal RAMP. It generates a compensation signal COMP based on the reference signal REF and the feedback signal FB. When the compensation signal COMP exceeds the ramp signal RAMP (i.e., when the voltage level of the compensation signal COMP is greater than the voltage level of the ramp signal RAMP), it generates a task pulse signal (i.e., the task signal DTY at the enable level) to the conduction time generation circuit 20 to regulate the sudden decrease of the output signal OUT. Furthermore, when the voltage level of the compensation signal COMP is not greater than the voltage level of the ramp signal RAMP, the control circuit 10A stops generating the task pulse signal to the conduction time generation circuit 20 (i.e., the comparator circuit 110 outputs the task signal DTY at the disable level to the conduction time generation circuit 20) to regulate the sudden increase of the output signal OUT.

[0036] In some practical applications, the control circuit 10A is slow to generate or stop generating task pulse signals in response to changes in the output signal OUT, making the output signal OUT more prone to overshoot or undershoot. Therefore, in some embodiments, the dynamic adjustment circuit 130A is coupled to the error amplifier circuit 120 and the output node NOUT, and the dynamic adjustment signal DLL can control the error amplifier circuit 120 to speed up the generation or stopping of task pulse signals by the control circuit 10A, thereby improving the overshoot or undershoot phenomenon of the output signal OUT.

[0037] Specifically, such as Figure 1As shown, the dynamic adjustment circuit 130A includes a high-pass filter circuit HPF and an error amplifier HV, and the control circuit 10A also includes an adder circuit C1. Specifically, the high-pass filter circuit HPF is used to receive the feedback signal FB and is coupled to the inverting input (-) of the error amplifier HV. The non-inverting input (+) of the error amplifier HV is used to receive the feedback signal FB. Furthermore, the adder circuit C1 is coupled to the non-inverting input of the error amplifier circuit 120 and the output of the error amplifier HV, and is used to receive the reference signal REF. The adder circuit C1 adds the dynamic adjustment signal DLL to the reference signal REF to generate another reference signal REFS (i.e., the adjusted reference signal REF).

[0038] Next, the pairing Figures 2A-2B Detailed description Figure 1 The operation of the control circuit 10A in the load device LD when a load withdrawal event occurs (e.g., the operation of the control circuit 10A when a load withdrawal event occurs when the load device LD is in a light load state). Figure 2A This is a timing diagram illustrating the compensation signal COMP and the ramp signal RAMP during a load withdrawal event in the load device LD, according to some embodiments of the present invention. Figure 2B This is a timing diagram illustrating the feedback signal FB and reference signal REFS during a load withdrawal event in the load device LD, according to some embodiments of the present invention. Furthermore, to illustrate the function of the dynamic adjustment signal DLL, [the following is a separate section]... Figure 2A The existing compensation signal WCOMP and the existing ramp signal WRAMP are also shown, and in Figure 2B The existing feedback signal WFB and the existing reference signal WREF are also shown. Note that the compensation signal COMP, the ramp signal RAMP, the feedback signal FB, and the reference signal REFS are all related to the dynamic adjustment signal DLL, while the existing compensation signal WCOMP, the existing ramp signal WRAMP, the existing feedback signal WFB, and the existing reference signal WREF are all independent of the dynamic adjustment signal DLL.

[0039] At Figures 2A-2B In one embodiment, the operating current of the load device LD increases, for example, from 1 mA to 15 amps, which is an example of a load device LD experiencing a de-loading event under a light load condition. Accordingly, the output signal OUT experiences transient disturbances and contains high-frequency components, such as a sudden decrease in the voltage level of the output signal OUT. Figure 2BAs shown, the feedback signal FB decreases significantly as the output signal OUT changes. A high-pass filter circuit HPF performs a high-pass filter on the feedback signal FB to generate a filtered signal (not shown in the figure). An error amplifier HV amplifies the difference between the feedback signal FB and the filtered signal (e.g., the feedback signal FB minus the filtered signal) to generate a dynamic adjustment signal DLL. In short, the dynamic adjustment circuit 130A detects the high-frequency components of the output signal OUT when the feedback signal FB changes, thereby generating the dynamic adjustment signal DLL.

[0040] Following the description of the above embodiments, the dynamically adjusted signal DLL and the output signal OUT are responsive to each other in their changes. For example... Figure 1 As shown, the adder circuit C1 adds the dynamic adjustment signal DLL to the reference signal REF to generate the reference signal REFS. For example... Figure 2B As shown, compared to the existing reference signal WREF with a fixed voltage level, the reference signal REFS generated by adding the dynamic adjustment signal DLL to the reference signal REF exhibits an inverse relationship with the feedback signal FB in terms of its changes. That is, when the voltage level of the feedback signal FB (or the output signal OUT) decreases, the voltage level of the dynamic adjustment signal DLL increases.

[0041] like Figure 2A As shown, the dynamic adjustment signal DLL is added to the reference signal REF through the adder circuit C1. The compensation signal COMP generated by the error amplifier circuit 120 surpasses the ramp signal RAMP at time point a1. Without the dynamic adjustment signal DLL, the existing compensation signal WCOMP surpasses the existing ramp signal WRAMP at time point a2, which is later than time point a1. Figure 2B As shown, this time difference causes the feedback signal FB to experience a voltage rise earlier than the existing feedback signal WFB (i.e., the voltage level changes from decreasing to increasing). Accordingly, as... Figure 2A As shown, the compensation signal COMP generated by the error amplifier circuit 120 stops exceeding the ramp signal RAMP at time point a3 (that is, the voltage level of the compensation signal COMP is equal to or less than the voltage level of the ramp signal RAMP). Without the dynamic adjustment signal DLL, the existing compensation signal WCOMP stops exceeding the existing ramp signal WRAMP at time point a4, which is later than time point a3. For example... Figure 2B As shown, this time difference allows the feedback signal FB to stop increasing voltage earlier than the existing feedback signal WFB. Therefore, the feedback signal FB can return to steady state faster than the existing feedback signal WFB, avoiding overshoot.

[0042] From the above Figures 2A-2BAs can be seen from the description of the embodiment, in the event of a load withdrawal event, the control circuit 10A dynamically adjusts the signal DLL to make the compensation signal COMP exceed the ramp signal RAMP earlier, and also makes the compensation signal COMP stop exceeding the ramp signal RAMP earlier, so that the conduction time generation circuit 20 can react quickly to the load withdrawal event and avoid the output signal OUT from overshooting and return to steady state more quickly.

[0043] In some embodiments, when a load event occurs in the load device LD under heavy load conditions (e.g., the operating current of the load device LD increases from 10 amps to 25 amps), the dynamic adjustment circuit 130A generates a dynamic adjustment signal DLL based on the change in the output signal OUT. The compensation signal COMP exceeds the ramp signal RAMP earlier, and the compensation signal COMP stops exceeding the ramp signal RAMP earlier, so that the on-time generation circuit 20 can react quickly to the load event under heavy load conditions, and the output signal OUT returns to the steady state more quickly.

[0044] Next, the pairing Figures 3A-3B The compensation signal COMP, ramp signal RAMP, feedback signal FB, and reference signal REFS are described in detail. Figure 1 The operation of control circuit 10A in the system when a load device LD experiences a removal event (e.g., when a load device LD experiences a removal event while under light load). Similar to... Figures 2A-2B The following explanation is provided to illustrate the role of the dynamically adjusted signal DLL. Figures 3A-3B The existing compensation signal WCOMP, the existing ramp signal WRAMP, the existing feedback signal WFB, and the existing reference signal WREF are also shown.

[0045] At Figures 3A-3B In this embodiment, a load device LD experiences a disconnection event. Accordingly, the voltage level of the output signal OUT suddenly increases. For example... Figure 3B As shown, the feedback signal FB increases significantly from time point a5 as the output signal OUT changes. The dynamic adjustment circuit 130A detects the high-frequency components of the output signal OUT when it changes based on the feedback signal FB, and generates a dynamic adjustment signal DLL. The adder circuit C1 adds the dynamic adjustment signal DLL to the reference signal REF to generate the reference signal REFS, and provides the reference signal REFS to the error amplifier circuit 120 to generate the compensation signal COMP.

[0046] like Figure 3AAs shown, the voltage level of the compensation signal COMP generated by the error amplifier circuit 120 is much lower than the voltage level of the ramp signal RAMP after time point a5. Furthermore, the voltage level of the existing compensation signal WCOMP, which is unrelated to the dynamic adjustment signal DLL, is also much lower than the voltage level of the existing ramp signal WRAMP after time point a5. Since the task signal DTY is at a disabled level at this time, the pulse period (or duty cycle) of the control signal CS remains unchanged. Therefore, during most stages when the output signal OUT suddenly increases from steady state due to the load device LD being removed, the impact of the dynamic adjustment signal DLL on the feedback signal FB is relatively limited.

[0047] For example Figure 3A As shown, the compensation signal COMP generated by the error amplifier circuit 120 surpasses the ramp signal RAMP at time point a6. Without the dynamic adjustment signal DLL, the existing compensation signal WCOMP surpasses the existing ramp signal WRAMP only at time point a7, which is later than time point a6. For example... Figure 3B As shown, this time difference causes the feedback signal FB to stop voltage earlier than the existing feedback signal WFB, thus the feedback signal FB does not experience undershoot compared to the existing feedback signal WFB.

[0048] From the above Figures 3A-3B As can be seen from the description of the embodiment, in the event of a removal event, the control circuit 10A dynamically adjusts the signal DLL to make the compensation signal COMP exceed the ramp signal RAMP earlier, so that the conduction time generation circuit 20 can react quickly to the removal event and avoid the output signal OUT from undershooting and return to steady state more quickly.

[0049] In some embodiments, when a load device LD experiences a removal event under heavy load conditions, the dynamic adjustment circuit 130A generates a dynamic adjustment signal DLL based on the change in the output signal OUT, and the compensation signal COMP exceeds the ramp signal RAMP earlier, so that the on-time generation circuit 20 can react quickly to the removal event under heavy load conditions, and the output signal OUT returns to a steady state more quickly.

[0050] From the above Figure 1 , Figures 2A-2B ,and Figures 3A-3B As can be seen from the description of the embodiment, the dynamic adjustment circuit 130A can be coupled to the non-inverting input terminal of the error amplifier circuit 120, and the reference signal REF is adjusted by the dynamic adjustment signal DLL to control the error amplifier circuit 120 to accelerate the compensation signal COMP overtaking the ramp signal RAMP. It should be understood that the power converter circuit 100 of this utility model is not limited to its application. Figure 1 The control circuit 10A in the middle will be described in the following paragraph. Figure 4 and Figure 5 Further explanation.

[0051] Please see Figure 4 , Figure 4 This is a circuit diagram illustrating a power converter circuit 100 according to some embodiments of the present invention. Figure 4 In the embodiment, control circuit 10B replaces Figure 1 The control circuit 10A of the power converter circuit 100 includes an error amplifier circuit 120, a comparator circuit 110, a subtraction circuit C2, and a dynamic adjustment circuit 130B. The implementation of the dynamic adjustment circuit 130B is the same as that of the dynamic adjustment circuit 130A, and therefore will not be described in detail here. The subtraction circuit C2 is coupled to the inverting input of the error amplifier circuit 120 and the dynamic adjustment circuit 130B, and is used to receive the feedback signal FB. When the dynamic adjustment circuit 130B generates a dynamic adjustment signal DLL in response to the high-frequency components of the output signal OUT (e.g., a sudden decrease or increase in the output signal OUT), the subtraction circuit C2 subtracts the dynamic adjustment signal DLL from the feedback signal FB to generate another feedback signal FBS (i.e., the adjusted feedback signal FB), and provides the feedback signal FBS to the error amplifier circuit 120 to generate the compensation signal COMP. Since the dynamic adjustment signal DLL and the output signal OUT are corresponding in their changes, the dynamic adjustment signal DLL is subtracted from the feedback signal FB by the subtraction circuit C2. The compensation signal COMP generated by the error amplifier circuit 120 surpasses the ramp signal RAMP earlier to avoid overshooting or undershooting of the output signal OUT.

[0052] Depend on Figure 4 As can be seen from the description of the embodiment, the dynamic adjustment circuit 130B is coupled to the inverting input terminal of the error amplifier circuit 120, and the dynamic adjustment signal DLL adjusts the feedback signal FB to control the error amplifier circuit 120 to accelerate the compensation signal COMP to surpass the ramp signal RAMP.

[0053] Please see Figure 5 , Figure 5 This is a circuit diagram illustrating a power converter circuit 100 according to some embodiments of the present invention. Figure 5 In this embodiment, the control circuit 10C replaces Figure 1The control circuit 10A of the power converter circuit 100 includes an error amplifier circuit 120, a comparator circuit 110, an adder circuit C3, and a dynamic adjustment circuit 130C. The implementation of the dynamic adjustment circuit 130C is the same as that of the dynamic adjustment circuit 130A, and therefore will not be described in detail here. The adder circuit C3 is coupled to the output terminal of the error amplifier circuit 120 and the dynamic adjustment circuit 130C, and is used to receive the compensation signal COMP. When the dynamic adjustment circuit 130C generates a dynamic adjustment signal DLL in response to the high-frequency components of the output signal OUT (e.g., a sudden decrease or increase in the output signal OUT), the adder circuit C3 adds the compensation signal COMP to the dynamic adjustment signal DLL to generate another compensation signal COMP (i.e., the adjusted compensation signal COMP), and provides the compensation signal COMP to the non-inverting input terminal of the comparator circuit 110. Since the dynamic adjustment signal DLL and the output signal OUT are corresponding in their changes, the compensation signal COMP is added to the dynamic adjustment signal DLL through the adder circuit C3. The compensation signal COMP generated by the error amplifier circuit 120 surpasses the ramp signal RAMP earlier, so as to avoid the output signal OUT from overshooting or undershooting.

[0054] Depend on Figure 5 As can be seen from the description of the embodiment, the dynamic adjustment circuit 130C is coupled to the output terminal of the error amplifier circuit 120, and the dynamic adjustment signal DLL adjusts the compensation signal COMP, so as to control the error amplifier circuit 120 to speed up the compensation signal COMP to surpass the ramp signal RAMP.

[0055] Furthermore, the power converter circuit 100 of this utility model is not limited to applications. Figure 1 The dynamic adjustment circuit 130A in the middle Figure 4 The dynamic adjustment circuit 130B and Figure 5 The dynamic adjustment circuit 130C is described in the example. For instance, please refer to... Figure 6 , Figure 6 This is a circuit diagram illustrating a dynamic adjustment circuit 130D according to some embodiments of the present invention. The dynamic adjustment circuit 130D can replace... Figure 1 The dynamic adjustment circuit 130A in the middle Figure 4 The dynamic adjustment circuit 130B or Figure 5The dynamic adjustment circuit 130C is included. In some embodiments, the dynamic adjustment circuit 130D includes a differentiator circuit D1. The differentiator circuit D1 is coupled to the output node NOUT and the conduction time generation circuit 20 to receive the feedback signal FB and to perform a differentiating operation on the feedback signal FB to generate a dynamic adjustment signal DLL. The dynamic adjustment signal DLL generated by the differentiator circuit D1 on the feedback signal FB corresponds to the output signal OUT in terms of change, and can therefore be used to adjust the reference signal REF, the feedback signal FB, or the compensation signal COMP, thereby controlling the error amplifier circuit 120 to accelerate the compensation signal COMP overtaking the ramp signal RAMP.

[0056] As can be seen from the above embodiments of this utility model, by detecting the high-frequency components of the output signal OUT when it changes, a dynamic adjustment signal DLL is generated. The control circuit of this utility model allows the event of the compensation signal COMP exceeding the ramp signal RAMP to occur or end earlier, thereby avoiding undershooting or overshooting of the output signal OUT. Therefore, the power converter circuit and its control circuit of this utility model have advantages such as excellent load transient response capability and high power stability.

[0057] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0058] [Symbol Explanation]

[0059] 10A, 10B, 10C: Control circuit

[0060] 20: On-time generation circuit

[0061] 30: Power stage circuit

[0062] 100: Power converter circuit

[0063] 110: Comparator circuit

[0064] 120: Error Amplifier Circuit

[0065] 130A, 130B, 130C, 130D: Dynamic adjustment circuit

[0066] 310: Drive circuit

[0067] a1, a2, a3, a4, a5, a6, a7: Time points

[0068] C1, C3: Adder circuit

[0069] C2: Subtraction circuit

[0070] CO: Capacitor

[0071] COMP, COMPS: Compensation signals

[0072] CS: Control signal

[0073] D1: Differentiator circuit

[0074] DLL: Dynamically Adjustable Signal

[0075] DTY: Mission Signal

[0076] FB, FBS: Feedback signals

[0077] HPF: High-pass filter circuit

[0078] HV: Error amplifier

[0079] L: Inductance

[0080] LD: Load device

[0081] M1: High-side switch

[0082] M2: Low-side switch

[0083] NOUT: Output node

[0084] OUT: Output signal

[0085] RAMP: Ramp Signal

[0086] REF, REFS: Reference signals

[0087] RO: Resistance

[0088] VIN: Input voltage

[0089] WCOMP: Existing compensation signal

[0090] WFB: Existing feedback signal

[0091] WRAMP: Existing ramp signal

[0092] WREF: Existing reference signal.

Claims

1. A control circuit, characterized in that, Suitable for power converter circuits, wherein the power converter circuit includes a power stage circuit for generating an output signal at the output node of the power converter circuit according to a duty cycle, and the control circuit includes: An error amplifier circuit is coupled to the output node and is used to output a compensation signal based on the difference between the reference signal and the feedback signal associated with the output signal. A comparator circuit, coupled to the error amplifier circuit, is used to compare the compensation signal with the ramp signal to generate a task signal, wherein the task signal has an enable level when the compensation signal exceeds the ramp signal; and A dynamic adjustment circuit is coupled to the error amplifier circuit and the output node, and is used to detect the high-frequency components of the output signal when the feedback signal changes, so as to generate a dynamic adjustment signal. The dynamic adjustment signal corresponds to the changes in the output signal, and the dynamic adjustment circuit is used to control the error amplifier circuit with the dynamic adjustment signal so that the event of the compensation signal exceeding the ramp signal occurs or ends earlier, thereby adjusting the duty cycle.

2. The control circuit according to claim 1, characterized in that, The dynamic adjustment circuit includes: A high-pass filter circuit is used to receive the feedback signal and to perform high-pass filtering on the feedback signal to generate a filtered signal. as well as An error amplifier, coupled to the high-pass filter circuit, is used to receive the feedback signal and the filtered signal, and to amplify the difference between the feedback signal and the filtered signal to generate the dynamic adjustment signal.

3. The control circuit according to claim 2, characterized in that, The dynamic adjustment circuit further includes: An adder circuit, coupled to the non-inverting input of the error amplifier circuit, is used to add the dynamic adjustment signal to the reference signal. The inverting input of the error amplifier circuit is used to receive the feedback signal.

4. The control circuit according to claim 2, characterized in that, The dynamic adjustment circuit further includes: A subtraction circuit, coupled to the inverting input of the error amplifier circuit, is used to subtract the dynamic adjustment signal from the feedback signal. The non-inverting input of the error amplifier circuit is used to receive the reference signal.

5. The control circuit according to claim 2, characterized in that, The dynamic adjustment circuit further includes: An adder circuit, coupled to the output of the error amplifier circuit, is used to add the compensation signal to the dynamic adjustment signal. The inverting input of the error amplifier circuit is used to receive the feedback signal, and the non-inverting input of the error amplifier circuit is used to receive the reference signal.

6. The control circuit according to claim 1, characterized in that, The dynamic adjustment circuit includes: A differentiator circuit is used to receive the feedback signal and to perform a differentiating operation on the feedback signal to generate the dynamic adjustment signal.

7. The control circuit according to claim 1, characterized in that, The dynamic adjustment circuit is coupled to the non-inverting input of the error amplifier circuit and adjusts the reference signal with the dynamic adjustment signal to control the error amplifier circuit to accelerate the compensation signal from overtaking the ramp signal.

8. The control circuit according to claim 1, characterized in that, The dynamic adjustment circuit is coupled to the inverting input of the error amplifier circuit and adjusts the feedback signal with the dynamic adjustment signal to control the error amplifier circuit to accelerate the compensation signal from overtaking the ramp signal.

9. The control circuit according to claim 1, characterized in that, The dynamic adjustment circuit is coupled to the output of the error amplifier circuit and adjusts the compensation signal with the dynamic adjustment signal to control the error amplifier circuit to accelerate the compensation signal to surpass the ramp signal.

10. A power converter circuit, characterized in that, Include: A power stage circuit is coupled to the output node of the power converter circuit and is used to generate an output signal at the output node according to the duty cycle. as well as A control circuit for receiving a reference signal, a feedback signal associated with the output signal, and a ramp signal, and comprising: An error amplifier circuit is coupled to the output node and is used to output a compensation signal based on the difference between the reference signal and the feedback signal. A comparator circuit, coupled to the error amplifier circuit, is used to compare the compensation signal with the ramp signal to generate a task signal, wherein the task signal has an enable level when the compensation signal exceeds the ramp signal; and A dynamic adjustment circuit is coupled to the error amplifier circuit and the output node, and is used to detect the high-frequency components of the output signal when the feedback signal changes, so as to generate a dynamic adjustment signal. The dynamic adjustment signal corresponds to the changes in the output signal, and the dynamic adjustment circuit is used to control the error amplifier circuit with the dynamic adjustment signal so that the event of the compensation signal exceeding the ramp signal occurs or ends earlier, thereby adjusting the duty cycle.

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