A TIADC time mismatch error all-digital background calibration system

Abstract

The utility model discloses a TIADC time mismatch error all -digital backstage calibration system relates to the field of analog -to -digital converter, solves the technical problem that present calibration technique is difficult to satisfy the requirement of wide band, low resource, high robustness, high accuracy simultaneously, the utility model discloses a TIADC digital analog conversion module, error calibration module, error estimation module and multiplexer, the TIADC digital analog conversion module includes multipath digital analog conversion circuit, and each digital analog conversion circuit includes the sampling hold -off circuit and digital analog converter that connect gradually, and the input of sampling hold -off circuit connects input analog signal and sampling clock, and the output of digital analog converter connects error calibration module, the input of error estimation module and the input of multiplexer are connected respectively to the output of error calibration module, the input of error calibration module is connected to the output of error estimation module, and the output of multiplexer exports the output signal after calibration, the utility model discloses have simple structure, the remarkable advantage of easy hardware implementation.

Claims

1. A fully digital back-end calibration system for TIADC time mismatch error, characterized in that, It includes a TIADC digital-to-analog converter module, an error calibration module, an error estimation module, and a multiplexer; The TIADC analog-to-digital conversion module includes multiple analog-to-digital conversion circuits. Each of the analog-to-digital conversion circuits includes a sample-and-hold circuit and an analog-to-digital converter connected in sequence. The input terminal of the sample-and-hold circuit is used to receive the input analog signal and the sampling clock. The output terminal of the analog-to-digital converter is connected to the error calibration module. The error calibration module receives four digital signals after analog-to-digital conversion at its input terminal and has three first-order three-point compensation circuits internally. The first digital signal is directly output as a pass-through reference signal, and the second to fourth digital signals are compensated by their respective first-order three-point compensation circuits to obtain three compensated signals. The error calibration module uses the pass-through reference signal and the three compensated signals as four calibration signals and outputs them simultaneously to the error estimation module and the multiplexer. The error estimation module receives the four calibration signals at its input and its output is connected to the feedback input of the error calibration module. The error estimation module includes four error estimation circuits, a matrix operation unit, and a three-channel adaptive iteration module. The four error estimation circuits perform error estimation on the four calibration signals respectively, generating four error signals. After processing by the matrix operation unit, these signals are input to the three-channel adaptive iteration module for LMS iterative update, generating three time mismatch error estimates, which are then fed back to the error calibration module. The multiplexer receives the four calibration signals output by the error calibration module and synthesizes them to output a single calibrated signal.

2. The TIADC time mismatch error fully digital back-end calibration system according to claim 1, characterized in that, Each error estimation circuit includes a subtractor SUB_DIFF, an absolute value operation module ABS, and a mean operation module AVG connected in sequence. The positive and negative terminals of the subtractor SUB_DIFF1 in the first error estimation circuit are connected to the second calibration signal and the first calibration signal, respectively. The positive and negative terminals of the subtractor SUB_DIFF4 in the fourth error estimation circuit are connected to the first calibration signal and the fourth calibration signal, respectively, after passing through the timing delay register SR_TD. The output terminal of the mean operation module AVG of the four error estimation circuits outputs four stable signals, which are connected in parallel to the input terminal of the matrix operation unit. The matrix operation unit outputs three output signals, which are connected to the input terminals of three adaptive iteration modules LMS, respectively. The adaptive iteration module LMS outputs the iterated signal.

3. The TIADC time mismatch error fully digital back-end calibration system according to claim 2, characterized in that, The adaptive iterative module LMS includes an iterative calculation unit, a data register SR_DT, a subtractor SUB_UPD, and a comparator connected in sequence. The positive and negative ends of the subtractor SUB_UPD are respectively connected to the data register SR_DT. The data register SR_DT outputs the value calculated in the current iteration and the value calculated in the previous iteration of the iterative calculation unit. The first input of the comparator is connected to the output of the subtractor SUB_UPD, and the second input of the comparator is connected to a preset threshold value.

4. The TIADC time mismatch error fully digital back-end calibration system according to claim 3, characterized in that, The iterative calculation unit includes a multiplier MUL_UPD, an adder ADD_UPD, and a delay register SR_DLY. The data input terminal of the multiplier MUL_UPD is connected to the output terminal of the matrix operation unit, the coefficient input terminal of the multiplier MUL_UPD is connected to the calculation coefficients, the output terminal of the multiplier MUL_UPD is connected to the first input terminal of the adder ADD_UPD, the output terminal of the adder ADD_UPD is connected to the input terminal of the delay register SR_DLY, and the output terminal of the delay register SR_DLY is connected to the second input terminal of the adder ADD_UPD and the input terminal of the data register SR_DT.

5. The TIADC time mismatch error fully digital back-end calibration system according to claim 1, characterized in that, The matrix operation unit includes shift registers SR_DLY1, SR_DLY2, SR_DLY3, SR_DLY4, adders ADD_MO1, ADD_MO2, ADD_MO3, ADD_MO4, ADD_MO5, ADD_MO6, ADD_MO7, subtractors SUB_MO1, SUB_MO2, and SUB_MO3. The input of shift register SR_DLY1 is connected to the first error signal. The output of shift register SR_DLY1 and the first error signal are respectively connected to the two inputs of adder ADD_MO1. The second and third error signals are respectively connected to the two inputs of adder ADD_MO2. The output of adder ADD_MO2 and the fourth error signal are respectively connected to the two inputs of adder ADD_MO3. The outputs of adder ADD_MO1 and adder ADD_MO3 are respectively connected to the positive and negative ends of subtractor SUB_MO1. The inputs of shift registers SR_DLY2, SR_DLY3, and SR_DLY4 are connected sequentially to the second, third, and fourth error signals, respectively. The outputs of shift registers SR_DLY1 and SR_DLY2 are connected to the two inputs of adder ADD_MO4, respectively. The outputs of shift registers SR_DLY3 and SR_DLY4 are connected to the two inputs of adder ADD_MO5, respectively. The outputs of adders ADD_MO4 and ADD_MO5 are then connected to the positive and negative terminals of subtractor SUB_MO2, respectively. Connect the second error signal and the output of adder ADD_MO2 to the two inputs of adder ADD_MO6 respectively; connect the fourth error signal and the output of shift register SR_DLY4 to adder ADD_MO7 respectively; finally, connect the outputs of adder ADD_MO6 and adder ADD_MO7 to the positive and negative ends of subtractor SUB_MO3 respectively.

6. The TIADC time mismatch error fully digital back-end calibration system according to claim 1, characterized in that, The error calibration module includes three first-order three-point compensation circuits. Each first-order three-point compensation circuit includes a subtractor SUB_CAL1, a multiplier MUL_CAL1, a multiplier MUL_CAL2, and a subtractor SUB_CAL2. The adjacent rear channel sampling signal and the adjacent front channel sampling signal are respectively connected to the positive and negative terminals of the subtractor SUB_CAL1. The output terminal of the subtractor SUB_CAL1 is connected to the data input terminal of the multiplier MUL_CAL1, and the coefficient input terminal of the multiplier MUL_CAL1 is connected to a fixed-amplifier circuit. The multiplier is set to 1 / 2; the output of multiplier MUL_CAL1 is connected to the data input of multiplier MUL_CAL2, and the coefficient input of multiplier MUL_CAL2 is connected to the estimated time mismatch error Δt; the output of multiplier MUL_CAL2 is connected to the negative input of subtractor SUB_CAL2, and the positive input of subtractor SUB_CAL2 is connected to the original sampled signal of the current channel; the output of subtractor SUB_CAL2 outputs the calibration signal after time mismatch compensation to the input of the multiplexer.

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