Semiconductor packaging structure

Abstract

This application discloses a semiconductor packaging structure, comprising: a redistribution layer having a first surface and a second surface opposite to the first surface; and a first chip connected to the first surface. The first surface of the redistribution layer includes a first reserved component region and a second reserved component region spaced apart from the first chip. The first reserved component region has a first function, and the second reserved component region has a second function, wherein the first function and the second function are different. The above technical solution of this application proposes an economical semiconductor packaging structure to solve the problems of high power consumption and high cost of existing packaging structures.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] With the rapid development of semiconductor technology, the requirements for semiconductor packaging structure performance are becoming increasingly stringent. As an example, current EDGE AI (edge ​​artificial intelligence) computing systems often face performance bottlenecks due to insufficient memory bandwidth when performing large amounts of computation. Because EDGE devices are limited by cost, power consumption, and space, they cannot utilize HBM (High Bandwidth Memory) like data centers. Therefore, when computational demands increase, system performance is often constrained by memory bandwidth, leading to decreased data access efficiency and impacting overall computational performance. As another example, LLM (Large Language Model) is a major AI (Artificial Intelligence) model with a massive number of parameters. Models like GPT-4 can have hundreds of billions of parameters, requiring powerful computing power to solve. This computing power includes both the processing processor and memory.

[0003] However, current mainstream technologies have the following problems:

[0004] (1) HBM and CoWoS (Chip on Wafer on Substrate) are costly. In the cloud, HBM technology, such as HBM2 and HBM3, is typically used to address memory bandwidth bottlenecks. Figure 1 As shown, a silicon interposer 30, a packaging substrate 50, and a circuit board 10 are vertically stacked. Multiple logic chips 40 are located on the silicon interposer 30, and multiple HBMs 20 are stacked on top of one logic chip 40. Multiple HBMs 20 can improve bandwidth and reduce power consumption through 3D stacking technology. The implementation of HBMs relies on advanced packaging technologies such as CoWoS, silicon interposers, wafer-level packaging, and through-silicon vias (TSV). While these technologies can improve memory performance, they are extremely expensive and difficult to apply on a large scale in EDGE computing scenarios.

[0005] (2) Increasing the number of layers in an FR4 (an epoxy resin-based material) PCB (printed circuit board) will increase the overall circuit board cost. In the EDGE sector, such as... Figure 2 As shown, FR4 PCB 12 is traditionally used to connect XPU 22 and SDRAM 42. However, due to the high complexity of the local interconnect structure, it is often necessary to increase the number of PCB layers to ensure signal integrity and stability. Increasing the number of layers only for the routing needs of a specific area will significantly increase the overall manufacturing cost of the circuit board. Utility Model Content

[0006] To address the above problems, this application proposes a relatively economical semiconductor packaging structure to solve the problems of high power consumption and high cost of existing packaging structures.

[0007] According to one aspect of this application, a semiconductor package structure is provided, comprising: a redistribution layer having a first surface and a second surface opposite to the first surface; a first chip connected to the first surface; wherein the first surface of the redistribution layer includes a first reserved component region and a second reserved component region arranged at a distance from the first chip, wherein the first reserved component region has a first function and the second reserved component region has a second function, the first function and the second function being different.

[0008] In some embodiments, a second chip is provided on the first reserved component area, wherein the first function of the first reserved component area is that the first chip and the second chip are interconnected by signal through the first reserved component area.

[0009] In some embodiments, a connector is provided on the second reserved area, wherein a second function of the second reserved area is that the connector is interconnected with an external device via a signal through the second reserved area.

[0010] In some embodiments, the semiconductor package structure further includes a molding layer located on the first surface and covering the first chip. In some embodiments, the molding layer is located outside the first reserved area and the second reserved area.

[0011] In some embodiments, the semiconductor package structure further includes an interposer layer connected beneath the second surface of the redistribution layer.

[0012] In some embodiments, the intermediary layer is located at the edge region of the second surface of the redistribution layer.

[0013] In some embodiments, the semiconductor package structure further includes passive components connected below the second surface of the redistribution layer.

[0014] In some embodiments, the first reserved area and the second reserved area are located around the first chip, and the first reserved area and the second reserved area are adjacent to the edge of the first chip on the first surface.

[0015] In some embodiments, the semiconductor package structure further includes a third chip located on the second surface of the redistribution layer; wherein the redistribution layer includes a dielectric layer and conductive lines located in the dielectric layer, and wherein a plurality of connection terminals in the first reserved area are connected to at least one of the first chip and the third chip via conductive lines.

[0016] In some embodiments, the semiconductor package structure further includes a molding layer that covers the second surface and encapsulates the third chip.

[0017] The technical solution of this application, by setting reserved component areas such as a first reserved component area and a second reserved component area, allows for the use of post-chip packaging methods to store the required components in the reserved component areas, thereby improving production flexibility and increasing the utilization rate of the redistribution layer. By replacing the silicon interposer with a redistribution layer, costs can be reduced by more than 90%. Replacing the existing FR4PCB with a redistribution layer reduces the footprint of the package structure, shortens the data transmission path, reduces latency, and improves the overall system energy efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a cross-sectional schematic diagram of a semiconductor packaging structure in the prior art.

[0020] Figure 2 This is a top view of another existing semiconductor packaging structure.

[0021] Figure 3A This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of this application.

[0022] Figure 3B This is a top view schematic diagram of a semiconductor packaging structure according to an embodiment of this application.

[0023] Figure 4 This is a cross-sectional schematic diagram of a semiconductor package structure according to another embodiment of this application.

[0024] Figure 5 This is a top view schematic diagram of a semiconductor package structure according to another embodiment of this application.

[0025] Figures 6A to 6I A schematic diagram of different stages during the formation of a semiconductor package structure according to another embodiment of this application is shown.

[0026] Figures 7A to 7I A schematic diagram of different stages during the formation of a semiconductor package structure according to another embodiment of this application is shown.

[0027] Figures 8A to 8C Schematic diagrams of various structures used for simulation verification are shown.

[0028] Figure 8D It shows the result of Figures 8A to 8CThe S-parameter insertion loss curves obtained from various structures are shown.

[0029] Figures 9A to 9D Schematic diagrams of several other structures used for simulation verification are shown.

[0030] Figure 9E It shows the result of Figures 9A to 9D Insertion loss curves obtained from various structures are shown. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0032] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0033] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] Figure 3A This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of this application. Figure 3B This is a top view schematic diagram of a semiconductor package structure according to an embodiment of this application. (Reference) Figure 3A and Figure 3B As shown, the semiconductor package structure 100A may include a redistribution layer (RDL) 110. The redistribution layer 120 has a first surface 121 and a second surface 122 opposite to the first surface 121. A first chip 141 is connected to the first surface 121.

[0035] The redistribution layer 120 includes a first reserved area A1 and a second reserved area A2 spaced apart from the first chip 141. Two second chips 150 are connected to the first surface 121 and are located in the first reserved area A1 and the second reserved area A2, respectively. In some embodiments, the first reserved area A1 is adjacent to the edge of the first surface 121 relative to the first chip 141, and the second reserved area A2 is also adjacent to the edge of the first surface 121 relative to the first chip 141. A plurality of connection terminals 124 may be respectively disposed in the first reserved area A1 and the second reserved area A2. The connection terminals 124 may be any one of pads, solder balls, or conductive pillars. In this embodiment, the connection terminals 124 are solder balls. The connection terminals 124 can be used to connect the second chips 150. In addition to the first reserved component area A1 and the second reserved component area A2, other reserved component areas can be provided. These other reserved component areas can be arranged around the first chip 141 to provide multiple functional elements, such as the second chip 150, around the first chip 141.

[0036] The first reserved component area A1 has a first function. The second reserved component area A2 has a second function. In some embodiments, the first function of the first reserved component area A1 is to enable the first chip 141 and the second chip 150 in the first reserved component area A1 to be interconnected via signals from the first reserved component area A1. In this embodiment, the second function of the second reserved component area A2 is the same as the first function of the first reserved component area A1, and the second function of the second reserved component area A2 is to enable the first chip 141 and the second chip 150 in the second reserved component area A2 to be interconnected via signals from the second reserved component area A2.

[0037] By setting reserved areas such as the first reserved area A1 and the second reserved area A2, the second chip 150 can be placed using a chip-last packaging method. This allows the second chip 150 to be mounted in the final stage of production (e.g., on a system assembly plant's SMT (Surface Mount Technology) line), improving production flexibility and increasing the utilization rate of the redistribution layer 120. Using existing silicon interposers leads to increased costs; this application reduces costs by more than 90% by replacing the silicon interposer with a silicon-less redistribution layer 120.

[0038] On the other hand, according to basic electrical theory, the shorter the transmission path between chips, the smaller the parasitic inductance and capacitance, and the larger the eye diagram, meaning that higher-speed signals can be transmitted. From existing 2D, 2.5D to 3D packaging structures, the amount of data that can be transmitted under the same power consumption is increasing, the key reason being that the closer the chips are, the lower the transmission loss. This application uses a redistribution layer 120 to replace the existing FR4PCB to interconnect the first chip 141 and the second chip 150, which can shorten the distance between the first chip 141 and the second chip 150 and reduce the area occupied by the packaging structure. For example, it can be achieved by using a redistribution layer 120 instead of the existing FR4PCB to interconnect the first chip 141 and the second chip 150. Figure 2 95×95=9025mm 2 Reduce to Figure 3B 50×50=2500mm 2 Furthermore, shortening the distance between the first chip 141 and the second chip 150 can also shorten the data transmission path, reduce latency, and improve the overall energy efficiency of the system.

[0039] In some embodiments, the first chip 141 may include a computing chip, such as an XPU. In embodiments where the semiconductor package structure 100A is applied to EDGE AI, the first chip 141 may be referred to as the EDGE AI chip. In some embodiments, the second chip 150 may be a memory chip, such as LPDDR (Double Data Rate Low Power Synchronous Dynamic Random Access Memory) (e.g., LPDDR5), SDRAM, or HBM. That is, the memory chip may be configured using a post-chip packaging approach.

[0040] Due to price fluctuations in memory chips (such as SDRAM), this application employs a post-chip packaging method, enabling memory chips to be mounted in the final stage of production (such as on an SMT line in a system assembly plant), thereby improving production flexibility and reducing costs. Furthermore, the semiconductor packaging structure 100A of this application is suitable not only for standard memory chips but also for customized memory chips, helping customized memory chips to enter the commercial market. Customized memory chips differ from standard memory chips; they increase transmission bandwidth with more I / O, and their original design goal is to stack them top-to-bottom with computing chips (such as XPUs). Given the market's continued concerns about top-to-bottom stacking, the structure of this application allows for optimized packaging of customized memory chips and computing chips. In this embodiment, the transmission path between the computing chip and the memory chip can also be shortened, reducing parasitic inductance and capacitance and transmission losses, thereby increasing the speed and data volume of transmitted signals.

[0041] The third chip 142 can be connected to the second surface 122 of the redistribution layer 120. In some embodiments, the third chip 142 can be disposed opposite to the first chip 141 in the vertical direction, and the third chip 142 can be located within the projection range of the first chip 141 in the vertical direction. In this embodiment, the third chip 142 can be a power management chip, such as a PMIC (Power Management Integrated Circuit) chip. By shortening the distance between the first chip 141 and the second chip 150 and placing the power management chip on the second surface 122, the power transmission path can be further shortened, power loss can be reduced, and overall energy efficiency can be improved.

[0042] In this embodiment, where the first chip 141 is a computing chip and the second chip 150 is a memory chip, heterogeneous integration technology integrates the computing chip, memory chip, and power management chip into a single package structure. This shortens the data transmission path and power transmission path, reduces latency and power loss, and improves the overall system energy efficiency. It can solve the problems of high power consumption and high cost associated with integrating XPU, HBM, and CoWoS in current technologies.

[0043] Specifically, the redistribution layer 120 includes a dielectric layer 128 and conductive lines 129 located within the dielectric layer 128. Multiple connection terminals 124 in the first reserved area A1 can be connected to at least one of the first chip 141 and the third chip 142 via the conductive lines 129. In this embodiment, multiple connection terminals 124 in the second reserved area A2 can also be connected to at least one of the first chip 141 and the third chip 142 via the conductive lines 129. Furthermore, passive components 220 can be connected to the second surface 122 of the redistribution layer 120. Passive components 220 can be, for example, resistors, capacitors, inductors, etc. Depending on design requirements, passive components 220 can be connected to corresponding first chips 141, third chips 142, or connection terminals 124 via the conductive lines 129 of the redistribution layer 120.

[0044] In some embodiments, an interposer 240 is connected beneath the second surface 122 of the redistribution layer 120. The interposer 240 may be located in the edge region of the second surface 122 of the redistribution layer 120. The interposer 240 may include a dielectric layer 242 and conductive vias 244 passing through the dielectric layer 242. The conductive vias 244 may be electrically connected to the redistribution layer 120 and may serve as I / O in the package structure. In one example, the pitch between the conductive vias 244 may be ≥0.28 mm.

[0045] A molding layer 182 may be located on the first surface 121 of the redistribution layer 120, and may be located outside the reserved placement area A1 and cover the first chip 141. A molding layer 184 may cover the second surface 122 of the redistribution layer 120 and cover the third chip 142, passive component 220, and interposer 240, etc. The interposer 240 is surrounded by the molding layer 184, and the surfaces of the interposer 240 and the molding layer 184 facing away from the redistribution layer 120 may be flush. The molding layer 184 may expose the conductive vias 244 of the interposer 240. In one example, the maximum height of the passive component 220 in the vertical direction is 0.8 mm, and the thickness of the molding layer 184 on the second surface 122 may be approximately 1.0 mm.

[0046] In some other embodiments, the molding layer 182 and the second chip 150 may be further encapsulated by another molding layer. After the second chip 150, as a rear component, is bonded to the redistribution layer 120, it will be encapsulated again to form another molding layer to encapsulate the molding layer 182 and the second chip 150. And thus, the first chip 141 will be encapsulated by the molding layer 182 and the other molding layer.

[0047] Figure 4 This is a cross-sectional schematic diagram of a semiconductor package structure 100B according to another embodiment of this application. Figure 4 Several aspects of the illustrated embodiments are related to the above references. Figures 3A to 3B The semiconductor packaging structure described is similar, and the following description is also provided. Figure 4 The differences between the illustrated embodiments are as follows. See also: Figure 4 As shown, in this embodiment, the second chip 150 is connected to the first reserved component area A1, and the connector 152 is connected to the second reserved component area A2. The second chip 150 and the connector 152 are coupled to the connection terminal 124 in the first reserved component area A1 via a back-chip connection.

[0048] In this embodiment, the second function of the second reserved component area A2 is different from the first function of the first reserved component area A1. The first function of the first reserved component area A1 is to enable the second chip 150 to be signal-interconnected with the first chip 141 through the first reserved component area A1, while the second function of the second reserved component area A2 is to enable the connector 152 to be signal-interconnected with an external device through the second reserved component area A2.

[0049] In some embodiments, the second chip 150 may be a memory chip. The connector 152 may be a co-packaged connector. In such embodiments, the semiconductor package structure 100B can be used as a high-speed SerDes (serializer / deserializer), such as a 224GB high-speed SerDes. Given the increasing demand for high-speed SerDes, the semiconductor package structure 100B can be used to post-solder the co-packaged connector via SMT.

[0050] In some other embodiments, the molding layer 182, the second chip 150, and the connector 152 may be further encapsulated by another molding layer. After the second chip 150 and connector 152, as rear-mount components, are bonded to the redistribution layer 120, they can be encapsulated again to form another molding layer to encapsulate the molding layer 182, the second chip 150, and the connector 152. Therefore, the first chip 141 will be encapsulated by the molding layer 182 and the other molding layer.

[0051] It should be understood that Figures 3A to 4 The described embodiments of functional elements, including memory chips and co-package connectors, are merely exemplary. Depending on the different applications and design requirements of the package structure, the functional elements can be any other type of element.

[0052] in addition, Figures 3A to 4 The described embodiment places the computing chip (e.g., first chip 141) and the memory chip (second chip 150) on the same side of the redistribution layer 120. In other embodiments, the computing chip and the memory chip may be placed on different sides of the redistribution layer 120. Figure 5 This is a top view schematic diagram of a semiconductor package structure 200 according to another embodiment of this application. See also Figure 5 As shown, the computing chip (e.g., the first chip 141) and the memory chip (e.g., the third chip 142) are disposed on opposite sides of the redistribution layer 120. Figure 5 In the diagram, the third chip 142 is disposed on the upper side of the redistribution layer 120. The first chip 141 is disposed on the lower side of the redistribution layer 120. The first chip 141 located on the lower side of the redistribution layer 120 is shown in dashed lines.

[0053] More specifically, Figures 6A to 6I A schematic diagram showing different stages during the formation of a semiconductor package structure 200A according to another embodiment of this application is provided. First, see... Figure 6A As shown, a carrier board 602 is provided for carrying the redistribution layer 120. The redistribution layer 120 is formed on the carrier board 602. Then, a third chip 142 is bonded on the second surface 122 of the redistribution layer 120. In this embodiment, the third chip 142 may be a computing chip, such as an XPU chip.

[0054] See Figure 6B As shown, a molding layer 184 is formed on the second surface 122 of the redistribution layer 120. The molding layer 184 covers the second surface 122 and encapsulates the third chip 142. The sidewalls of the molding layer 184 can be vertically aligned with the sidewalls of the redistribution layer 120. See also Figure 6C As shown, another carrier plate 604 is attached to the molding layer 184. Then... Figure 6C The structure shown is flipped; see [link / reference]. Figure 6D As shown. The carrier board 602 is removed, exposing the first surface 121 of the redistribution layer 120.

[0055] See Figure 6E As shown, solder balls 192 are formed on the first surface 121 of the redistribution layer 120, which faces the second surface 122. The solder balls 192 may be disposed adjacent to the edge of the first surface 121. See also... Figure 6F As shown, a first chip 141 is bonded on the first surface 121 of the redistribution layer 120. The first chip 141 may be a memory chip, such as an LPDDR chip.

[0056] See Figure 6G As shown, a molding layer 182 is formed on the first surface 121 of the redistribution layer 120. The molding layer 182 covers the first surface 121 and encapsulates the first chip 141. The sidewalls of the molding layer 182 may be perpendicularly aligned with the sidewalls of the redistribution layer 120. See also Figure 6H As shown, the molding seal layer 182 is ground, and the top portion of the solder ball 192 can be removed, exposing the solder ball 192 to the molding seal layer 182. See also Figure 6I As shown, re-balling is performed, and solder balls 192 are re-formed. In some embodiments, a laser marking process can also be performed. The carrier board 604 is removed. Subsequently, the resulting structure can be cut 608. In this way, a semiconductor package structure 200A is formed using panel-level packaging (PLP) technology. In the semiconductor package structure 200A, the area where the solder balls 192 are located can be used as a first reserved component area A1 and a second reserved component area A2, and the solder balls 192 can be used as connection terminals for connecting functional elements (such as the second chip 150 and connector 152 described above).

[0057] Figures 7A to 7I This diagram illustrates different stages during the formation of another semiconductor package structure 200B, in which the first chip 141 and the third chip 142 are disposed on different sides of the redistribution layer 120.

[0058] See Figures 7A to 7D As shown, in accordance with the above references Figures 6A to 6DSimilar to the description, a redistribution layer 120, a third chip 142 bonded to a second surface 122 of the redistribution layer 120, a molding layer 184 covering the third chip 142, and a carrier board 604 attached to the molding layer 184 are formed.

[0059] Then see Figure 7E As shown, conductive pillars 194 are formed on the first surface 121 of the redistribution layer 120. For example, the conductive pillars 194 can be formed via an SMT process. The conductive pillars 194 can be disposed adjacent to the edge of the first surface 121. See also... Figure 7F As shown, a first chip 141 is bonded on the first surface 121 of the redistribution layer 120. The first chip 141 may be a memory chip, such as an LPDDR chip.

[0060] See Figure 7G As shown, a molding layer 182 is formed on the first surface 121 of the redistribution layer 120. The molding layer 182 covers the first surface 121 and encapsulates the first chip 141. The sidewalls of the molding layer 182 may be perpendicularly aligned with the sidewalls of the redistribution layer 120. See also Figure 7H As shown, the molding seal layer 182 is ground until it is flush with the conductive pillar 194, exposing the conductive pillar 194. See also Figure 7I As shown, then we can proceed with... Figure 7H The obtained structure is subjected to a cutting process to form a semiconductor package structure 200B. In the semiconductor package structure 200B, the area where the conductive post 194 is located can be used as a first reserved component area A1 and a second reserved component area A2, and the conductive post 194 can be used as a connection terminal for connecting functional elements (such as the second chip 150 and connector 152 mentioned above).

[0061] The semiconductor package structures 100A, 100B, 200A, and 200B provided in this application, by using a redistribution layer 120 to replace the existing FR4 PCB to interconnect the computing chip and the memory chip, can shorten the distance between the computing chip and the memory chip, reduce the footprint of the package structure, reduce power loss, and improve data transmission rate. For example, compared with using an FR4 PCB... Figure 2 The area in the middle is 95×95=9025mm 2 The area of ​​semiconductor package structures 100A and 100B, in which the computing chip and memory chip are located on the same side of the redistribution layer 120, can be reduced to 50×50=2500mm². 2 The semiconductor package structures 200A and 200B, where the computing chip and memory chip are located on different sides of the redistribution layer 120, can reduce the area to 45×45=2025mm². 2Furthermore, power savings can reach 16%. For semiconductor package structures 100A and 100B, since the computing chip (first chip 141) and the memory chip (second chip 150) can be located on the same side of the redistribution layer 120, they can be called single-sided fan-out structures; for semiconductor package structures 200A and 200B, since the computing chip (third chip 142) and the memory chip (first chip 141) can be located on different sides of the redistribution layer 120, they can be called double-sided fan-out structures.

[0062] The technical effects of this application can be verified through simulation. This can be achieved using... Figures 8A to 8C The structure shown is used for simulation verification. See also Figure 8A As shown, an FR4 PCB 720 is provided. The conductive lines 722 of the FR4 PCB 720 can be used to connect chips located on the same side of the FR4 PCB 720. This structure corresponds to the prior art structure in which arithmetic chips and memory chips are arranged side by side on an FR4 PCB, and can be called an FR4 side-by-side structure. See also Figure 8B As shown, a redistribution layer 730 is provided. The conductive lines 732 of the redistribution layer 730 can be used to connect chips located on the same side of the redistribution layer 730. This structure can correspond to a single-sided fan-out structure. See also... Figure 8C As shown, a redistribution layer 730' is provided, and the conductive lines 732' of the redistribution layer 730' can be used to connect chips located on the opposite side of the redistribution layer 730'. This structure can correspond to a double-sided fan-out structure. The dielectric constant Dk of the dielectric material of both redistribution layers 730 and 730' is 3, and the dielectric loss factor Df is 0.0019. Figures 8A to 8C As shown, compared to Figure 8A The existing FR4 side-by-side structure, Figure 8B Conductive circuit 732 in the single-sided fan-out structure and Figure 8C The distances of the conductive lines 732' in the double-sided fan-out structure are all shortened. Additionally, for each... Figures 8A to 8C The structure shown was simulated to obtain the following results: Figure 8D The S-parameter insertion loss curve is shown below. Among them, using... Figure 8A The FR4 side-by-side structure yields curve S11, utilizing... Figure 8A The curve S12 is obtained from the single-sided fan-out structure, using Figure 8C The double-sided fan-out structure yields curve S13.

[0063] Further adoption Figures 9A to 9D The simulation verification will be performed as shown. First, see [link / reference]. Figure 9A and Figure 9BAs shown in the dual-fan-out structure 800A, the first chip 841 and the second chip 842 are located on opposite sides of the redistribution layer 820. The redistribution layer 820 includes five metal layers M1-M5. Metal layers M1 and M5 can be ground layers, and the laterally extending conductive lines 829 connecting the first chip 841 and the second chip 842 are located on metal layer M3. See also... Figure 9C and Figure 9D As shown in the FR4 side-by-side structure 800B, the first chip 841 and the second chip 842 are located on the same side of the redistribution layer 820'. The redistribution layer 820' includes six metal layers M1-M6. Metal layers M4 and M6 can be ground layers, and the laterally extending conductive line 829' connecting the first chip 841 and the second chip 842 is located on metal layer M5. The dielectric constant Dk of the dielectric material in the redistribution layers 820 and 820' is both 3, and the dielectric loss factor Df is both 0.0019. [The remaining text appears to be incomplete and requires further context.] Figures 9A to 9D Simulations were performed on the double-sided fan-out structure 800A and the FR4 side-by-side structure 800B shown, and the results were as follows: Figure 9E The insertion loss curve shown is illustrated. Among them, using... Figure 9A and Figure 9B The curve S21 is obtained from the double-sided fan-out structure 800A, using Figure 9C and Figure 9D The FR4 side-by-side structure 800B yields curve S22. Figure 8D and Figure 9E As shown, compared to the existing FR4 side-by-side structure, the single-sided fan-out structure can shorten the data transmission path without adversely affecting the insertion loss; the double-sided fan-out structure can shorten the data transmission path while improving the insertion loss.

[0064] In summary, this technology utilizes advanced packaging methods, combining fan-out, redistribution layers, and panel-level packaging technologies to provide an innovative packaging technology suitable for EDGE AI computing. By implementing system-in-package (SiP) through heterogeneous integration technology, the computing core chip, memory chip, and power management chip are integrated into a single package. This shortens data transmission / power transmission paths, reduces latency, minimizes power loss, and improves overall system energy efficiency. This addresses the memory bandwidth bottleneck while simultaneously balancing cost, performance, and power consumption requirements; that is, it reduces manufacturing costs, improves electrical efficiency and production efficiency, and makes AI chips more widely available.

[0065] This application, by combining double-sided packaging and heterogeneous integration of the redistribution layer, provides a high-bandwidth, low-power, and low-cost solution suitable for various EDGE AI application scenarios. For example, it can be applied to: mobile devices, improving processor and memory integration, enhancing power efficiency and computing performance; intelligent monitoring, providing high-performance AI computing capabilities under low-power conditions; industrial automation, suitable for high-performance EDGE computing needs, improving data processing capabilities; and autonomous driving and ADAS (Advanced Driving Assistance Systems), providing a high-bandwidth, low-power computing architecture to support in-vehicle AI computing requirements.

[0066] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor packaging structure, characterized in that, include: A redistribution layer having a first surface and a second surface opposite to the first surface; and The first chip is connected to the first surface; The first surface of the redistribution layer includes a first reserved component area and a second reserved component area arranged at a distance from the first chip. The first reserved component area has a first function, and the second reserved component area has a second function, wherein the first function and the second function are different.

2. The semiconductor packaging structure according to claim 1, characterized in that, The first reserved component area is provided with a second chip, wherein the first function of the first reserved component area is that the first chip and the second chip are interconnected through the first reserved component area.

3. The semiconductor packaging structure according to claim 2, characterized in that, The second reserved component area is provided with a connector, wherein the second function of the second reserved component area is that the connector is interconnected with an external device through the signal of the second reserved component area.

4. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A molding layer is located on the first surface and covers the first chip, the molding layer being located outside the first reserved component area and the second reserved component area.

5. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: An intermediary layer is connected below the second surface of the redistribution layer.

6. The semiconductor packaging structure according to claim 5, characterized in that, The intermediate layer is located in the edge region of the second surface of the redistribution layer.

7. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: A passive component is connected below the second surface of the redistribution layer.

8. The semiconductor packaging structure according to claim 1, characterized in that, The first reserved area and the second reserved area are located around the first chip, and the first reserved area and the second reserved area are adjacent to the edge of the first chip on the first surface.

9. The semiconductor packaging structure according to claim 1, characterized in that, Also includes: The third chip is located on the second surface of the redistribution layer; The redistribution layer includes a dielectric layer and conductive lines located in the dielectric layer. A plurality of connection terminals in the first reserved area are connected to at least one of the first chip and the third chip through the conductive lines.

10. The semiconductor packaging structure according to claim 9, characterized in that, Also includes: A molding layer is applied to the second surface and encapsulates the third chip.

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