Packaging structure and electronic device

Abstract

The application provides a packaging structure and an electronic device, and relates to the technical field of packaging. The packaging structure comprises a frame, at least two chip units and a packaging body. The frame comprises at least two base islands arranged at intervals. The at least two chip units are arranged in the at least two base islands, and at least one chip unit is arranged in each base island. The chips in different base islands are insulated, and the creepage distance between two adjacent base islands is greater than a first preset value. The packaging body encapsulates the frame and the at least two chip units. The application can improve the integration of the electronic device and facilitate the carrying of the electronic device.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a packaging structure and electronic device. Background Technology

[0002] With the increasing variety of electronic products, universal charging adapters have become an inevitable trend. Among them, flyback switching power supplies are widely used in low-power power supplies and various charging adapters due to their simple circuit structure and low cost.

[0003] In related technologies, flyback switching power supplies typically include a circuit board and multiple chips mounted on the board. The arrangement of these multiple chips ensures safety and stability during charging. However, this layout results in a bulky charging adapter, making it difficult to improve the integration of the adapter and consequently making it inconvenient to carry. Utility Model Content

[0004] In view of the above problems, embodiments of this application provide a packaging structure and an electronic device that can improve the integration of the electronic device and facilitate its portability.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] A first aspect of this application provides a packaging structure, which includes:

[0007] The frame includes at least two spaced-apart base islands;

[0008] At least two chip units are disposed in at least two base islands, and each base island is provided with at least one chip unit; wherein the chips located in different base islands are insulated, and the creepage distance between two adjacent base islands is greater than a first preset value;

[0009] A package that encapsulates the frame and at least two of the chip units.

[0010] In one possible implementation, at least two of the base islands include a first base island and a second base island, with a portion of the chip units of at least two of the chip units mounted on the first base island; and a portion of the chip units of at least two of the chip units mounted on the second base island;

[0011] The second base island is spaced apart from the first base island, and the creepage distance between the first base island and the second base island is greater than the first preset value.

[0012] In one possible implementation, the number of chip units is four, including a first chip, a second chip, a third chip, and a fourth chip. The first chip and the second chip are disposed at intervals on the first base island, and the third chip and the fourth chip are disposed on the second base island. The first chip and the fourth chip are disposed opposite to each other, and the second chip and the third chip are disposed opposite to each other. The second chip and the third chip are control chips.

[0013] In one possible implementation, the packaging structure is applied to a flyback switching power supply; the first chip is a fast charging protocol chip, the second chip is a primary-side controller, the third chip is a secondary-side controller, and the fourth chip is a rectifier diode; the flyback switching power supply also includes a transformer, which includes a primary winding and a secondary winding.

[0014] The primary-side controller is electrically connected to the primary-side winding via the primary-side power transistor and is used to control the on / off state of the primary-side power transistor. The secondary-side controller is electrically connected to the secondary-side winding via the rectifier transistor and is used to control the on / off state of the rectifier transistor.

[0015] The primary-side controller is also connected to the secondary-side controller via the fast charging protocol chip, and is used to receive control signals sent by the secondary-side controller via the fast charging protocol chip. The control signals are used to control the primary-side power transistor to turn on or off.

[0016] In one possible implementation, the package structure further includes a plurality of pins connected to at least two of the chip units, with portions of the plurality of pins located within the package and the remainder located outside the package.

[0017] At least one of the at least two chip units includes a power chip, and at least one of the plurality of pins connected to the power chip constitutes a heat dissipation pin.

[0018] In one possible implementation, the width of the heat dissipation pin is greater than a preset width.

[0019] In one possible implementation, among two pins adjacent to the heat dissipation pin, the distance between one of the pins and the heat dissipation pin is a first distance, and the distance between the other pin and the heat dissipation pin is a second distance;

[0020] The first distance is greater than the second distance.

[0021] In one possible implementation, the base island and / or the pin are provided with a power contact area.

[0022] In one possible implementation, a first molding hole is provided on the heat dissipation pin; a portion of the package is filled into the first molding hole; at least one second molding hole is provided on the frame, and a portion of the package is filled into the second molding hole.

[0023] A second aspect of this application provides an electronic device including a circuit board and a packaging structure including the one described in the first aspect; the packaging structure is disposed on the circuit board.

[0024] In the packaging structure and electronic device provided in this application embodiment, at least two chip units are disposed on a frame, and the frame and at least two chip units are encapsulated by a package to form an integral whole. Compared with the related technology, where the packaging structure includes only a frame and a chip unit, and multiple packaging structures are arranged on a circuit board according to certain rules, the complexity of the circuit board can be reduced, the layout space of the circuit board can be saved, thereby reducing the size of the electronic device and improving the integration of the electronic device.

[0025] In addition, the chip units located in different base islands are insulated, and the creepage distance between two adjacent base islands is greater than a first preset value. This first preset value is used to characterize the minimum value at which signal crosstalk will not occur between two adjacent base islands. This setting helps to reduce the electric field strength between adjacent base islands, prevents breakdown caused by excessive electric field, and further reduces the risk of breakdown.

[0026] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the packaging structure and electronic device provided by the embodiments of this application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific implementation. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A three-dimensional schematic diagram of the packaging structure provided in the embodiments of this application;

[0029] Figure 2 This is a top view of the packaging structure provided in an embodiment of this application;

[0030] Figure 3A schematic diagram illustrating the structure of the frame, pins, and chip units when they are in conjunction, as provided in the embodiments of this application.

[0031] Figure 4 This is a schematic diagram of the structure of the first base island provided in an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of the structure of the second base island provided in an embodiment of this application;

[0033] Figure 6 This is a front view of the packaging structure provided in the embodiments of this application;

[0034] Figure 7 A bottom view of the packaging structure provided in the embodiments of this application;

[0035] Figure 8 A circuit diagram of an electronic device provided in an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures:

[0037] 100: Frame; 110: First base island; 120: Second base island; 130: Second mold-locking hole; 140: Electrical connection area;

[0038] 200: Chip unit; 210: First chip; 220: Second chip; 230: Third chip; 240: Fourth chip;

[0039] 300: Pin; 310: Heat dissipation pin; 311: First mold-locking hole; 320: First base island pin; 330: Second base island pin; 340: First end; 350: Second end;

[0040] 400: Package;

[0041] 500: Transformer; 510: Primary winding; 520: Secondary winding;

[0042] 600: Primary power transistor;

[0043] 700: Output capacitor. Detailed Implementation

[0044] As described in the background section, the charging adapters in the related technologies have the problems of being too large and having low integration. The inventors have found that the reason for this problem is that each chip is usually packaged separately, and then multiple chips are integrated onto a circuit board. This setup increases the area of ​​the circuit board, thereby increasing the size of the charging adapter and reducing its integration.

[0045] To address the aforementioned technical problems, embodiments of this application provide a packaging structure and an electronic device. This structure involves mounting at least two chip units on a frame and then encapsulating the frame and the chip units into a single unit using a package. Compared to related technologies where the packaging structure includes only a frame and one chip unit, and multiple packaging structures are arranged on a circuit board according to certain rules, this approach reduces the complexity of the circuit board, saves layout space, thereby reducing the size of the electronic device and improving its integration.

[0046] In addition, the chip units located in different base islands are insulated, and the creepage distance between two adjacent base islands is greater than a first preset value. This first preset value is used to characterize the minimum value at which signal crosstalk will not occur between two adjacent base islands. This setting helps to reduce the electric field strength between adjacent base islands, prevents breakdown caused by excessive electric field, and further reduces the risk of breakdown.

[0047] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0048] This application provides an electronic device, which includes a circuit board and a packaging structure, with the packaging structure disposed on the circuit board. The electronic device includes, but is not limited to, portable power storage devices, adapters, mobile phone adapters, mobile terminals, remote controls, mobile phones, projectors, etc.

[0049] Please refer to the attached document. Figure 1 To be continued Figure 7 The packaging structure provided in this application embodiment includes a frame 100. The frame 100 serves as the main support for the chip unit 200, and can be used to mount the chip unit 200 and realize the electrical connection between the chip unit 200 and the circuit board.

[0050] The frame 100 includes at least two spaced-apart base islands; that is, the frame 100 may include two, three, or even more base islands. The following embodiments are described using the example of a frame 100 including two base islands. For example, the frame 100 includes a first base island 110 and a second base island 120 spaced apart from each other.

[0051] It should be noted that there are several options for forming at least two base islands in the frame 100. For example, the at least two base islands can be separated by etching during the processing of the frame 100; that is, a substrate can be provided first, and a portion of the substrate can be removed by etching to form at least two spaced base islands. Alternatively, the at least two base islands can be relatively independent separate units, and the frame 100 can be formed by assembling the at least two base islands. This arrangement increases the flexibility of the placement of the at least two base islands, facilitates the installation of at least two chip units 200, and provides a more flexible installation method.

[0052] The packaging structure also includes at least two chip units 200, which are disposed in at least two base islands, with each base island having at least one chip unit 200. That is, when the at least two base islands include a first base island 110 and a second base island 120, a portion of the chip units 200 of the at least two chip units 200 are mounted on the first base island 110; and a portion of the chip units 200 are mounted on the second base island 120, such that both the first base island 110 and the second base island 120 have at least one chip unit 200. For example, there may be two chip units 200, with one chip unit 200 disposed on the first base island 110 and the other chip unit 200 disposed on the second base island 120. Alternatively, there may be three chip units 200, with one chip unit 200 disposed on the first base island 110 and the other two chip units 200 disposed on the second base island 120. For example, the number of chip units 200 may be four; two chip units 200 may be arranged on the first base island 110, and two chip units 200 may be arranged on the second base island 120. As another example, the number of chip units 200 may be five; two chip units 200 may be arranged on the first base island 110, and three chip units 200 may be arranged on the second base island 120. The numbers mentioned above are merely illustrative; the specific arrangement needs to be freely configured according to actual requirements.

[0053] The basic requirement for the arrangement of at least two chip units 200 is that chip units 200 located in different base islands are insulated from each other, and chip units 200 located in the same base island are spaced apart, so as to place chip units 200 that may cause signal interference in different base islands, thereby preventing the aforementioned chip units 200 from causing signal interference and ensuring the performance of the packaging structure.

[0054] In addition, the chip units 200 located in different base islands are insulated, and the creepage distance between two adjacent base islands is greater than a first preset value. The first preset value is used to characterize the minimum value at which signal crosstalk will not occur between two adjacent base islands. This setting helps to reduce the electric field strength between adjacent base islands, prevents breakdown caused by excessive electric field, and further reduces the risk of breakdown.

[0055] Please continue to refer to the appendix. Figure 3 When at least two base islands include a first base island 110 and a second base island 120, the creepage distance between the first base island 110 and the second base island 120 is greater than a first preset value. Here, creepage distance refers to the maximum allowable distance between the first base island 110 and the second base island 120 when the chip unit 200 is in operation, denoted by b. Creepage distance is mainly used to evaluate the performance of the chip unit 200 under high-voltage environments. When the chip unit 200 is in operation, it is necessary to ensure that the creepage distance between the first base island 110 and the second base island 120 is sufficiently large to guarantee the stability and safety of the chip unit 200.

[0056] The first preset value can be calculated based on the vertical distance between the first base island 110 and the second base island 120, denoted by a, and the creepage distance (in mm / kV) obtained from the package 400 filled between the first base island 110 and the second base island 120.

[0057] In package design, vertical distance is a crucial parameter because it directly impacts the performance and reliability of the chip cell 200. It is essential to ensure that the vertical distance between the first base island 110 and the second base island 120 is sufficiently large to prevent unnecessary current leakage between them. This, in turn, can reduce or even prevent voltage breakdown between the first base island 110 and the second base island 120.

[0058] The first preset value is equal to the product of the vertical distance *a* (in mm) between the first base island 110 and the second base island 120 and the creepage distance (in mm / kV). In practical applications, the creepage distance *b* is usually required to be greater than the first preset value. This is to ensure that the chip can still operate normally under high voltage conditions, while avoiding current leakage that could lead to chip performance degradation, and can reduce or even prevent voltage breakdown between the first base island 110 and the second base island 120. To achieve this goal, the chip's materials, processes, and design parameters need to be fully considered to achieve a reasonable layout between the base islands.

[0059] In this embodiment, the vertical distance between the first base island 110 and the second base island 120 can be set to a = 0.6mm ± 0.05mm, depending on actual needs. This distance can be adjusted according to specific circumstances. The vertical distance between the first base island 110 and the second base island 120 must meet the condition of being greater than or equal to 0.55mm and less than or equal to 0.65mm. During the operation of the chip module, this distance ensures that the maximum creepage distance b between the first base island 110 and the second base island 120 is greater than a first preset value.

[0060] Please refer to the attached document. Figure 1 and attached Figure 2 The packaging structure also includes a package body 400, which encapsulates the frame 100 and at least two chip units 200. That is, the package body 400 encapsulates the frame 100 and at least two chip units 200, protecting them. This prevents external moisture from entering the packaging structure and thus from corroding the chip units 200, ensuring the normal operation of the packaging structure. Furthermore, it facilitates transportation and installation of the packaging structure.

[0061] The materials used in the package 400 include epoxy resin, phenolic resin, polyimide, silicone, or spin-coated silicone glass. These materials possess excellent insulation, thermal conductivity, and mechanical strength, effectively blocking the effects of external dust, moisture, and mechanical impact. They also ensure the safe and stable operation of the circuit, effectively dissipate heat, improve the reliability of the package structure, and extend its service life.

[0062] This embodiment involves placing at least two chip units 200 on a frame 100 and encapsulating the frame 100 and the at least two chip units 200 into a single unit using a package. Compared with related technologies where the package structure includes only a frame and a chip unit, and multiple package structures are arranged on a circuit board according to certain rules, this embodiment reduces the complexity of the circuit board, saves layout space, thereby reducing the size of the electronic device and improving its integration.

[0063] When the electronic device is a mobile phone adapter, the size of the mobile phone adapter can be effectively reduced, and it has good heat dissipation performance.

[0064] In one possible implementation, please refer to the appendix. Figure 3 To be continued Figure 5The package structure also includes multiple pins 300, which are used to establish electrical connections between at least two chip units 200 and the circuit board. For example, one end of the pin 300 is connected to the chip unit 200, and the other end is connected to the circuit board. One end of the pin 300 is typically connected to the chip unit 200 via wire bonding, a method that connects the chip's pads to the pin 300 using metal wires. This connection method has the advantages of being simple to operate and inexpensive.

[0065] The metal wire used for lead wires needs to possess good conductivity, ductility, toughness, and corrosion resistance. Commonly used metal wire materials include gold (Au), silver (Ag), copper (Cu), aluminum (Al), and their alloys. Gold wire has excellent conductivity and oxidation resistance; silver wire has good conductivity; copper wire is relatively inexpensive; and aluminum wire is suitable for light-contact bonding. The appropriate metal wire material should be selected based on different application scenarios and cost requirements.

[0066] It is important to understand that the pins 300 and the frame 100 are typically made of copper. This makes it difficult to directly bond wires to the pins 300. Therefore, a contact area 140 needs to be formed on the pins 300 and / or the base island. That is, silver is electroplated onto the pins 300 and / or the base island using an electroplating process to form the contact area 140. The contact area 140 has high conductivity, which facilitates a more stable and reliable electrical connection between the two chip units 200, and between the chip unit 200 and the pins 300.

[0067] The location of the grounding area 140 can be chosen in several ways. For example, the location of the grounding area 140 can be determined based on the relative position of the base island and the pin 300. In one example, when the pin 300 and the base island are spaced apart, the grounding area 140 can be located on the pin 300, or it can be located on both the pin 300 and the base island. For example, the grounding area 140 can be located on the pin 300, with one end of a lead connected to the grounding area 140 located on the pin 300, and the other end of the lead connected to the pad of the chip unit 200, so as to realize the electrical connection between the pin 300 and the chip unit 200, and thus realize the electrical connection between the chip unit 200 and the circuit board through the pin 300. For example, the bonding area 140 is simultaneously located on the pin 300 and the base island. In this case, two leads are used accordingly. One lead connects the pad of the chip unit 200 to the bonding area 140 of the base island, and the other lead connects the bonding area 140 of the base island to the bonding area 140 of the pin 300. This arrangement can improve the flexibility of the bonding lead placement and make it easier to realize the electrical connection between the chip unit 200 and the pin 300.

[0068] In another example, when the base island and pin 300 are connected together, the power contact area 140 can be set on the frame, that is, the power contact area 140 can be directly set at the connection position between the base island and pin 300. With this setting, when one end of the lead is connected to the power contact area 140, it is also connected to the pin 300.

[0069] During the packaging process, a portion of the multiple pins 300 is located inside the package body 400, and the remaining portion is located outside the package body 400. The portion of the multiple pins 300 located inside the package body 400 is used to connect with the chip unit 200, and the portion located outside the package body 400 is used to connect with the circuit board. For example, the pins 300 extending to the outside of the package body 400 can be electrically connected to the corresponding circuit board by means of soldering or other methods.

[0070] It should be noted that the number and function of the multiple pins 300 in this embodiment can be freely set according to the package structure and the type of electronic device. For example, some of the multiple pins 300 can be signal pins; some can be ground pins; and some can be heat dissipation pins.

[0071] For example, at least one of the at least two chip units 200 includes a power chip that generates a significant amount of heat during operation; therefore, at least one of the plurality of pins 300 connected to the power chip constitutes a heat dissipation pin 310. In other words, the power chip is located on that base island, and correspondingly, at least one of the plurality of pins 300 opposite the base island where the power chip is located is a heat dissipation pin 310. For example, please refer to the appendix... Figure 3 and attached Figure 5 At least two base islands include a first base island 110 and a second base island 120, and a power chip is disposed on the second base island 120. Accordingly, at least one of the plurality of pins 300 opposite to the second base island 120 is a heat dissipation pin 310.

[0072] The heat dissipation pin 310 can quickly and effectively conduct the heat generated by the package structure to the outside of the package structure, improving the heat dissipation effect of the package structure and ensuring the stable and reliable function of the chip unit 200. The embodiments of this application can reduce the complexity of the circuit board, simplify the circuit, save chip layout space, reduce costs, and have good heat dissipation performance.

[0073] It should be noted that the number and placement of the heat dissipation pin 310 and the other pins 300 can be designed according to the size of the package structure and the placement of the power chip. For example, most of the other pins 300 can be placed on the base island that does not contain the power chip, thus leaving sufficient layout space for the heat dissipation pin 310 and improving the heat dissipation efficiency of the package structure.

[0074] To improve the heat dissipation effect of the heat dissipation pin 310, the width of the heat dissipation pin 310 is greater than the width of the other pins 300. For example, the width of the heat dissipation pin 310 is greater than a preset width. Specifically, the preset width is twice or more than the width of the conventional pin 300, thus providing a larger heat dissipation area and better heat dissipation. For instance, if the width of pin 300 is approximately 0.5mm, the width of the heat dissipation pin 310 is twice that of pin 300, i.e., the width of the heat dissipation pin 310 is more than 1mm. The width of the heat dissipation pin 310 can also be six times the width of the conventional pin 300, specifically 3mm; or eight times the width of the conventional pin 300, specifically 4mm, etc. The width of the heat dissipation pin 310 is not limited to an integer multiple of the width of the conventional pin 300; the width of the heat dissipation pin 310 can also be 3.1mm, 4.1mm, etc.

[0075] Please continue to refer to the appendix. Figure 2 In the two pins 300 adjacent to the heat dissipation pin 310, the distance between one of the pins 300 and the heat dissipation pin 310 is the first distance, that is, the attached... Figure 2 D1. The distance between the other pin 300 and the heat dissipation pin 310 is the second distance, i.e., the attached distance. Figure 2 D2.

[0076] Among them, the first distance D1 is greater than the second distance D2. (See attached...) Figure 2 Taking the orientation shown as an example, the first distance D1 is greater than the second distance D2, which avoids signal interference between the heat dissipation pin 310 and the pin 300 located to its left, improves the withstand voltage of both, and thus improves the overall withstand voltage performance of the circuit in which the package structure is located.

[0077] It should be noted that the third distance D3 between any two pins 300 in the remaining pins 300 can be equal or unequal, and can be freely set according to the type of package structure.

[0078] Furthermore, given that pin 300 is made of metal, in order to... Figure 2 Taking the orientation shown as an example, and considering the two rightmost and opposite pins, for instance, the two pins 300 have a first end 340 and a second end 350. The creepage distance c between the first end 340 and the second end 350 is greater than a second preset value for the two pins 300 in air, in order to improve the overall withstand voltage performance of the circuit containing the package structure. It should be noted that the method for obtaining the second preset value is the same as that for the first preset value, and will not be elaborated further in this embodiment.

[0079] It should be noted that the pins 300 can be fabricated simultaneously with the base islands. For example, a substrate can be provided first, then the substrate can be patterned, and a portion of the substrate can be removed to form at least two base islands and multiple pins 300. Some of the pins 300 may be spaced apart from the base islands, while others may be interconnected with them.

[0080] Please continue to refer to the appendix. Figure 3 The pin 300 integrally formed with the first base island 110 is designated as the first base island pin 320, and the pin 300 integrally formed with the second base island 120 is designated as the second base island pin 330. Both the first base island pin 320 and the second base island pin 330 include at least one heat dissipation pin 310. That is, when the power chip (fourth chip) is located on the first base island 110, the first base island pin 320 serves as a heat dissipation pin; when the power chip (fourth chip) is located on the second base island 120, the second base island pin 330 serves as a heat dissipation pin. The presence of a heat dissipation pin 310 in both the first and second base island pins increases the width of the corresponding base island pins, thereby increasing the heat dissipation area. The heat dissipation pin 310 can be grounded, which not only dissipates excess heat through the grounding point but also improves the safety of the package structure.

[0081] However, the functions of the first base island pin 320 and the second base island pin 330 are not limited to the functions described above. For example, the first base island pin 320 can be a ground pin 300 or a signal pin 300, depending on the specific requirements. Similarly, the second base island pin 330 can be a ground pin 300 or a signal pin 300, depending on the specific requirements.

[0082] In one possible implementation, a first molding hole 311 is provided on the heat dissipation pin 310. The first molding hole 311 can penetrate one side of the heat dissipation pin 310, so that the first molding hole 311 forms a U-shaped hole. During the packaging process, part of the package body 400 fills into the first molding hole 311 to form a protrusion within the first molding hole 311, constituting a fit between the protrusion and the hole, thereby improving the connection strength between the heat dissipation pin 310 and the package body 400. It should be noted that the number and shape of the first molding holes 311 can be set as needed. A certain number of first molding holes 311 can be provided on the heat dissipation pin 310. For example, the heat dissipation pin 310 can have one first molding hole 311, or it can have two or more first molding holes 311. The shape of the first molding hole 311 can be set as a square hole, a circular hole, a long hole, a fan-shaped hole, or an irregularly shaped hole, etc.

[0083] The frame 100 has at least one second molding hole 130, and part of the package 400 is filled into the second molding hole 130.

[0084] Based on the above examples of this application, the setting of the second locking hole 130 can improve the bonding force between the frame 100 and the package 400, making it less likely for the frame 100 and the package 400 to detach from each other, ensuring the packaging stability of the frame 100, and ensuring the stability of the electrical connection of the chip unit 200 on the frame 100, making it less likely for the electrical connection to fail.

[0085] The second locking hole 130 can be arranged in various ways on at least two base islands. The following will describe in detail the arrangement of at least two base islands, including the first base island 110 and the second base island 120.

[0086] For example, please refer to the appendix. Figure 3 To be continued Figure 5 The first base island 110 may be provided with at least one second molding hole 130. This application uses an example of providing six second molding holes 130 for illustration, but it is not limited to only having six second molding holes 130; it can also have three, four, five, or seven second molding holes 130, etc. The second base island 120 may also be provided with at least one second molding hole 130. This application uses an example of providing three second molding holes 130 for illustration, but it is not limited to only having three second molding holes 130; it can also have two, four, five, or seven second molding holes 130, etc.

[0087] In some examples of this application, the second locking hole 130 is an elongated hole, and there are at least two elongated holes, which are spaced apart, and the orientation of the at least two elongated holes is the same or the orientation of some of the elongated holes is different.

[0088] Based on the examples above in this application, elongated holes offer greater encapsulation stability, and a certain number can be set as needed to further enhance the connection stability between the frame 100 and the package 400. Specifically, the first base island 110 can have six elongated holes in the same direction, or three elongated holes in different directions, to achieve this. Figure 5 Taking the attached diagram as an example, one of the elongated holes is a horizontal elongated hole, and the other two are vertical elongated holes.

[0089] The second locking hole 130 of this application is not limited to the elongated hole in the figure, but can also be a plum blossom-shaped through hole, a square hole, an elliptical hole, a fan-shaped hole or an irregular hole, etc. When at least two second locking holes 130 are provided, the shapes of the second locking holes 130 can be the same, or some of the second locking holes 130 can be set to different shapes.

[0090] In one possible implementation, there are four chip units 200, including a first chip 210, a second chip 220, a third chip 230, and a fourth chip 240. The first chip 210 and the second chip 220 are spaced apart on the first base island 110, and the third chip 230 and the fourth chip 240 are disposed on the second base island 120. The first chip 210 and the fourth chip 240 are disposed opposite each other and are insulated from each other. The second chip 220 is disposed opposite to the third chip 230. The second chip 220 and the third chip 230 are control chips; the fourth chip 240 is a power chip. Therefore, at least one of the multiple pins 300 connected to the second base island 120 is a heat dissipation pin 310.

[0091] In related technologies, since there is no signal interference between the first chip 210 and the fourth chip 240, the first chip 210 and the fourth chip 240 are usually packaged in one package structure, the second chip 220 is packaged in another package structure, and the third chip 230 is packaged in yet another package structure. Integrating three independent package structures onto a circuit board increases the circuit board area, thereby increasing the size of the charging adapter and reducing its integration density.

[0092] Therefore, based on this, this embodiment encapsulates four chip units 200 into a single package structure. Each chip unit 200 has at least one pin connected to it, allowing it to be easily connected to its corresponding circuit and perform its intended function. This arrangement further reduces the complexity of the circuit board, simplifies the circuitry, saves chip layout space, and lowers costs.

[0093] This embodiment also avoids signal interference between the second chip 220 and the third chip 230 by reasonably setting the creepage distance between the first base island 110 and the second base island 120, thereby reducing the requirements for the selection of the setting position of each chip unit 200 and increasing the flexibility of the setting position of each chip unit 200.

[0094] In one possible implementation, the package structure is applied to a flyback switching power supply, where the first chip 210 is a fast charging protocol chip, the second chip 220 is a primary-side controller, the third chip 230 is a secondary-side controller, and the fourth chip 240 is a rectifier diode.

[0095] Please refer to the attached document. Figure 8The flyback switching power supply also includes a transformer 500, which includes a primary winding 510 and a secondary winding 520. The primary controller is electrically connected to the primary winding 510 through a primary power transistor 600. That is, the primary power transistor 600 includes a gate terminal, a source terminal, and a drain terminal. The output terminal of the primary controller is connected to the gate terminal of the primary power transistor 600, and the drain terminal of the primary power transistor 600 is connected to the primary winding 510.

[0096] The secondary controller is electrically connected to the secondary winding 520 via the rectifier diode and is used to control the switching of the rectifier diode. In other words, the rectifier diode includes a gate terminal, a drain terminal, and a source terminal. The output terminal of the secondary controller is connected to the gate terminal of the rectifier diode, and the drain terminal of the rectifier diode is connected to the secondary winding 520.

[0097] The primary-side controller is connected to the secondary-side controller via a fast-charging protocol chip. The secondary-side controller is configured to send control signals to the primary-side controller via the fast-charging protocol chip. The control signals are used to control the primary-side power transistor 600 to turn on or off. For example, the fast-charging protocol chip is used to modulate and / or demodulate the control signals sent by the secondary-side controller into signals that the primary-side controller can receive, and then transmit the converted signals to the primary-side controller.

[0098] When the primary-side controller controls the primary-side power transistor 600 to be in the conducting state, the voltage difference across the primary winding 510 is VIN, and the voltage across the corresponding terminal of the secondary winding 520 is VOUT + VIN / N, where N is the turns ratio of the flyback converter. At this time, the secondary-side controller controls the rectifier transistor to be in the cutoff state, and electrical energy is converted into magnetic energy and stored in the transformer 500. When the primary-side controller controls the primary-side power transistor 600 to be in the cutoff state, since the current in the primary winding 510 cannot change abruptly, the voltage difference across the primary winding 510 reverses, and the voltage difference across the secondary winding 520 also reverses. The secondary-side controller then controls the rectifier transistor to be in the conducting state, and the output capacitor 700 supplies power.

[0099] Please refer to the appendix. Figure 3 Given that this example integrates four chip units 200 into the same package structure, and that the package structure is applied to a flyback switching power supply, the positional relationship of the four chip units 200 is defined in this embodiment.

[0100] For example, in the direction perpendicular to the first base island 110 pointing to the second base island 120, i.e., attached Figure 3In the X direction, the first chip 210 and the second chip 220 are offset, and the third chip 230 and the fourth chip 240 are offset. Also, in the direction from the first base island 110 to the second base island 120, the first chip 210 and the fourth chip 240 are offset, and the second chip 220 and the third chip 230 are offset. Given that this example has reasonably set the creepage distance between the first base island 110 and the second base island 120, avoiding signal interference between the second chip 220 and the third chip 230, reducing the requirements for the selection of the setting position of each chip unit 200, the flexibility of the setting position of each chip unit 200 can be increased.

[0101] It should be noted that the above embodiments are all described using four chip units 200 as an example. However, the number of chip units 200 provided in this embodiment can also be five. For example, the five chip units 200 can be a primary-side controller, a GaN device, a secondary-side controller, a rectifier diode, and a fast-charging protocol chip, respectively. GaN (gallium nitride) devices are semiconductor materials with excellent physical and chemical properties. GaN devices are widely used in electronics, optoelectronics, energy, and other fields.

[0102] GaN devices mainly have two structures: heterostructure and homostructure.

[0103] Heterogeneous structures: Heterogeneous structures refer to structures where one material is grown on top of another. In GaN devices, heterogeneous structures typically consist of a GaN thin film and a substrate (such as silicon or sapphire). This structure exhibits high thermal conductivity, good electron mobility, and high breakdown voltage, giving GaN devices superior performance in high-temperature, high-power, and high-frequency applications.

[0104] Homogeneous structures: Homogeneous structures refer to structures fabricated from the same material. GaN homogeneous structures mainly include nanowires, nanoribbons, and nanosheets. Compared to heterogeneous structures, homogeneous structures have a larger surface area, and therefore can play an important role in optoelectronic devices, energy devices, and other fields.

[0105] The GaN device of this application can be a homogeneous GaN device.

[0106] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0107] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A package structure, characterized by, include: The frame includes at least two spaced-apart base islands; At least two chip units are disposed in at least two base islands, and each base island is provided with at least one chip unit; wherein the chips located in different base islands are insulated, and the creepage distance between two adjacent base islands is greater than a first preset value; A package that encapsulates the frame and at least two of the chip units.

2. The package structure of claim 1, wherein, At least two of the base islands include a first base island and a second base island, and a portion of the chip units of at least two of the chip units are mounted on the first base island; a portion of the chip units of at least two of the chip units are mounted on the second base island; The second base island is spaced apart from the first base island, and the creepage distance between the first base island and the second base island is greater than the first preset value.

3. The package structure of claim 2, wherein, The number of chip units is four, including a first chip, a second chip, a third chip, and a fourth chip. The first chip and the second chip are disposed at intervals on the first base island, and the third chip and the fourth chip are disposed on the second base island. The first chip and the fourth chip are disposed opposite to each other, and the second chip and the third chip are disposed opposite to each other. The second chip and the third chip are control chips.

4. The package structure of claim 3, wherein, The packaging structure is applied to a flyback switching power supply; the first chip is a fast charging protocol chip, the second chip is a primary-side controller, the third chip is a secondary-side controller, and the fourth chip is a rectifier diode; the flyback switching power supply also includes a transformer, which includes a primary winding and a secondary winding; The primary-side controller is electrically connected to the primary-side winding via the primary-side power transistor and is used to control the on / off state of the primary-side power transistor. The secondary-side controller is electrically connected to the secondary-side winding via the rectifier transistor and is used to control the on / off state of the rectifier transistor. The primary-side controller is also connected to the secondary-side controller via the fast charging protocol chip, and is used to receive control signals sent by the secondary-side controller via the fast charging protocol chip. The control signals are used to control the primary-side power transistor to turn on or off.

5. The package structure of any one of claims 1-4, wherein, The packaging structure further includes multiple pins, which are connected to at least two of the chip units, with portions of the multiple pins located inside the package and the remainder located outside the package. At least one of the at least two chip units includes a power chip, and at least one of the plurality of pins connected to the power chip constitutes a heat dissipation pin.

6. The package structure of claim 5, wherein, The width of the heat dissipation pin is greater than the preset width.

7. The package structure of claim 6, wherein, In the two pins adjacent to the heat dissipation pin, the distance between one of the pins and the heat dissipation pin is a first distance, and the distance between the other pin and the heat dissipation pin is a second distance; The first distance is greater than the second distance.

8. The package structure of claim 5, wherein, The base island and / or the pin are provided with a power contact area.

9. The package structure of claim 5, wherein, A first molding hole is provided on the heat dissipation pin; a portion of the package body is filled into the first molding hole; The frame has at least one second molding hole, and part of the package is filled into the second molding hole.

10. An electronic device, comprising: A circuit board and a package structure according to any one of claims 1-9; the package structure is disposed on the circuit board.

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